4 compatible = "mediatek,mtk7621-soc";
8 compatible = "mips,mips1004Kc";
12 compatible = "mips,mips1004Kc";
18 #interrupt-cells = <1>;
20 compatible = "mti,cpu-interrupt-controller";
24 compatible = "palmbus";
25 reg = <0x1E000000 0x100000>;
26 ranges = <0x0 0x1E000000 0x0FFFFF>;
32 compatible = "mtk,mt7621-sysc";
37 compatible = "mtk,mt7621-wdt";
45 compatible = "mtk,mt7621-gpio";
50 compatible = "mtk,mt7621-gpio-bank";
57 compatible = "mtk,mt7621-gpio-bank";
64 compatible = "mtk,mt7621-gpio-bank";
71 compatible = "mtk,mt7621-memc";
76 compatible = "ns16550a";
79 interrupt-parent = <&gic>;
90 compatible = "ralink,mt7621-spi";
93 resets = <&rstctrl 18>;
99 pinctrl-names = "default";
100 pinctrl-0 = <&spi_pins>;
103 #address-cells = <1>;
106 spi-max-frequency = <10000000>;
107 m25p,chunked-io = <32>;
113 compatible = "ralink,rt2880-pinmux";
114 pinctrl-names = "default";
115 pinctrl-0 = <&state_default>;
116 state_default: pinctrl0 {
120 ralink,group = "spi";
121 ralink,function = "spi";
126 lantiq,group = "i2c";
127 lantiq,function = "i2c";
132 ralink,group = "uart1";
133 ralink,function = "uart";
138 ralink,group = "uart2";
139 ralink,function = "uart";
144 ralink,group = "uart3";
145 ralink,function = "uart";
148 rgmii1_pins: rgmii1 {
150 ralink,group = "rgmii1";
151 ralink,function = "rgmii";
154 rgmii2_pins: rgmii2 {
156 ralink,group = "rgmii2";
157 ralink,function = "rgmii";
162 ralink,group = "mdio";
163 ralink,function = "mdio";
168 ralink,group = "pcie";
169 ralink,function = "pcie rst";
174 ralink,group = "spi";
175 ralink,function = "nand";
178 ralink,group = "sdhci";
179 ralink,function = "nand";
184 ralink,group = "sdhci";
185 ralink,function = "sdhci";
191 compatible = "ralink,rt2880-reset";
196 compatible = "ralink,mt7620-sdhci";
197 reg = <0x1E130000 4000>;
199 interrupt-parent = <&gic>;
206 compatible = "xhci-platform";
207 reg = <0x1E1C0000 4000>;
209 interrupt-parent = <&gic>;
214 #address-cells = <0>;
215 #interrupt-cells = <1>;
216 interrupt-controller;
217 compatible = "ralink,mt7621-gic";
218 reg = < 0x1fbc0000 0x80 /* gic */
219 0x1fbf0000 0x8000 /* cpc */
220 0x1fbf8000 0x8000 /* gpmc */
225 compatible = "mtk,mt7621-nand";
227 reg = <0x1e003000 0x800
229 #address-cells = <1>;
234 reg = <0x00000 0x80000>; /* 64 KB */
238 reg = <0x80000 0x80000>; /* 64 KB */
242 reg = <0x100000 0x40000>;
246 reg = <0x140000 0xec0000>;
251 compatible = "ralink,mt7621-eth";
252 reg = <0x1e100000 10000>;
254 #address-cells = <1>;
257 resets = <&rstctrl 6 &rstctrl 23>;
258 reset-names = "fe", "eth";
260 interrupt-parent = <&gic>;
264 #address-cells = <1>;
267 phy1f: ethernet-phy@1f {
275 compatible = "ralink,mt7620a-gsw";
276 reg = <0x1e110000 8000>;
277 interrupt-parent = <&gic>;
282 compatible = "mediatek,mt7621-pci";
283 reg = <0x1e140000 0x100
286 #address-cells = <3>;
289 pinctrl-names = "default";
290 pinctrl-0 = <&pcie_pins>;
296 0x02000000 0 0x00000000 0x60000000 0 0x10000000 /* pci memory */
297 0x01000000 0 0x00000000 0x1e160000 0 0x00010000 /* io space */
303 reg = <0x0000 0 0 0 0>;
305 #address-cells = <3>;
312 reg = <0x0800 0 0 0 0>;
314 #address-cells = <3>;
321 reg = <0x1000 0 0 0 0>;
323 #address-cells = <3>;