1 #include <dt-bindings/interrupt-controller/mips-gic.h>
6 compatible = "mediatek,mtk7621-soc";
10 compatible = "mips,mips1004Kc";
14 compatible = "mips,mips1004Kc";
20 #interrupt-cells = <1>;
22 compatible = "mti,cpu-interrupt-controller";
26 compatible = "palmbus";
27 reg = <0x1E000000 0x100000>;
28 ranges = <0x0 0x1E000000 0x0FFFFF>;
34 compatible = "mtk,mt7621-sysc";
39 compatible = "mtk,mt7621-wdt";
47 compatible = "mtk,mt7621-gpio";
52 compatible = "mtk,mt7621-gpio-bank";
59 compatible = "mtk,mt7621-gpio-bank";
66 compatible = "mtk,mt7621-gpio-bank";
73 compatible = "mtk,mt7621-memc";
78 compatible = "mtk,mt7621-cpc";
79 reg = <0x1fbf0000 0x8000>;
83 compatible = "mtk,mt7621-mc";
84 reg = <0x1fbf8000 0x8000>;
88 compatible = "ns16550a";
91 interrupt-parent = <&gic>;
92 interrupts = <GIC_SHARED 26 IRQ_TYPE_LEVEL_HIGH>;
102 compatible = "ralink,mt7621-spi";
105 resets = <&rstctrl 18>;
108 #address-cells = <1>;
111 pinctrl-names = "default";
112 pinctrl-0 = <&spi_pins>;
115 #address-cells = <1>;
118 spi-max-frequency = <10000000>;
119 m25p,chunked-io = <32>;
125 compatible = "ralink,rt2880-pinmux";
126 pinctrl-names = "default";
127 pinctrl-0 = <&state_default>;
129 state_default: pinctrl0 {
134 ralink,group = "spi";
135 ralink,function = "spi";
141 ralink,group = "i2c";
142 ralink,function = "i2c";
148 ralink,group = "uart1";
149 ralink,function = "uart1";
155 ralink,group = "uart2";
156 ralink,function = "uart2";
162 ralink,group = "uart3";
163 ralink,function = "uart3";
167 rgmii1_pins: rgmii1 {
169 ralink,group = "rgmii1";
170 ralink,function = "rgmii1";
174 rgmii2_pins: rgmii2 {
176 ralink,group = "rgmii2";
177 ralink,function = "rgmii2";
183 ralink,group = "mdio";
184 ralink,function = "mdio";
190 ralink,group = "pcie";
191 ralink,function = "pcie rst";
197 ralink,group = "spi";
198 ralink,function = "nand1";
202 ralink,group = "sdhci";
203 ralink,function = "nand2";
209 ralink,group = "sdhci";
210 ralink,function = "sdhci";
216 compatible = "ralink,rt2880-reset";
221 compatible = "ralink,mt7620-sdhci";
222 reg = <0x1E130000 4000>;
224 interrupt-parent = <&gic>;
225 interrupts = <GIC_SHARED 20 IRQ_TYPE_LEVEL_HIGH>;
231 compatible = "xhci-platform";
232 reg = <0x1E1C0000 4000>;
234 interrupt-parent = <&gic>;
235 interrupts = <GIC_SHARED 22 IRQ_TYPE_LEVEL_HIGH>;
238 gic: interrupt-controller@1fbc0000 {
239 compatible = "mti,gic";
240 reg = <0x1fbc0000 0x80>;
242 interrupt-controller;
243 #interrupt-cells = <3>;
245 mti,reserved-cpu-vectors = <7>;
249 compatible = "mtk,mt7621-nand";
251 reg = <0x1e003000 0x800
253 #address-cells = <1>;
258 reg = <0x00000 0x80000>; /* 64 KB */
263 reg = <0x80000 0x80000>; /* 64 KB */
268 reg = <0x100000 0x40000>;
273 reg = <0x140000 0xec0000>;
278 compatible = "ralink,mt7621-eth";
279 reg = <0x1e100000 10000>;
281 #address-cells = <1>;
284 resets = <&rstctrl 6 &rstctrl 23>;
285 reset-names = "fe", "eth";
287 interrupt-parent = <&gic>;
288 interrupts = <GIC_SHARED 3 IRQ_TYPE_LEVEL_HIGH>;
291 #address-cells = <1>;
294 phy1f: ethernet-phy@1f {
302 compatible = "ralink,mt7620a-gsw";
303 reg = <0x1e110000 8000>;
304 interrupt-parent = <&gic>;
305 interrupts = <GIC_SHARED 23 IRQ_TYPE_LEVEL_HIGH>;
309 compatible = "mediatek,mt7621-pci";
310 reg = <0x1e140000 0x100
313 #address-cells = <3>;
316 pinctrl-names = "default";
317 pinctrl-0 = <&pcie_pins>;
323 0x02000000 0 0x00000000 0x60000000 0 0x10000000 /* pci memory */
324 0x01000000 0 0x00000000 0x1e160000 0 0x00010000 /* io space */
327 interrupt-parent = <&gic>;
328 interrupts = <GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH
329 GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH
330 GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
335 reg = <0x0000 0 0 0 0>;
337 #address-cells = <3>;
344 reg = <0x0800 0 0 0 0>;
346 #address-cells = <3>;
353 reg = <0x1000 0 0 0 0>;
355 #address-cells = <3>;