1 #include <linux/types.h>
4 #include <linux/init.h>
6 #include <asm/mach-ralink/rt288x.h>
7 #include <asm/mach-ralink/rt288x_regs.h>
9 #define RT2880_PCI_SLOT1_BASE 0x20000000
11 #define RT2880_PCI_REG_PCICFG_ADDR 0x00
12 #define RT2880_PCI_REG_PCIMSK_ADDR 0x0c
13 #define RT2880_PCI_REG_BAR0SETUP_ADDR 0x10
14 #define RT2880_PCI_REG_IMBASEBAR0_ADDR 0x18
15 #define RT2880_PCI_REG_CONFIG_ADDR 0x20
16 #define RT2880_PCI_REG_CONFIG_DATA 0x24
17 #define RT2880_PCI_REG_MEMBASE 0x28
18 #define RT2880_PCI_REG_IOBASE 0x2c
19 #define RT2880_PCI_REG_ID 0x30
20 #define RT2880_PCI_REG_CLASS 0x34
21 #define RT2880_PCI_REG_SUBID 0x38
22 #define RT2880_PCI_REG_ARBCTL 0x80
24 #define PCI_ACCESS_READ 0
25 #define PCI_ACCESS_WRITE 1
27 void __iomem
*rt2880_pci_base
;
29 static u32
rt2880_pci_reg_read(u32 reg
)
31 return readl(rt2880_pci_base
+ reg
);
34 static void rt2880_pci_reg_write(u32 val
, u32 reg
)
36 writel(val
, rt2880_pci_base
+ reg
);
39 static void config_access(unsigned char access_type
, struct pci_bus
*bus
,
40 unsigned int devfn
, unsigned char where
, u32
*data
)
42 unsigned int slot
= PCI_SLOT(devfn
);
44 u8 func
= PCI_FUNC(devfn
);
46 address
= (bus
->number
<< 16) | (slot
<< 11) | (func
<< 8) |
47 (where
& 0xfc) | 0x80000000;
49 rt2880_pci_reg_write(address
, RT2880_PCI_REG_CONFIG_ADDR
);
50 if (access_type
== PCI_ACCESS_WRITE
)
51 rt2880_pci_reg_write(*data
, RT2880_PCI_REG_CONFIG_DATA
);
53 *data
= rt2880_pci_reg_read(RT2880_PCI_REG_CONFIG_DATA
);
56 static int rt2880_pci_config_read(struct pci_bus
*bus
, unsigned int devfn
,
57 int where
, int size
, u32
*val
)
61 config_access(PCI_ACCESS_READ
, bus
, devfn
, where
, &data
);
64 *val
= (data
>> ((where
& 3) << 3)) & 0xff;
66 *val
= (data
>> ((where
& 3) << 3)) & 0xffff;
70 return PCIBIOS_SUCCESSFUL
;
73 static int rt2880_pci_config_write(struct pci_bus
*bus
, unsigned int devfn
,
74 int where
, int size
, u32 val
)
81 config_access(PCI_ACCESS_READ
, bus
, devfn
, where
, &data
);
83 data
= (data
& ~(0xff << ((where
& 3) << 3))) |
84 (val
<< ((where
& 3) << 3));
86 data
= (data
& ~(0xffff << ((where
& 3) << 3))) |
87 (val
<< ((where
& 3) << 3));
90 config_access(PCI_ACCESS_WRITE
, bus
, devfn
, where
, &data
);
92 return PCIBIOS_SUCCESSFUL
;
95 static struct pci_ops rt2880_pci_ops
= {
96 .read
= rt2880_pci_config_read
,
97 .write
= rt2880_pci_config_write
,
100 static struct resource rt2880_pci_io_resource
= {
101 .name
= "PCI MEM space",
104 .flags
= IORESOURCE_MEM
,
107 static struct resource rt2880_pci_mem_resource
= {
108 .name
= "PCI IO space",
111 .flags
= IORESOURCE_IO
,
114 static struct pci_controller rt2880_pci_controller
= {
115 .pci_ops
= &rt2880_pci_ops
,
116 .mem_resource
= &rt2880_pci_io_resource
,
117 .io_resource
= &rt2880_pci_mem_resource
,
120 void inline read_config(unsigned long bus
, unsigned long dev
,
121 unsigned long func
, unsigned long reg
,
124 unsigned long address
;
126 address
= (bus
<< 16) | (dev
<< 11) | (func
<< 8) | (reg
& 0xfc) |
128 rt2880_pci_reg_write(address
, RT2880_PCI_REG_CONFIG_ADDR
);
129 *val
= rt2880_pci_reg_read(RT2880_PCI_REG_CONFIG_DATA
);
132 void inline write_config(unsigned long bus
, unsigned long dev
,
133 unsigned long func
, unsigned long reg
,
136 unsigned long address
;
138 address
= (bus
<< 16) | (dev
<< 11) | (func
<< 8) | (reg
& 0xfc) |
140 rt2880_pci_reg_write(address
, RT2880_PCI_REG_CONFIG_ADDR
);
141 rt2880_pci_reg_write(val
, RT2880_PCI_REG_CONFIG_DATA
);
144 int __init
pcibios_map_irq(const struct pci_dev
*dev
, u8 slot
, u8 pin
)
150 if (dev
->bus
->number
!= 0)
153 switch (PCI_SLOT(dev
->devfn
)) {
155 write_config(0, 0, 0, PCI_BASE_ADDRESS_0
, 0x08000000);
156 read_config(0, 0, 0, PCI_BASE_ADDRESS_0
, &val
);
159 irq
= RT288X_CPU_IRQ_PCI
;
162 printk("%s:%s[%d] trying to alloc unknown pci irq\n",
163 __FILE__
, __func__
, __LINE__
);
168 pci_write_config_byte((struct pci_dev
*)dev
, PCI_CACHE_LINE_SIZE
, 0x14);
169 pci_write_config_byte((struct pci_dev
*)dev
, PCI_LATENCY_TIMER
, 0xFF);
170 pci_read_config_word((struct pci_dev
*)dev
, PCI_COMMAND
, &cmd
);
171 cmd
|= PCI_COMMAND_MASTER
| PCI_COMMAND_IO
| PCI_COMMAND_MEMORY
|
172 PCI_COMMAND_INVALIDATE
| PCI_COMMAND_FAST_BACK
|
173 PCI_COMMAND_SERR
| PCI_COMMAND_WAIT
| PCI_COMMAND_PARITY
;
174 pci_write_config_word((struct pci_dev
*)dev
, PCI_COMMAND
, cmd
);
175 pci_write_config_byte((struct pci_dev
*)dev
, PCI_INTERRUPT_LINE
,
180 static int __init
rt2880_pci_init(void)
182 unsigned long val
= 0;
185 rt2880_pci_base
= ioremap_nocache(RT2880_PCI_BASE
, PAGE_SIZE
);
187 rt2880_pci_reg_write(0, RT2880_PCI_REG_PCICFG_ADDR
);
188 for(i
= 0; i
< 0xfffff; i
++) {}
190 rt2880_pci_reg_write(0x79, RT2880_PCI_REG_ARBCTL
);
191 rt2880_pci_reg_write(0x07FF0001, RT2880_PCI_REG_BAR0SETUP_ADDR
);
192 rt2880_pci_reg_write(RT2880_PCI_SLOT1_BASE
, RT2880_PCI_REG_MEMBASE
);
193 rt2880_pci_reg_write(0x00460000, RT2880_PCI_REG_IOBASE
);
194 rt2880_pci_reg_write(0x08000000, RT2880_PCI_REG_IMBASEBAR0_ADDR
);
195 rt2880_pci_reg_write(0x08021814, RT2880_PCI_REG_ID
);
196 rt2880_pci_reg_write(0x00800001, RT2880_PCI_REG_CLASS
);
197 rt2880_pci_reg_write(0x28801814, RT2880_PCI_REG_SUBID
);
198 rt2880_pci_reg_write(0x000c0000, RT2880_PCI_REG_PCIMSK_ADDR
);
199 write_config(0, 0, 0, PCI_BASE_ADDRESS_0
, 0x08000000);
200 read_config(0, 0, 0, PCI_BASE_ADDRESS_0
, &val
);
202 register_pci_controller(&rt2880_pci_controller
);
206 int pcibios_plat_dev_init(struct pci_dev
*dev
)
211 struct pci_fixup pcibios_fixups
[] = {
215 arch_initcall(rt2880_pci_init
);