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ramips: fix kernel module build errors on linux 5.15
[openwrt/staging/mkresin.git] / target / linux / ramips / files / drivers / mmc / host / mtk-mmc / sd.c
1 /* Copyright Statement:
2 *
3 * This software/firmware and related documentation ("MediaTek Software") are
4 * protected under relevant copyright laws. The information contained herein
5 * is confidential and proprietary to MediaTek Inc. and/or its licensors.
6 * Without the prior written permission of MediaTek inc. and/or its licensors,
7 * any reproduction, modification, use or disclosure of MediaTek Software,
8 * and information contained herein, in whole or in part, shall be strictly prohibited.
9 *
10 * MediaTek Inc. (C) 2010. All rights reserved.
11 *
12 * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
13 * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
14 * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
15 * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
16 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
17 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
18 * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
19 * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
20 * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
21 * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
22 * THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
23 * CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
24 * SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
25 * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
26 * CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
27 * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
28 * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
29 * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
30 *
31 * The following software/firmware and/or related documentation ("MediaTek Software")
32 * have been modified by MediaTek Inc. All revisions are subject to any receiver's
33 * applicable license agreements with MediaTek Inc.
34 */
35
36 #include <linux/module.h>
37 #include <linux/delay.h>
38 #include <linux/dma-mapping.h>
39 #include <linux/spinlock.h>
40 #include <linux/platform_device.h>
41 #include <linux/interrupt.h>
42 #include <linux/of.h>
43
44 #include <linux/mmc/host.h>
45 #include <linux/mmc/mmc.h>
46 #include <linux/mmc/sd.h>
47 #include <linux/mmc/sdio.h>
48
49 #include <asm/mach-ralink/ralink_regs.h>
50
51 #include "board.h"
52 #include "dbg.h"
53 #include "mt6575_sd.h"
54
55 //#define IRQ_SDC 14 //MT7620 /*FIXME*/
56 #ifdef CONFIG_SOC_MT7621
57 #define RALINK_SYSCTL_BASE 0xbe000000
58 #define RALINK_MSDC_BASE 0xbe130000
59 #else
60 #define RALINK_SYSCTL_BASE 0xb0000000
61 #define RALINK_MSDC_BASE 0xb0130000
62 #endif
63 #define IRQ_SDC 22 /*FIXME*/
64
65 #define DRV_NAME "mtk-sd"
66
67 #if defined(CONFIG_SOC_MT7620)
68 #define HOST_MAX_MCLK (48000000) /* +/- by chhung */
69 #elif defined(CONFIG_SOC_MT7621)
70 #define HOST_MAX_MCLK (50000000) /* +/- by chhung */
71 #endif
72 #define HOST_MIN_MCLK (260000)
73
74 #define HOST_MAX_BLKSZ (2048)
75
76 #define MSDC_OCR_AVAIL (MMC_VDD_28_29 | MMC_VDD_29_30 | MMC_VDD_30_31 | MMC_VDD_31_32 | MMC_VDD_32_33)
77
78 #define GPIO_PULL_DOWN (0)
79 #define GPIO_PULL_UP (1)
80
81 #if 0 /* --- by chhung */
82 #define MSDC_CLKSRC_REG (0xf100000C)
83 #define PDN_REG (0xF1000010)
84 #endif /* end of --- */
85
86 #define DEFAULT_DEBOUNCE (8) /* 8 cycles */
87 #define DEFAULT_DTOC (40) /* data timeout counter. 65536x40 sclk. */
88
89 #define CMD_TIMEOUT (HZ / 10) /* 100ms */
90 #define DAT_TIMEOUT (HZ / 2 * 5) /* 500ms x5 */
91
92 #define MAX_DMA_CNT (64 * 1024 - 512) /* a single transaction for WIFI may be 50K*/
93
94 #define MAX_GPD_NUM (1 + 1) /* one null gpd */
95 #define MAX_BD_NUM (1024)
96 #define MAX_BD_PER_GPD (MAX_BD_NUM)
97
98 #define MAX_HW_SGMTS (MAX_BD_NUM)
99 #define MAX_PHY_SGMTS (MAX_BD_NUM)
100 #define MAX_SGMT_SZ (MAX_DMA_CNT)
101 #define MAX_REQ_SZ (MAX_SGMT_SZ * 8)
102
103 static int cd_active_low = 1;
104
105 //=================================
106 #define PERI_MSDC0_PDN (15)
107 //#define PERI_MSDC1_PDN (16)
108 //#define PERI_MSDC2_PDN (17)
109 //#define PERI_MSDC3_PDN (18)
110
111 #if 0 /* --- by chhung */
112 /* gate means clock power down */
113 static int g_clk_gate = 0;
114 #define msdc_gate_clock(id) \
115 do { \
116 g_clk_gate &= ~(1 << ((id) + PERI_MSDC0_PDN)); \
117 } while (0)
118 /* not like power down register. 1 means clock on. */
119 #define msdc_ungate_clock(id) \
120 do { \
121 g_clk_gate |= 1 << ((id) + PERI_MSDC0_PDN); \
122 } while (0)
123
124 // do we need sync object or not
125 void msdc_clk_status(int *status)
126 {
127 *status = g_clk_gate;
128 }
129 #endif /* end of --- */
130
131 /* +++ by chhung */
132 struct msdc_hw msdc0_hw = {
133 .clk_src = 0,
134 .flags = MSDC_CD_PIN_EN | MSDC_REMOVABLE,
135 // .flags = MSDC_WP_PIN_EN | MSDC_CD_PIN_EN | MSDC_REMOVABLE,
136 };
137
138 /* end of +++ */
139
140 static int msdc_rsp[] = {
141 0, /* RESP_NONE */
142 1, /* RESP_R1 */
143 2, /* RESP_R2 */
144 3, /* RESP_R3 */
145 4, /* RESP_R4 */
146 1, /* RESP_R5 */
147 1, /* RESP_R6 */
148 1, /* RESP_R7 */
149 7, /* RESP_R1b */
150 };
151
152 #define msdc_txfifocnt() ((sdr_read32(MSDC_FIFOCS) & MSDC_FIFOCS_TXCNT) >> 16)
153 #define msdc_rxfifocnt() ((sdr_read32(MSDC_FIFOCS) & MSDC_FIFOCS_RXCNT) >> 0)
154 #define msdc_fifo_write32(v) sdr_write32(MSDC_TXDATA, (v))
155 #define msdc_fifo_write8(v) sdr_write8(MSDC_TXDATA, (v))
156 #define msdc_fifo_read32() sdr_read32(MSDC_RXDATA)
157 #define msdc_fifo_read8() sdr_read8(MSDC_RXDATA)
158
159 #define msdc_dma_on() sdr_clr_bits(MSDC_CFG, MSDC_CFG_PIO)
160
161 #define msdc_retry(expr, retry, cnt) \
162 do { \
163 int backup = cnt; \
164 while (retry) { \
165 if (!(expr)) \
166 break; \
167 if (cnt-- == 0) { \
168 retry--; mdelay(1); cnt = backup; \
169 } \
170 } \
171 WARN_ON(retry == 0); \
172 } while (0)
173
174 static void msdc_reset_hw(struct msdc_host *host)
175 {
176 void __iomem *base = host->base;
177
178 sdr_set_bits(MSDC_CFG, MSDC_CFG_RST);
179 while (sdr_read32(MSDC_CFG) & MSDC_CFG_RST)
180 cpu_relax();
181 }
182
183 #define msdc_clr_int() \
184 do { \
185 volatile u32 val = sdr_read32(MSDC_INT); \
186 sdr_write32(MSDC_INT, val); \
187 } while (0)
188
189 #define msdc_clr_fifo() \
190 do { \
191 int retry = 3, cnt = 1000; \
192 sdr_set_bits(MSDC_FIFOCS, MSDC_FIFOCS_CLR); \
193 msdc_retry(sdr_read32(MSDC_FIFOCS) & MSDC_FIFOCS_CLR, retry, cnt); \
194 } while (0)
195
196 #define msdc_irq_save(val) \
197 do { \
198 val = sdr_read32(MSDC_INTEN); \
199 sdr_clr_bits(MSDC_INTEN, val); \
200 } while (0)
201
202 #define msdc_irq_restore(val) \
203 do { \
204 sdr_set_bits(MSDC_INTEN, val); \
205 } while (0)
206
207 /* clock source for host: global */
208 #if defined(CONFIG_SOC_MT7620)
209 static u32 hclks[] = {48000000}; /* +/- by chhung */
210 #elif defined(CONFIG_SOC_MT7621)
211 static u32 hclks[] = {50000000}; /* +/- by chhung */
212 #endif
213
214 //============================================
215 // the power for msdc host controller: global
216 // always keep the VMC on.
217 //============================================
218 #define msdc_vcore_on(host) \
219 do { \
220 INIT_MSG("[+]VMC ref. count<%d>", ++host->pwr_ref); \
221 (void)hwPowerOn(MT65XX_POWER_LDO_VMC, VOL_3300, "SD"); \
222 } while (0)
223 #define msdc_vcore_off(host) \
224 do { \
225 INIT_MSG("[-]VMC ref. count<%d>", --host->pwr_ref); \
226 (void)hwPowerDown(MT65XX_POWER_LDO_VMC, "SD"); \
227 } while (0)
228
229 //====================================
230 // the vdd output for card: global
231 // always keep the VMCH on.
232 //====================================
233 #define msdc_vdd_on(host) \
234 do { \
235 (void)hwPowerOn(MT65XX_POWER_LDO_VMCH, VOL_3300, "SD"); \
236 } while (0)
237 #define msdc_vdd_off(host) \
238 do { \
239 (void)hwPowerDown(MT65XX_POWER_LDO_VMCH, "SD"); \
240 } while (0)
241
242 #define sdc_is_busy() (sdr_read32(SDC_STS) & SDC_STS_SDCBUSY)
243 #define sdc_is_cmd_busy() (sdr_read32(SDC_STS) & SDC_STS_CMDBUSY)
244
245 #define sdc_send_cmd(cmd, arg) \
246 do { \
247 sdr_write32(SDC_ARG, (arg)); \
248 sdr_write32(SDC_CMD, (cmd)); \
249 } while (0)
250
251 // can modify to read h/w register.
252 //#define is_card_present(h) ((sdr_read32(MSDC_PS) & MSDC_PS_CDSTS) ? 0 : 1);
253 #define is_card_present(h) (((struct msdc_host *)(h))->card_inserted)
254
255 /* +++ by chhung */
256 #ifndef __ASSEMBLY__
257 #define PHYSADDR(a) (((unsigned long)(a)) & 0x1fffffff)
258 #else
259 #define PHYSADDR(a) ((a) & 0x1fffffff)
260 #endif
261 /* end of +++ */
262 static unsigned int msdc_do_command(struct msdc_host *host,
263 struct mmc_command *cmd,
264 int tune,
265 unsigned long timeout);
266
267 static int msdc_tune_cmdrsp(struct msdc_host *host, struct mmc_command *cmd);
268
269 #ifdef MT6575_SD_DEBUG
270 static void msdc_dump_card_status(struct msdc_host *host, u32 status)
271 {
272 /* N_MSG is currently a no-op */
273 #if 0
274 static char *state[] = {
275 "Idle", /* 0 */
276 "Ready", /* 1 */
277 "Ident", /* 2 */
278 "Stby", /* 3 */
279 "Tran", /* 4 */
280 "Data", /* 5 */
281 "Rcv", /* 6 */
282 "Prg", /* 7 */
283 "Dis", /* 8 */
284 "Reserved", /* 9 */
285 "Reserved", /* 10 */
286 "Reserved", /* 11 */
287 "Reserved", /* 12 */
288 "Reserved", /* 13 */
289 "Reserved", /* 14 */
290 "I/O mode", /* 15 */
291 };
292 #endif
293 if (status & R1_OUT_OF_RANGE)
294 N_MSG(RSP, "[CARD_STATUS] Out of Range");
295 if (status & R1_ADDRESS_ERROR)
296 N_MSG(RSP, "[CARD_STATUS] Address Error");
297 if (status & R1_BLOCK_LEN_ERROR)
298 N_MSG(RSP, "[CARD_STATUS] Block Len Error");
299 if (status & R1_ERASE_SEQ_ERROR)
300 N_MSG(RSP, "[CARD_STATUS] Erase Seq Error");
301 if (status & R1_ERASE_PARAM)
302 N_MSG(RSP, "[CARD_STATUS] Erase Param");
303 if (status & R1_WP_VIOLATION)
304 N_MSG(RSP, "[CARD_STATUS] WP Violation");
305 if (status & R1_CARD_IS_LOCKED)
306 N_MSG(RSP, "[CARD_STATUS] Card is Locked");
307 if (status & R1_LOCK_UNLOCK_FAILED)
308 N_MSG(RSP, "[CARD_STATUS] Lock/Unlock Failed");
309 if (status & R1_COM_CRC_ERROR)
310 N_MSG(RSP, "[CARD_STATUS] Command CRC Error");
311 if (status & R1_ILLEGAL_COMMAND)
312 N_MSG(RSP, "[CARD_STATUS] Illegal Command");
313 if (status & R1_CARD_ECC_FAILED)
314 N_MSG(RSP, "[CARD_STATUS] Card ECC Failed");
315 if (status & R1_CC_ERROR)
316 N_MSG(RSP, "[CARD_STATUS] CC Error");
317 if (status & R1_ERROR)
318 N_MSG(RSP, "[CARD_STATUS] Error");
319 if (status & R1_UNDERRUN)
320 N_MSG(RSP, "[CARD_STATUS] Underrun");
321 if (status & R1_OVERRUN)
322 N_MSG(RSP, "[CARD_STATUS] Overrun");
323 if (status & R1_CID_CSD_OVERWRITE)
324 N_MSG(RSP, "[CARD_STATUS] CID/CSD Overwrite");
325 if (status & R1_WP_ERASE_SKIP)
326 N_MSG(RSP, "[CARD_STATUS] WP Eraser Skip");
327 if (status & R1_CARD_ECC_DISABLED)
328 N_MSG(RSP, "[CARD_STATUS] Card ECC Disabled");
329 if (status & R1_ERASE_RESET)
330 N_MSG(RSP, "[CARD_STATUS] Erase Reset");
331 if (status & R1_READY_FOR_DATA)
332 N_MSG(RSP, "[CARD_STATUS] Ready for Data");
333 if (status & R1_SWITCH_ERROR)
334 N_MSG(RSP, "[CARD_STATUS] Switch error");
335 if (status & R1_APP_CMD)
336 N_MSG(RSP, "[CARD_STATUS] App Command");
337
338 N_MSG(RSP, "[CARD_STATUS] '%s' State", state[R1_CURRENT_STATE(status)]);
339 }
340
341 static void msdc_dump_ocr_reg(struct msdc_host *host, u32 resp)
342 {
343 if (resp & (1 << 7))
344 N_MSG(RSP, "[OCR] Low Voltage Range");
345 if (resp & (1 << 15))
346 N_MSG(RSP, "[OCR] 2.7-2.8 volt");
347 if (resp & (1 << 16))
348 N_MSG(RSP, "[OCR] 2.8-2.9 volt");
349 if (resp & (1 << 17))
350 N_MSG(RSP, "[OCR] 2.9-3.0 volt");
351 if (resp & (1 << 18))
352 N_MSG(RSP, "[OCR] 3.0-3.1 volt");
353 if (resp & (1 << 19))
354 N_MSG(RSP, "[OCR] 3.1-3.2 volt");
355 if (resp & (1 << 20))
356 N_MSG(RSP, "[OCR] 3.2-3.3 volt");
357 if (resp & (1 << 21))
358 N_MSG(RSP, "[OCR] 3.3-3.4 volt");
359 if (resp & (1 << 22))
360 N_MSG(RSP, "[OCR] 3.4-3.5 volt");
361 if (resp & (1 << 23))
362 N_MSG(RSP, "[OCR] 3.5-3.6 volt");
363 if (resp & (1 << 24))
364 N_MSG(RSP, "[OCR] Switching to 1.8V Accepted (S18A)");
365 if (resp & (1 << 30))
366 N_MSG(RSP, "[OCR] Card Capacity Status (CCS)");
367 if (resp & (1 << 31))
368 N_MSG(RSP, "[OCR] Card Power Up Status (Idle)");
369 else
370 N_MSG(RSP, "[OCR] Card Power Up Status (Busy)");
371 }
372
373 static void msdc_dump_rca_resp(struct msdc_host *host, u32 resp)
374 {
375 u32 status = (((resp >> 15) & 0x1) << 23) |
376 (((resp >> 14) & 0x1) << 22) |
377 (((resp >> 13) & 0x1) << 19) |
378 (resp & 0x1fff);
379
380 N_MSG(RSP, "[RCA] 0x%.4x", resp >> 16);
381 msdc_dump_card_status(host, status);
382 }
383
384 static void msdc_dump_io_resp(struct msdc_host *host, u32 resp)
385 {
386 u32 flags = (resp >> 8) & 0xFF;
387 #if 0
388 char *state[] = {"DIS", "CMD", "TRN", "RFU"};
389 #endif
390 if (flags & (1 << 7))
391 N_MSG(RSP, "[IO] COM_CRC_ERR");
392 if (flags & (1 << 6))
393 N_MSG(RSP, "[IO] Illgal command");
394 if (flags & (1 << 3))
395 N_MSG(RSP, "[IO] Error");
396 if (flags & (1 << 2))
397 N_MSG(RSP, "[IO] RFU");
398 if (flags & (1 << 1))
399 N_MSG(RSP, "[IO] Function number error");
400 if (flags & (1 << 0))
401 N_MSG(RSP, "[IO] Out of range");
402
403 N_MSG(RSP, "[IO] State: %s, Data:0x%x", state[(resp >> 12) & 0x3], resp & 0xFF);
404 }
405 #endif
406
407 static void msdc_set_timeout(struct msdc_host *host, u32 ns, u32 clks)
408 {
409 void __iomem *base = host->base;
410 u32 timeout, clk_ns;
411
412 host->timeout_ns = ns;
413 host->timeout_clks = clks;
414
415 clk_ns = 1000000000UL / host->sclk;
416 timeout = ns / clk_ns + clks;
417 timeout = timeout >> 16; /* in 65536 sclk cycle unit */
418 timeout = timeout > 1 ? timeout - 1 : 0;
419 timeout = timeout > 255 ? 255 : timeout;
420
421 sdr_set_field(SDC_CFG, SDC_CFG_DTOC, timeout);
422
423 N_MSG(OPS, "Set read data timeout: %dns %dclks -> %d x 65536 cycles",
424 ns, clks, timeout + 1);
425 }
426
427 static void msdc_tasklet_card(struct work_struct *work)
428 {
429 struct msdc_host *host = (struct msdc_host *)container_of(work,
430 struct msdc_host, card_delaywork.work);
431 void __iomem *base = host->base;
432 u32 inserted;
433 u32 status = 0;
434 //u32 change = 0;
435
436 spin_lock(&host->lock);
437
438 status = sdr_read32(MSDC_PS);
439 if (cd_active_low)
440 inserted = (status & MSDC_PS_CDSTS) ? 0 : 1;
441 else
442 inserted = (status & MSDC_PS_CDSTS) ? 1 : 0;
443 if (host->mmc->caps & MMC_CAP_NEEDS_POLL)
444 inserted = 1;
445
446 #if 0
447 change = host->card_inserted ^ inserted;
448 host->card_inserted = inserted;
449
450 if (change && !host->suspend) {
451 if (inserted)
452 host->mmc->f_max = HOST_MAX_MCLK; // work around
453 mmc_detect_change(host->mmc, msecs_to_jiffies(20));
454 }
455 #else /* Make sure: handle the last interrupt */
456 host->card_inserted = inserted;
457
458 if (!host->suspend) {
459 host->mmc->f_max = HOST_MAX_MCLK;
460 mmc_detect_change(host->mmc, msecs_to_jiffies(20));
461 }
462
463 IRQ_MSG("card found<%s>", inserted ? "inserted" : "removed");
464 #endif
465
466 spin_unlock(&host->lock);
467 }
468
469 #if 0 /* --- by chhung */
470 /* For E2 only */
471 static u8 clk_src_bit[4] = {
472 0, 3, 5, 7
473 };
474
475 static void msdc_select_clksrc(struct msdc_host *host, unsigned char clksrc)
476 {
477 u32 val;
478 void __iomem *base = host->base;
479
480 BUG_ON(clksrc > 3);
481 INIT_MSG("set clock source to <%d>", clksrc);
482
483 val = sdr_read32(MSDC_CLKSRC_REG);
484 if (sdr_read32(MSDC_ECO_VER) >= 4) {
485 val &= ~(0x3 << clk_src_bit[host->id]);
486 val |= clksrc << clk_src_bit[host->id];
487 } else {
488 val &= ~0x3; val |= clksrc;
489 }
490 sdr_write32(MSDC_CLKSRC_REG, val);
491
492 host->hclk = hclks[clksrc];
493 host->hw->clk_src = clksrc;
494 }
495 #endif /* end of --- */
496
497 static void msdc_set_mclk(struct msdc_host *host, int ddr, unsigned int hz)
498 {
499 //struct msdc_hw *hw = host->hw;
500 void __iomem *base = host->base;
501 u32 mode;
502 u32 flags;
503 u32 div;
504 u32 sclk;
505 u32 hclk = host->hclk;
506 //u8 clksrc = hw->clk_src;
507
508 if (!hz) { // set mmc system clock to 0 ?
509 //ERR_MSG("set mclk to 0!!!");
510 msdc_reset_hw(host);
511 return;
512 }
513
514 msdc_irq_save(flags);
515
516 if (ddr) {
517 mode = 0x2; /* ddr mode and use divisor */
518 if (hz >= (hclk >> 2)) {
519 div = 1; /* mean div = 1/4 */
520 sclk = hclk >> 2; /* sclk = clk / 4 */
521 } else {
522 div = (hclk + ((hz << 2) - 1)) / (hz << 2);
523 sclk = (hclk >> 2) / div;
524 }
525 } else if (hz >= hclk) { /* bug fix */
526 mode = 0x1; /* no divisor and divisor is ignored */
527 div = 0;
528 sclk = hclk;
529 } else {
530 mode = 0x0; /* use divisor */
531 if (hz >= (hclk >> 1)) {
532 div = 0; /* mean div = 1/2 */
533 sclk = hclk >> 1; /* sclk = clk / 2 */
534 } else {
535 div = (hclk + ((hz << 2) - 1)) / (hz << 2);
536 sclk = (hclk >> 2) / div;
537 }
538 }
539
540 /* set clock mode and divisor */
541 sdr_set_field(MSDC_CFG, MSDC_CFG_CKMOD, mode);
542 sdr_set_field(MSDC_CFG, MSDC_CFG_CKDIV, div);
543
544 /* wait clock stable */
545 while (!(sdr_read32(MSDC_CFG) & MSDC_CFG_CKSTB))
546 cpu_relax();
547
548 host->sclk = sclk;
549 host->mclk = hz;
550 msdc_set_timeout(host, host->timeout_ns, host->timeout_clks); // need?
551
552 INIT_MSG("================");
553 INIT_MSG("!!! Set<%dKHz> Source<%dKHz> -> sclk<%dKHz>", hz / 1000, hclk / 1000, sclk / 1000);
554 INIT_MSG("================");
555
556 msdc_irq_restore(flags);
557 }
558
559 /* Fix me. when need to abort */
560 static void msdc_abort_data(struct msdc_host *host)
561 {
562 void __iomem *base = host->base;
563 struct mmc_command *stop = host->mrq->stop;
564
565 ERR_MSG("Need to Abort.");
566
567 msdc_reset_hw(host);
568 msdc_clr_fifo();
569 msdc_clr_int();
570
571 // need to check FIFO count 0 ?
572
573 if (stop) { /* try to stop, but may not success */
574 ERR_MSG("stop when abort CMD<%d>", stop->opcode);
575 (void)msdc_do_command(host, stop, 0, CMD_TIMEOUT);
576 }
577
578 //if (host->mclk >= 25000000) {
579 // msdc_set_mclk(host, 0, host->mclk >> 1);
580 //}
581 }
582
583 #if 0 /* --- by chhung */
584 static void msdc_pin_config(struct msdc_host *host, int mode)
585 {
586 struct msdc_hw *hw = host->hw;
587 void __iomem *base = host->base;
588 int pull = (mode == MSDC_PIN_PULL_UP) ? GPIO_PULL_UP : GPIO_PULL_DOWN;
589
590 /* Config WP pin */
591 if (hw->flags & MSDC_WP_PIN_EN) {
592 if (hw->config_gpio_pin) /* NULL */
593 hw->config_gpio_pin(MSDC_WP_PIN, pull);
594 }
595
596 switch (mode) {
597 case MSDC_PIN_PULL_UP:
598 //sdr_set_field(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKPU, 1); /* Check & FIXME */
599 //sdr_set_field(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKPD, 0); /* Check & FIXME */
600 sdr_set_field(MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDPU, 1);
601 sdr_set_field(MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDPD, 0);
602 sdr_set_field(MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATPU, 1);
603 sdr_set_field(MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATPD, 0);
604 break;
605 case MSDC_PIN_PULL_DOWN:
606 //sdr_set_field(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKPU, 0); /* Check & FIXME */
607 //sdr_set_field(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKPD, 1); /* Check & FIXME */
608 sdr_set_field(MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDPU, 0);
609 sdr_set_field(MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDPD, 1);
610 sdr_set_field(MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATPU, 0);
611 sdr_set_field(MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATPD, 1);
612 break;
613 case MSDC_PIN_PULL_NONE:
614 default:
615 //sdr_set_field(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKPU, 0); /* Check & FIXME */
616 //sdr_set_field(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKPD, 0); /* Check & FIXME */
617 sdr_set_field(MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDPU, 0);
618 sdr_set_field(MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDPD, 0);
619 sdr_set_field(MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATPU, 0);
620 sdr_set_field(MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATPD, 0);
621 break;
622 }
623
624 N_MSG(CFG, "Pins mode(%d), down(%d), up(%d)",
625 mode, MSDC_PIN_PULL_DOWN, MSDC_PIN_PULL_UP);
626 }
627
628 void msdc_pin_reset(struct msdc_host *host, int mode)
629 {
630 struct msdc_hw *hw = (struct msdc_hw *)host->hw;
631 void __iomem *base = host->base;
632 int pull = (mode == MSDC_PIN_PULL_UP) ? GPIO_PULL_UP : GPIO_PULL_DOWN;
633
634 /* Config reset pin */
635 if (hw->flags & MSDC_RST_PIN_EN) {
636 if (hw->config_gpio_pin) /* NULL */
637 hw->config_gpio_pin(MSDC_RST_PIN, pull);
638
639 if (mode == MSDC_PIN_PULL_UP)
640 sdr_clr_bits(EMMC_IOCON, EMMC_IOCON_BOOTRST);
641 else
642 sdr_set_bits(EMMC_IOCON, EMMC_IOCON_BOOTRST);
643 }
644 }
645
646 static void msdc_core_power(struct msdc_host *host, int on)
647 {
648 N_MSG(CFG, "Turn %s %s power (copower: %d -> %d)",
649 on ? "on" : "off", "core", host->core_power, on);
650
651 if (on && host->core_power == 0) {
652 msdc_vcore_on(host);
653 host->core_power = 1;
654 msleep(1);
655 } else if (!on && host->core_power == 1) {
656 msdc_vcore_off(host);
657 host->core_power = 0;
658 msleep(1);
659 }
660 }
661
662 static void msdc_host_power(struct msdc_host *host, int on)
663 {
664 N_MSG(CFG, "Turn %s %s power ", on ? "on" : "off", "host");
665
666 if (on) {
667 //msdc_core_power(host, 1); // need do card detection.
668 msdc_pin_reset(host, MSDC_PIN_PULL_UP);
669 } else {
670 msdc_pin_reset(host, MSDC_PIN_PULL_DOWN);
671 //msdc_core_power(host, 0);
672 }
673 }
674
675 static void msdc_card_power(struct msdc_host *host, int on)
676 {
677 N_MSG(CFG, "Turn %s %s power ", on ? "on" : "off", "card");
678
679 if (on) {
680 msdc_pin_config(host, MSDC_PIN_PULL_UP);
681 //msdc_vdd_on(host); // need todo card detection.
682 msleep(1);
683 } else {
684 //msdc_vdd_off(host);
685 msdc_pin_config(host, MSDC_PIN_PULL_DOWN);
686 msleep(1);
687 }
688 }
689
690 static void msdc_set_power_mode(struct msdc_host *host, u8 mode)
691 {
692 N_MSG(CFG, "Set power mode(%d)", mode);
693
694 if (host->power_mode == MMC_POWER_OFF && mode != MMC_POWER_OFF) {
695 msdc_host_power(host, 1);
696 msdc_card_power(host, 1);
697 } else if (host->power_mode != MMC_POWER_OFF && mode == MMC_POWER_OFF) {
698 msdc_card_power(host, 0);
699 msdc_host_power(host, 0);
700 }
701 host->power_mode = mode;
702 }
703 #endif /* end of --- */
704
705 #ifdef CONFIG_PM
706 /*
707 register as callback function of WIFI(combo_sdio_register_pm) .
708 can called by msdc_drv_suspend/resume too.
709 */
710 static void msdc_pm(pm_message_t state, void *data)
711 {
712 struct msdc_host *host = (struct msdc_host *)data;
713 int evt = state.event;
714
715 if (evt == PM_EVENT_USER_RESUME || evt == PM_EVENT_USER_SUSPEND) {
716 INIT_MSG("USR_%s: suspend<%d> power<%d>",
717 evt == PM_EVENT_USER_RESUME ? "EVENT_USER_RESUME" : "EVENT_USER_SUSPEND",
718 host->suspend, host->power_mode);
719 }
720
721 if (evt == PM_EVENT_SUSPEND || evt == PM_EVENT_USER_SUSPEND) {
722 if (host->suspend) /* already suspend */ /* default 0*/
723 return;
724
725 /* for memory card. already power off by mmc */
726 if (evt == PM_EVENT_SUSPEND && host->power_mode == MMC_POWER_OFF)
727 return;
728
729 host->suspend = 1;
730 host->pm_state = state; /* default PMSG_RESUME */
731
732 } else if (evt == PM_EVENT_RESUME || evt == PM_EVENT_USER_RESUME) {
733 if (!host->suspend) {
734 //ERR_MSG("warning: already resume");
735 return;
736 }
737
738 /* No PM resume when USR suspend */
739 if (evt == PM_EVENT_RESUME && host->pm_state.event == PM_EVENT_USER_SUSPEND) {
740 ERR_MSG("PM Resume when in USR Suspend"); /* won't happen. */
741 return;
742 }
743
744 host->suspend = 0;
745 host->pm_state = state;
746
747 }
748 }
749 #endif
750
751 /*--------------------------------------------------------------------------*/
752 /* mmc_host_ops members */
753 /*--------------------------------------------------------------------------*/
754 static unsigned int msdc_command_start(struct msdc_host *host,
755 struct mmc_command *cmd,
756 int tune, /* not used */
757 unsigned long timeout)
758 {
759 void __iomem *base = host->base;
760 u32 opcode = cmd->opcode;
761 u32 rawcmd;
762 u32 wints = MSDC_INT_CMDRDY | MSDC_INT_RSPCRCERR | MSDC_INT_CMDTMO |
763 MSDC_INT_ACMDRDY | MSDC_INT_ACMDCRCERR | MSDC_INT_ACMDTMO |
764 MSDC_INT_ACMD19_DONE;
765
766 u32 resp;
767 unsigned long tmo;
768
769 /* Protocol layer does not provide response type, but our hardware needs
770 * to know exact type, not just size!
771 */
772 if (opcode == MMC_SEND_OP_COND || opcode == SD_APP_OP_COND) {
773 resp = RESP_R3;
774 } else if (opcode == MMC_SET_RELATIVE_ADDR) {
775 resp = (mmc_cmd_type(cmd) == MMC_CMD_BCR) ? RESP_R6 : RESP_R1;
776 } else if (opcode == MMC_FAST_IO) {
777 resp = RESP_R4;
778 } else if (opcode == MMC_GO_IRQ_STATE) {
779 resp = RESP_R5;
780 } else if (opcode == MMC_SELECT_CARD) {
781 resp = (cmd->arg != 0) ? RESP_R1B : RESP_NONE;
782 } else if (opcode == SD_IO_RW_DIRECT || opcode == SD_IO_RW_EXTENDED) {
783 resp = RESP_R1; /* SDIO workaround. */
784 } else if (opcode == SD_SEND_IF_COND && (mmc_cmd_type(cmd) == MMC_CMD_BCR)) {
785 resp = RESP_R1;
786 } else {
787 switch (mmc_resp_type(cmd)) {
788 case MMC_RSP_R1:
789 resp = RESP_R1;
790 break;
791 case MMC_RSP_R1B:
792 resp = RESP_R1B;
793 break;
794 case MMC_RSP_R2:
795 resp = RESP_R2;
796 break;
797 case MMC_RSP_R3:
798 resp = RESP_R3;
799 break;
800 case MMC_RSP_NONE:
801 default:
802 resp = RESP_NONE;
803 break;
804 }
805 }
806
807 cmd->error = 0;
808 /* rawcmd :
809 * vol_swt << 30 | auto_cmd << 28 | blklen << 16 | go_irq << 15 |
810 * stop << 14 | rw << 13 | dtype << 11 | rsptyp << 7 | brk << 6 | opcode
811 */
812 rawcmd = opcode | msdc_rsp[resp] << 7 | host->blksz << 16;
813
814 if (opcode == MMC_READ_MULTIPLE_BLOCK) {
815 rawcmd |= (2 << 11);
816 } else if (opcode == MMC_READ_SINGLE_BLOCK) {
817 rawcmd |= (1 << 11);
818 } else if (opcode == MMC_WRITE_MULTIPLE_BLOCK) {
819 rawcmd |= ((2 << 11) | (1 << 13));
820 } else if (opcode == MMC_WRITE_BLOCK) {
821 rawcmd |= ((1 << 11) | (1 << 13));
822 } else if (opcode == SD_IO_RW_EXTENDED) {
823 if (cmd->data->flags & MMC_DATA_WRITE)
824 rawcmd |= (1 << 13);
825 if (cmd->data->blocks > 1)
826 rawcmd |= (2 << 11);
827 else
828 rawcmd |= (1 << 11);
829 } else if (opcode == SD_IO_RW_DIRECT && cmd->flags == (unsigned int)-1) {
830 rawcmd |= (1 << 14);
831 } else if ((opcode == SD_APP_SEND_SCR) ||
832 (opcode == SD_APP_SEND_NUM_WR_BLKS) ||
833 (opcode == SD_SWITCH && (mmc_cmd_type(cmd) == MMC_CMD_ADTC)) ||
834 (opcode == SD_APP_SD_STATUS && (mmc_cmd_type(cmd) == MMC_CMD_ADTC)) ||
835 (opcode == MMC_SEND_EXT_CSD && (mmc_cmd_type(cmd) == MMC_CMD_ADTC))) {
836 rawcmd |= (1 << 11);
837 } else if (opcode == MMC_STOP_TRANSMISSION) {
838 rawcmd |= (1 << 14);
839 rawcmd &= ~(0x0FFF << 16);
840 }
841
842 N_MSG(CMD, "CMD<%d><0x%.8x> Arg<0x%.8x>", opcode, rawcmd, cmd->arg);
843
844 tmo = jiffies + timeout;
845
846 if (opcode == MMC_SEND_STATUS) {
847 for (;;) {
848 if (!sdc_is_cmd_busy())
849 break;
850
851 if (time_after(jiffies, tmo)) {
852 ERR_MSG("XXX cmd_busy timeout: before CMD<%d>", opcode);
853 cmd->error = -ETIMEDOUT;
854 msdc_reset_hw(host);
855 goto end;
856 }
857 }
858 } else {
859 for (;;) {
860 if (!sdc_is_busy())
861 break;
862 if (time_after(jiffies, tmo)) {
863 ERR_MSG("XXX sdc_busy timeout: before CMD<%d>", opcode);
864 cmd->error = -ETIMEDOUT;
865 msdc_reset_hw(host);
866 goto end;
867 }
868 }
869 }
870
871 //BUG_ON(in_interrupt());
872 host->cmd = cmd;
873 host->cmd_rsp = resp;
874
875 init_completion(&host->cmd_done);
876
877 sdr_set_bits(MSDC_INTEN, wints);
878 sdc_send_cmd(rawcmd, cmd->arg);
879
880 end:
881 return cmd->error;
882 }
883
884 static unsigned int msdc_command_resp(struct msdc_host *host,
885 struct mmc_command *cmd,
886 int tune,
887 unsigned long timeout)
888 __must_hold(&host->lock)
889 {
890 void __iomem *base = host->base;
891 u32 opcode = cmd->opcode;
892 //u32 rawcmd;
893 u32 resp;
894 u32 wints = MSDC_INT_CMDRDY | MSDC_INT_RSPCRCERR | MSDC_INT_CMDTMO |
895 MSDC_INT_ACMDRDY | MSDC_INT_ACMDCRCERR | MSDC_INT_ACMDTMO |
896 MSDC_INT_ACMD19_DONE;
897
898 resp = host->cmd_rsp;
899
900 BUG_ON(in_interrupt());
901 //init_completion(&host->cmd_done);
902 //sdr_set_bits(MSDC_INTEN, wints);
903
904 spin_unlock(&host->lock);
905 if (!wait_for_completion_timeout(&host->cmd_done, 10 * timeout)) {
906 ERR_MSG("XXX CMD<%d> wait_for_completion timeout ARG<0x%.8x>", opcode, cmd->arg);
907 cmd->error = -ETIMEDOUT;
908 msdc_reset_hw(host);
909 }
910 spin_lock(&host->lock);
911
912 sdr_clr_bits(MSDC_INTEN, wints);
913 host->cmd = NULL;
914
915 //end:
916 #ifdef MT6575_SD_DEBUG
917 switch (resp) {
918 case RESP_NONE:
919 N_MSG(RSP, "CMD_RSP(%d): %d RSP(%d)", opcode, cmd->error, resp);
920 break;
921 case RESP_R2:
922 N_MSG(RSP, "CMD_RSP(%d): %d RSP(%d)= %.8x %.8x %.8x %.8x",
923 opcode, cmd->error, resp, cmd->resp[0], cmd->resp[1],
924 cmd->resp[2], cmd->resp[3]);
925 break;
926 default: /* Response types 1, 3, 4, 5, 6, 7(1b) */
927 N_MSG(RSP, "CMD_RSP(%d): %d RSP(%d)= 0x%.8x",
928 opcode, cmd->error, resp, cmd->resp[0]);
929 if (cmd->error == 0) {
930 switch (resp) {
931 case RESP_R1:
932 case RESP_R1B:
933 msdc_dump_card_status(host, cmd->resp[0]);
934 break;
935 case RESP_R3:
936 msdc_dump_ocr_reg(host, cmd->resp[0]);
937 break;
938 case RESP_R5:
939 msdc_dump_io_resp(host, cmd->resp[0]);
940 break;
941 case RESP_R6:
942 msdc_dump_rca_resp(host, cmd->resp[0]);
943 break;
944 }
945 }
946 break;
947 }
948 #endif
949
950 /* do we need to save card's RCA when SD_SEND_RELATIVE_ADDR */
951
952 if (!tune)
953 return cmd->error;
954
955 /* memory card CRC */
956 if (host->hw->flags & MSDC_REMOVABLE && cmd->error == -EIO) {
957 if (sdr_read32(SDC_CMD) & 0x1800) { /* check if has data phase */
958 msdc_abort_data(host);
959 } else {
960 /* do basic: reset*/
961 msdc_reset_hw(host);
962 msdc_clr_fifo();
963 msdc_clr_int();
964 }
965 cmd->error = msdc_tune_cmdrsp(host, cmd);
966 }
967
968 // check DAT0
969 /* if (resp == RESP_R1B) {
970 while ((sdr_read32(MSDC_PS) & 0x10000) != 0x10000);
971 } */
972 /* CMD12 Error Handle */
973
974 return cmd->error;
975 }
976
977 static unsigned int msdc_do_command(struct msdc_host *host,
978 struct mmc_command *cmd,
979 int tune,
980 unsigned long timeout)
981 {
982 if (msdc_command_start(host, cmd, tune, timeout))
983 goto end;
984
985 if (msdc_command_resp(host, cmd, tune, timeout))
986 goto end;
987
988 end:
989
990 N_MSG(CMD, " return<%d> resp<0x%.8x>", cmd->error, cmd->resp[0]);
991 return cmd->error;
992 }
993
994 #if 0 /* --- by chhung */
995 // DMA resume / start / stop
996 static void msdc_dma_resume(struct msdc_host *host)
997 {
998 void __iomem *base = host->base;
999
1000 sdr_set_field(MSDC_DMA_CTRL, MSDC_DMA_CTRL_RESUME, 1);
1001
1002 N_MSG(DMA, "DMA resume");
1003 }
1004 #endif /* end of --- */
1005
1006 static void msdc_dma_start(struct msdc_host *host)
1007 {
1008 void __iomem *base = host->base;
1009 u32 wints = MSDC_INTEN_XFER_COMPL | MSDC_INTEN_DATTMO | MSDC_INTEN_DATCRCERR;
1010
1011 sdr_set_bits(MSDC_INTEN, wints);
1012 //dsb(); /* --- by chhung */
1013 sdr_set_field(MSDC_DMA_CTRL, MSDC_DMA_CTRL_START, 1);
1014
1015 N_MSG(DMA, "DMA start");
1016 }
1017
1018 static void msdc_dma_stop(struct msdc_host *host)
1019 {
1020 void __iomem *base = host->base;
1021 //u32 retries=500;
1022 u32 wints = MSDC_INTEN_XFER_COMPL | MSDC_INTEN_DATTMO | MSDC_INTEN_DATCRCERR;
1023
1024 N_MSG(DMA, "DMA status: 0x%.8x", sdr_read32(MSDC_DMA_CFG));
1025 //while (sdr_read32(MSDC_DMA_CFG) & MSDC_DMA_CFG_STS);
1026
1027 sdr_set_field(MSDC_DMA_CTRL, MSDC_DMA_CTRL_STOP, 1);
1028 while (sdr_read32(MSDC_DMA_CFG) & MSDC_DMA_CFG_STS)
1029 ;
1030
1031 //dsb(); /* --- by chhung */
1032 sdr_clr_bits(MSDC_INTEN, wints); /* Not just xfer_comp */
1033
1034 N_MSG(DMA, "DMA stop");
1035 }
1036
1037 /* calc checksum */
1038 static u8 msdc_dma_calcs(u8 *buf, u32 len)
1039 {
1040 u32 i, sum = 0;
1041
1042 for (i = 0; i < len; i++)
1043 sum += buf[i];
1044 return 0xFF - (u8)sum;
1045 }
1046
1047 /* gpd bd setup + dma registers */
1048 static void msdc_dma_config(struct msdc_host *host, struct msdc_dma *dma)
1049 {
1050 void __iomem *base = host->base;
1051 //u32 i, j, num, bdlen, arg, xfersz;
1052 u32 j, num;
1053 struct scatterlist *sg;
1054 struct gpd *gpd;
1055 struct bd *bd;
1056
1057 switch (dma->mode) {
1058 case MSDC_MODE_DMA_BASIC:
1059 BUG_ON(host->xfer_size > 65535);
1060 BUG_ON(dma->sglen != 1);
1061 sdr_write32(MSDC_DMA_SA, PHYSADDR(sg_dma_address(sg)));
1062 sdr_set_field(MSDC_DMA_CTRL, MSDC_DMA_CTRL_LASTBUF, 1);
1063 //#if defined (CONFIG_RALINK_MT7620)
1064 if (ralink_soc == MT762X_SOC_MT7620A)
1065 sdr_set_field(MSDC_DMA_CTRL, MSDC_DMA_CTRL_XFERSZ, sg_dma_len(sg));
1066 //#elif defined (CONFIG_RALINK_MT7621) || defined (CONFIG_RALINK_MT7628)
1067 else
1068 sdr_write32((void __iomem *)(RALINK_MSDC_BASE + 0xa8), sg_dma_len(sg));
1069 //#endif
1070 sdr_set_field(MSDC_DMA_CTRL, MSDC_DMA_CTRL_BRUSTSZ,
1071 MSDC_BRUST_64B);
1072 sdr_set_field(MSDC_DMA_CTRL, MSDC_DMA_CTRL_MODE, 0);
1073 break;
1074 case MSDC_MODE_DMA_DESC:
1075
1076 /* calculate the required number of gpd */
1077 num = (dma->sglen + MAX_BD_PER_GPD - 1) / MAX_BD_PER_GPD;
1078 BUG_ON(num != 1);
1079
1080 gpd = dma->gpd;
1081 bd = dma->bd;
1082
1083 /* modify gpd*/
1084 //gpd->intr = 0;
1085 gpd->hwo = 1; /* hw will clear it */
1086 gpd->bdp = 1;
1087 gpd->chksum = 0; /* need to clear first. */
1088 gpd->chksum = msdc_dma_calcs((u8 *)gpd, 16);
1089
1090 /* modify bd*/
1091 for_each_sg(dma->sg, sg, dma->sglen, j) {
1092 bd[j].blkpad = 0;
1093 bd[j].dwpad = 0;
1094 bd[j].ptr = (void *)sg_dma_address(sg);
1095 bd[j].buflen = sg_dma_len(sg);
1096
1097 if (j == dma->sglen - 1)
1098 bd[j].eol = 1; /* the last bd */
1099 else
1100 bd[j].eol = 0;
1101
1102 bd[j].chksum = 0; /* checksume need to clear first */
1103 bd[j].chksum = msdc_dma_calcs((u8 *)(&bd[j]), 16);
1104 }
1105
1106 sdr_set_field(MSDC_DMA_CFG, MSDC_DMA_CFG_DECSEN, 1);
1107 sdr_set_field(MSDC_DMA_CTRL, MSDC_DMA_CTRL_BRUSTSZ,
1108 MSDC_BRUST_64B);
1109 sdr_set_field(MSDC_DMA_CTRL, MSDC_DMA_CTRL_MODE, 1);
1110
1111 sdr_write32(MSDC_DMA_SA, PHYSADDR((u32)dma->gpd_addr));
1112 break;
1113
1114 default:
1115 break;
1116 }
1117
1118 N_MSG(DMA, "DMA_CTRL = 0x%x", sdr_read32(MSDC_DMA_CTRL));
1119 N_MSG(DMA, "DMA_CFG = 0x%x", sdr_read32(MSDC_DMA_CFG));
1120 N_MSG(DMA, "DMA_SA = 0x%x", sdr_read32(MSDC_DMA_SA));
1121
1122 }
1123
1124 static void msdc_dma_setup(struct msdc_host *host, struct msdc_dma *dma,
1125 struct scatterlist *sg, unsigned int sglen)
1126 {
1127 BUG_ON(sglen > MAX_BD_NUM); /* not support currently */
1128
1129 dma->sg = sg;
1130 dma->sglen = sglen;
1131
1132 dma->mode = MSDC_MODE_DMA_DESC;
1133
1134 N_MSG(DMA, "DMA mode<%d> sglen<%d> xfersz<%d>", dma->mode, dma->sglen,
1135 host->xfer_size);
1136
1137 msdc_dma_config(host, dma);
1138 }
1139
1140 static int msdc_do_request(struct mmc_host *mmc, struct mmc_request *mrq)
1141 __must_hold(&host->lock)
1142 {
1143 struct msdc_host *host = mmc_priv(mmc);
1144 struct mmc_command *cmd;
1145 struct mmc_data *data;
1146 void __iomem *base = host->base;
1147 //u32 intsts = 0;
1148 int read = 1, send_type = 0;
1149
1150 #define SND_DAT 0
1151 #define SND_CMD 1
1152
1153 BUG_ON(mmc == NULL);
1154 BUG_ON(mrq == NULL);
1155
1156 host->error = 0;
1157
1158 cmd = mrq->cmd;
1159 data = mrq->cmd->data;
1160
1161 #if 0 /* --- by chhung */
1162 //if(host->id ==1){
1163 N_MSG(OPS, "enable clock!");
1164 msdc_ungate_clock(host->id);
1165 //}
1166 #endif /* end of --- */
1167
1168 if (!data) {
1169 send_type = SND_CMD;
1170 if (msdc_do_command(host, cmd, 1, CMD_TIMEOUT) != 0)
1171 goto done;
1172 } else {
1173 BUG_ON(data->blksz > HOST_MAX_BLKSZ);
1174 send_type = SND_DAT;
1175
1176 data->error = 0;
1177 read = data->flags & MMC_DATA_READ ? 1 : 0;
1178 host->data = data;
1179 host->xfer_size = data->blocks * data->blksz;
1180 host->blksz = data->blksz;
1181
1182 if (read) {
1183 if ((host->timeout_ns != data->timeout_ns) ||
1184 (host->timeout_clks != data->timeout_clks)) {
1185 msdc_set_timeout(host, data->timeout_ns, data->timeout_clks);
1186 }
1187 }
1188
1189 sdr_write32(SDC_BLK_NUM, data->blocks);
1190 //msdc_clr_fifo(); /* no need */
1191
1192 msdc_dma_on(); /* enable DMA mode first!! */
1193 init_completion(&host->xfer_done);
1194
1195 /* start the command first*/
1196 if (msdc_command_start(host, cmd, 1, CMD_TIMEOUT) != 0)
1197 goto done;
1198
1199 data->sg_count = dma_map_sg(mmc_dev(mmc), data->sg,
1200 data->sg_len,
1201 mmc_get_dma_dir(data));
1202 msdc_dma_setup(host, &host->dma, data->sg,
1203 data->sg_count);
1204
1205 /* then wait command done */
1206 if (msdc_command_resp(host, cmd, 1, CMD_TIMEOUT) != 0)
1207 goto done;
1208
1209 /* for read, the data coming too fast, then CRC error
1210 start DMA no business with CRC. */
1211 //init_completion(&host->xfer_done);
1212 msdc_dma_start(host);
1213
1214 spin_unlock(&host->lock);
1215 if (!wait_for_completion_timeout(&host->xfer_done, DAT_TIMEOUT)) {
1216 ERR_MSG("XXX CMD<%d> wait xfer_done<%d> timeout!!", cmd->opcode, data->blocks * data->blksz);
1217 ERR_MSG(" DMA_SA = 0x%x", sdr_read32(MSDC_DMA_SA));
1218 ERR_MSG(" DMA_CA = 0x%x", sdr_read32(MSDC_DMA_CA));
1219 ERR_MSG(" DMA_CTRL = 0x%x", sdr_read32(MSDC_DMA_CTRL));
1220 ERR_MSG(" DMA_CFG = 0x%x", sdr_read32(MSDC_DMA_CFG));
1221 data->error = -ETIMEDOUT;
1222
1223 msdc_reset_hw(host);
1224 msdc_clr_fifo();
1225 msdc_clr_int();
1226 }
1227 spin_lock(&host->lock);
1228 msdc_dma_stop(host);
1229
1230 /* Last: stop transfer */
1231 if (data->stop) {
1232 if (msdc_do_command(host, data->stop, 0, CMD_TIMEOUT) != 0)
1233 goto done;
1234 }
1235 }
1236
1237 done:
1238 if (data != NULL) {
1239 host->data = NULL;
1240 dma_unmap_sg(mmc_dev(mmc), data->sg, data->sg_len,
1241 mmc_get_dma_dir(data));
1242 host->blksz = 0;
1243
1244 #if 0 // don't stop twice!
1245 if (host->hw->flags & MSDC_REMOVABLE && data->error) {
1246 msdc_abort_data(host);
1247 /* reset in IRQ, stop command has issued. -> No need */
1248 }
1249 #endif
1250
1251 N_MSG(OPS, "CMD<%d> data<%s %s> blksz<%d> block<%d> error<%d>", cmd->opcode, (dma ? "dma" : "pio"),
1252 (read ? "read " : "write"), data->blksz, data->blocks, data->error);
1253 }
1254
1255 #if 0 /* --- by chhung */
1256 #if 1
1257 //if(host->id==1) {
1258 if (send_type == SND_CMD) {
1259 if (cmd->opcode == MMC_SEND_STATUS) {
1260 if ((cmd->resp[0] & CARD_READY_FOR_DATA) || (CARD_CURRENT_STATE(cmd->resp[0]) != 7)) {
1261 N_MSG(OPS, "disable clock, CMD13 IDLE");
1262 msdc_gate_clock(host->id);
1263 }
1264 } else {
1265 N_MSG(OPS, "disable clock, CMD<%d>", cmd->opcode);
1266 msdc_gate_clock(host->id);
1267 }
1268 } else {
1269 if (read) {
1270 N_MSG(OPS, "disable clock!!! Read CMD<%d>", cmd->opcode);
1271 msdc_gate_clock(host->id);
1272 }
1273 }
1274 //}
1275 #else
1276 msdc_gate_clock(host->id);
1277 #endif
1278 #endif /* end of --- */
1279
1280 if (mrq->cmd->error)
1281 host->error = 0x001;
1282 if (mrq->data && mrq->data->error)
1283 host->error |= 0x010;
1284 if (mrq->stop && mrq->stop->error)
1285 host->error |= 0x100;
1286
1287 //if (host->error) ERR_MSG("host->error<%d>", host->error);
1288
1289 return host->error;
1290 }
1291
1292 static int msdc_app_cmd(struct mmc_host *mmc, struct msdc_host *host)
1293 {
1294 struct mmc_command cmd;
1295 struct mmc_request mrq;
1296 u32 err;
1297
1298 memset(&cmd, 0, sizeof(struct mmc_command));
1299 cmd.opcode = MMC_APP_CMD;
1300 #if 0 /* bug: we meet mmc->card is null when ACMD6 */
1301 cmd.arg = mmc->card->rca << 16;
1302 #else
1303 cmd.arg = host->app_cmd_arg;
1304 #endif
1305 cmd.flags = MMC_RSP_SPI_R1 | MMC_RSP_R1 | MMC_CMD_AC;
1306
1307 memset(&mrq, 0, sizeof(struct mmc_request));
1308 mrq.cmd = &cmd; cmd.mrq = &mrq;
1309 cmd.data = NULL;
1310
1311 err = msdc_do_command(host, &cmd, 0, CMD_TIMEOUT);
1312 return err;
1313 }
1314
1315 static int msdc_tune_cmdrsp(struct msdc_host *host, struct mmc_command *cmd)
1316 {
1317 int result = -1;
1318 void __iomem *base = host->base;
1319 u32 rsmpl, cur_rsmpl, orig_rsmpl;
1320 u32 rrdly, cur_rrdly = 0xffffffff, orig_rrdly;
1321 u32 skip = 1;
1322
1323 /* ==== don't support 3.0 now ====
1324 1: R_SMPL[1]
1325 2: PAD_CMD_RESP_RXDLY[26:22]
1326 ==========================*/
1327
1328 // save the previous tune result
1329 sdr_get_field(MSDC_IOCON, MSDC_IOCON_RSPL, &orig_rsmpl);
1330 sdr_get_field(MSDC_PAD_TUNE, MSDC_PAD_TUNE_CMDRRDLY, &orig_rrdly);
1331
1332 rrdly = 0;
1333 do {
1334 for (rsmpl = 0; rsmpl < 2; rsmpl++) {
1335 /* Lv1: R_SMPL[1] */
1336 cur_rsmpl = (orig_rsmpl + rsmpl) % 2;
1337 if (skip == 1) {
1338 skip = 0;
1339 continue;
1340 }
1341 sdr_set_field(MSDC_IOCON, MSDC_IOCON_RSPL, cur_rsmpl);
1342
1343 if (host->app_cmd) {
1344 result = msdc_app_cmd(host->mmc, host);
1345 if (result) {
1346 ERR_MSG("TUNE_CMD app_cmd<%d> failed: RESP_RXDLY<%d>,R_SMPL<%d>",
1347 host->mrq->cmd->opcode, cur_rrdly, cur_rsmpl);
1348 continue;
1349 }
1350 }
1351 result = msdc_do_command(host, cmd, 0, CMD_TIMEOUT); // not tune.
1352 ERR_MSG("TUNE_CMD<%d> %s PAD_CMD_RESP_RXDLY[26:22]<%d> R_SMPL[1]<%d>", cmd->opcode,
1353 (result == 0) ? "PASS" : "FAIL", cur_rrdly, cur_rsmpl);
1354
1355 if (result == 0)
1356 return 0;
1357 if (result != -EIO) {
1358 ERR_MSG("TUNE_CMD<%d> Error<%d> not -EIO", cmd->opcode, result);
1359 return result;
1360 }
1361
1362 /* should be EIO */
1363 if (sdr_read32(SDC_CMD) & 0x1800) { /* check if has data phase */
1364 msdc_abort_data(host);
1365 }
1366 }
1367
1368 /* Lv2: PAD_CMD_RESP_RXDLY[26:22] */
1369 cur_rrdly = (orig_rrdly + rrdly + 1) % 32;
1370 sdr_set_field(MSDC_PAD_TUNE, MSDC_PAD_TUNE_CMDRRDLY, cur_rrdly);
1371 } while (++rrdly < 32);
1372
1373 return result;
1374 }
1375
1376 /* Support SD2.0 Only */
1377 static int msdc_tune_bread(struct mmc_host *mmc, struct mmc_request *mrq)
1378 {
1379 struct msdc_host *host = mmc_priv(mmc);
1380 void __iomem *base = host->base;
1381 u32 ddr = 0;
1382 u32 dcrc = 0;
1383 u32 rxdly, cur_rxdly0, cur_rxdly1;
1384 u32 dsmpl, cur_dsmpl, orig_dsmpl;
1385 u32 cur_dat0, cur_dat1, cur_dat2, cur_dat3;
1386 u32 cur_dat4, cur_dat5, cur_dat6, cur_dat7;
1387 u32 orig_dat0, orig_dat1, orig_dat2, orig_dat3;
1388 u32 orig_dat4, orig_dat5, orig_dat6, orig_dat7;
1389 int result = -1;
1390 u32 skip = 1;
1391
1392 sdr_get_field(MSDC_IOCON, MSDC_IOCON_DSPL, &orig_dsmpl);
1393
1394 /* Tune Method 2. */
1395 sdr_set_field(MSDC_IOCON, MSDC_IOCON_DDLSEL, 1);
1396
1397 rxdly = 0;
1398 do {
1399 for (dsmpl = 0; dsmpl < 2; dsmpl++) {
1400 cur_dsmpl = (orig_dsmpl + dsmpl) % 2;
1401 if (skip == 1) {
1402 skip = 0;
1403 continue;
1404 }
1405 sdr_set_field(MSDC_IOCON, MSDC_IOCON_DSPL, cur_dsmpl);
1406
1407 if (host->app_cmd) {
1408 result = msdc_app_cmd(host->mmc, host);
1409 if (result) {
1410 ERR_MSG("TUNE_BREAD app_cmd<%d> failed", host->mrq->cmd->opcode);
1411 continue;
1412 }
1413 }
1414 result = msdc_do_request(mmc, mrq);
1415
1416 sdr_get_field(SDC_DCRC_STS,
1417 SDC_DCRC_STS_POS | SDC_DCRC_STS_NEG,
1418 &dcrc); /* RO */
1419 if (!ddr)
1420 dcrc &= ~SDC_DCRC_STS_NEG;
1421 ERR_MSG("TUNE_BREAD<%s> dcrc<0x%x> DATRDDLY0/1<0x%x><0x%x> dsmpl<0x%x>",
1422 (result == 0 && dcrc == 0) ? "PASS" : "FAIL", dcrc,
1423 sdr_read32(MSDC_DAT_RDDLY0), sdr_read32(MSDC_DAT_RDDLY1), cur_dsmpl);
1424
1425 /* Fix me: result is 0, but dcrc is still exist */
1426 if (result == 0 && dcrc == 0) {
1427 goto done;
1428 } else {
1429 /* there is a case: command timeout, and data phase not processed */
1430 if (mrq->data->error != 0 &&
1431 mrq->data->error != -EIO) {
1432 ERR_MSG("TUNE_READ: result<0x%x> cmd_error<%d> data_error<%d>",
1433 result, mrq->cmd->error, mrq->data->error);
1434 goto done;
1435 }
1436 }
1437 }
1438
1439 cur_rxdly0 = sdr_read32(MSDC_DAT_RDDLY0);
1440 cur_rxdly1 = sdr_read32(MSDC_DAT_RDDLY1);
1441
1442 /* E1 ECO. YD: Reverse */
1443 if (sdr_read32(MSDC_ECO_VER) >= 4) {
1444 orig_dat0 = (cur_rxdly0 >> 24) & 0x1F;
1445 orig_dat1 = (cur_rxdly0 >> 16) & 0x1F;
1446 orig_dat2 = (cur_rxdly0 >> 8) & 0x1F;
1447 orig_dat3 = (cur_rxdly0 >> 0) & 0x1F;
1448 orig_dat4 = (cur_rxdly1 >> 24) & 0x1F;
1449 orig_dat5 = (cur_rxdly1 >> 16) & 0x1F;
1450 orig_dat6 = (cur_rxdly1 >> 8) & 0x1F;
1451 orig_dat7 = (cur_rxdly1 >> 0) & 0x1F;
1452 } else {
1453 orig_dat0 = (cur_rxdly0 >> 0) & 0x1F;
1454 orig_dat1 = (cur_rxdly0 >> 8) & 0x1F;
1455 orig_dat2 = (cur_rxdly0 >> 16) & 0x1F;
1456 orig_dat3 = (cur_rxdly0 >> 24) & 0x1F;
1457 orig_dat4 = (cur_rxdly1 >> 0) & 0x1F;
1458 orig_dat5 = (cur_rxdly1 >> 8) & 0x1F;
1459 orig_dat6 = (cur_rxdly1 >> 16) & 0x1F;
1460 orig_dat7 = (cur_rxdly1 >> 24) & 0x1F;
1461 }
1462
1463 if (ddr) {
1464 cur_dat0 = (dcrc & (1 << 0) || dcrc & (1 << 8)) ? ((orig_dat0 + 1) % 32) : orig_dat0;
1465 cur_dat1 = (dcrc & (1 << 1) || dcrc & (1 << 9)) ? ((orig_dat1 + 1) % 32) : orig_dat1;
1466 cur_dat2 = (dcrc & (1 << 2) || dcrc & (1 << 10)) ? ((orig_dat2 + 1) % 32) : orig_dat2;
1467 cur_dat3 = (dcrc & (1 << 3) || dcrc & (1 << 11)) ? ((orig_dat3 + 1) % 32) : orig_dat3;
1468 } else {
1469 cur_dat0 = (dcrc & (1 << 0)) ? ((orig_dat0 + 1) % 32) : orig_dat0;
1470 cur_dat1 = (dcrc & (1 << 1)) ? ((orig_dat1 + 1) % 32) : orig_dat1;
1471 cur_dat2 = (dcrc & (1 << 2)) ? ((orig_dat2 + 1) % 32) : orig_dat2;
1472 cur_dat3 = (dcrc & (1 << 3)) ? ((orig_dat3 + 1) % 32) : orig_dat3;
1473 }
1474 cur_dat4 = (dcrc & (1 << 4)) ? ((orig_dat4 + 1) % 32) : orig_dat4;
1475 cur_dat5 = (dcrc & (1 << 5)) ? ((orig_dat5 + 1) % 32) : orig_dat5;
1476 cur_dat6 = (dcrc & (1 << 6)) ? ((orig_dat6 + 1) % 32) : orig_dat6;
1477 cur_dat7 = (dcrc & (1 << 7)) ? ((orig_dat7 + 1) % 32) : orig_dat7;
1478
1479 cur_rxdly0 = (cur_dat0 << 24) | (cur_dat1 << 16) | (cur_dat2 << 8) | (cur_dat3 << 0);
1480 cur_rxdly1 = (cur_dat4 << 24) | (cur_dat5 << 16) | (cur_dat6 << 8) | (cur_dat7 << 0);
1481
1482 sdr_write32(MSDC_DAT_RDDLY0, cur_rxdly0);
1483 sdr_write32(MSDC_DAT_RDDLY1, cur_rxdly1);
1484
1485 } while (++rxdly < 32);
1486
1487 done:
1488 return result;
1489 }
1490
1491 static int msdc_tune_bwrite(struct mmc_host *mmc, struct mmc_request *mrq)
1492 {
1493 struct msdc_host *host = mmc_priv(mmc);
1494 void __iomem *base = host->base;
1495
1496 u32 wrrdly, cur_wrrdly = 0xffffffff, orig_wrrdly;
1497 u32 dsmpl, cur_dsmpl, orig_dsmpl;
1498 u32 rxdly, cur_rxdly0;
1499 u32 orig_dat0, orig_dat1, orig_dat2, orig_dat3;
1500 u32 cur_dat0, cur_dat1, cur_dat2, cur_dat3;
1501 int result = -1;
1502 u32 skip = 1;
1503
1504 // MSDC_IOCON_DDR50CKD need to check. [Fix me]
1505
1506 sdr_get_field(MSDC_PAD_TUNE, MSDC_PAD_TUNE_DATWRDLY, &orig_wrrdly);
1507 sdr_get_field(MSDC_IOCON, MSDC_IOCON_DSPL, &orig_dsmpl);
1508
1509 /* Tune Method 2. just DAT0 */
1510 sdr_set_field(MSDC_IOCON, MSDC_IOCON_DDLSEL, 1);
1511 cur_rxdly0 = sdr_read32(MSDC_DAT_RDDLY0);
1512
1513 /* E1 ECO. YD: Reverse */
1514 if (sdr_read32(MSDC_ECO_VER) >= 4) {
1515 orig_dat0 = (cur_rxdly0 >> 24) & 0x1F;
1516 orig_dat1 = (cur_rxdly0 >> 16) & 0x1F;
1517 orig_dat2 = (cur_rxdly0 >> 8) & 0x1F;
1518 orig_dat3 = (cur_rxdly0 >> 0) & 0x1F;
1519 } else {
1520 orig_dat0 = (cur_rxdly0 >> 0) & 0x1F;
1521 orig_dat1 = (cur_rxdly0 >> 8) & 0x1F;
1522 orig_dat2 = (cur_rxdly0 >> 16) & 0x1F;
1523 orig_dat3 = (cur_rxdly0 >> 24) & 0x1F;
1524 }
1525
1526 rxdly = 0;
1527 do {
1528 wrrdly = 0;
1529 do {
1530 for (dsmpl = 0; dsmpl < 2; dsmpl++) {
1531 cur_dsmpl = (orig_dsmpl + dsmpl) % 2;
1532 if (skip == 1) {
1533 skip = 0;
1534 continue;
1535 }
1536 sdr_set_field(MSDC_IOCON, MSDC_IOCON_DSPL, cur_dsmpl);
1537
1538 if (host->app_cmd) {
1539 result = msdc_app_cmd(host->mmc, host);
1540 if (result) {
1541 ERR_MSG("TUNE_BWRITE app_cmd<%d> failed", host->mrq->cmd->opcode);
1542 continue;
1543 }
1544 }
1545 result = msdc_do_request(mmc, mrq);
1546
1547 ERR_MSG("TUNE_BWRITE<%s> DSPL<%d> DATWRDLY<%d> MSDC_DAT_RDDLY0<0x%x>",
1548 result == 0 ? "PASS" : "FAIL",
1549 cur_dsmpl, cur_wrrdly, cur_rxdly0);
1550
1551 if (result == 0) {
1552 goto done;
1553 } else {
1554 /* there is a case: command timeout, and data phase not processed */
1555 if (mrq->data->error != -EIO) {
1556 ERR_MSG("TUNE_READ: result<0x%x> cmd_error<%d> data_error<%d>",
1557 result, mrq->cmd->error, mrq->data->error);
1558 goto done;
1559 }
1560 }
1561 }
1562 cur_wrrdly = (orig_wrrdly + wrrdly + 1) % 32;
1563 sdr_set_field(MSDC_PAD_TUNE, MSDC_PAD_TUNE_DATWRDLY, cur_wrrdly);
1564 } while (++wrrdly < 32);
1565
1566 cur_dat0 = (orig_dat0 + rxdly) % 32; /* only adjust bit-1 for crc */
1567 cur_dat1 = orig_dat1;
1568 cur_dat2 = orig_dat2;
1569 cur_dat3 = orig_dat3;
1570
1571 cur_rxdly0 = (cur_dat0 << 24) | (cur_dat1 << 16) | (cur_dat2 << 8) | (cur_dat3 << 0);
1572 sdr_write32(MSDC_DAT_RDDLY0, cur_rxdly0);
1573 } while (++rxdly < 32);
1574
1575 done:
1576 return result;
1577 }
1578
1579 static int msdc_get_card_status(struct mmc_host *mmc, struct msdc_host *host, u32 *status)
1580 {
1581 struct mmc_command cmd;
1582 struct mmc_request mrq;
1583 u32 err;
1584
1585 memset(&cmd, 0, sizeof(struct mmc_command));
1586 cmd.opcode = MMC_SEND_STATUS;
1587 if (mmc->card) {
1588 cmd.arg = mmc->card->rca << 16;
1589 } else {
1590 ERR_MSG("cmd13 mmc card is null");
1591 cmd.arg = host->app_cmd_arg;
1592 }
1593 cmd.flags = MMC_RSP_SPI_R2 | MMC_RSP_R1 | MMC_CMD_AC;
1594
1595 memset(&mrq, 0, sizeof(struct mmc_request));
1596 mrq.cmd = &cmd; cmd.mrq = &mrq;
1597 cmd.data = NULL;
1598
1599 err = msdc_do_command(host, &cmd, 1, CMD_TIMEOUT);
1600
1601 if (status)
1602 *status = cmd.resp[0];
1603
1604 return err;
1605 }
1606
1607 static int msdc_check_busy(struct mmc_host *mmc, struct msdc_host *host)
1608 {
1609 u32 err = 0;
1610 u32 status = 0;
1611
1612 do {
1613 err = msdc_get_card_status(mmc, host, &status);
1614 if (err)
1615 return err;
1616 /* need cmd12? */
1617 ERR_MSG("cmd<13> resp<0x%x>", status);
1618 } while (R1_CURRENT_STATE(status) == 7);
1619
1620 return err;
1621 }
1622
1623 /* failed when msdc_do_request */
1624 static int msdc_tune_request(struct mmc_host *mmc, struct mmc_request *mrq)
1625 {
1626 struct msdc_host *host = mmc_priv(mmc);
1627 struct mmc_command *cmd;
1628 struct mmc_data *data;
1629 //u32 base = host->base;
1630 int ret = 0, read;
1631
1632 cmd = mrq->cmd;
1633 data = mrq->cmd->data;
1634
1635 read = data->flags & MMC_DATA_READ ? 1 : 0;
1636
1637 if (read) {
1638 if (data->error == -EIO)
1639 ret = msdc_tune_bread(mmc, mrq);
1640 } else {
1641 ret = msdc_check_busy(mmc, host);
1642 if (ret) {
1643 ERR_MSG("XXX cmd13 wait program done failed");
1644 return ret;
1645 }
1646 /* CRC and TO */
1647 /* Fix me: don't care card status? */
1648 ret = msdc_tune_bwrite(mmc, mrq);
1649 }
1650
1651 return ret;
1652 }
1653
1654 /* ops.request */
1655 static void msdc_ops_request(struct mmc_host *mmc, struct mmc_request *mrq)
1656 {
1657 struct msdc_host *host = mmc_priv(mmc);
1658
1659 //=== for sdio profile ===
1660 #if 0 /* --- by chhung */
1661 u32 old_H32, old_L32, new_H32, new_L32;
1662 u32 ticks = 0, opcode = 0, sizes = 0, bRx = 0;
1663 #endif /* end of --- */
1664
1665 WARN_ON(host->mrq);
1666
1667 /* start to process */
1668 spin_lock(&host->lock);
1669 #if 0 /* --- by chhung */
1670 if (sdio_pro_enable) { //=== for sdio profile ===
1671 if (mrq->cmd->opcode == 52 || mrq->cmd->opcode == 53)
1672 GPT_GetCounter64(&old_L32, &old_H32);
1673 }
1674 #endif /* end of --- */
1675
1676 host->mrq = mrq;
1677
1678 if (msdc_do_request(mmc, mrq)) {
1679 if (host->hw->flags & MSDC_REMOVABLE && ralink_soc == MT762X_SOC_MT7621AT && mrq->data && mrq->data->error)
1680 msdc_tune_request(mmc, mrq);
1681 }
1682
1683 /* ==== when request done, check if app_cmd ==== */
1684 if (mrq->cmd->opcode == MMC_APP_CMD) {
1685 host->app_cmd = 1;
1686 host->app_cmd_arg = mrq->cmd->arg; /* save the RCA */
1687 } else {
1688 host->app_cmd = 0;
1689 //host->app_cmd_arg = 0;
1690 }
1691
1692 host->mrq = NULL;
1693
1694 #if 0 /* --- by chhung */
1695 //=== for sdio profile ===
1696 if (sdio_pro_enable) {
1697 if (mrq->cmd->opcode == 52 || mrq->cmd->opcode == 53) {
1698 GPT_GetCounter64(&new_L32, &new_H32);
1699 ticks = msdc_time_calc(old_L32, old_H32, new_L32, new_H32);
1700
1701 opcode = mrq->cmd->opcode;
1702 if (mrq->cmd->data) {
1703 sizes = mrq->cmd->data->blocks * mrq->cmd->data->blksz;
1704 bRx = mrq->cmd->data->flags & MMC_DATA_READ ? 1 : 0;
1705 } else {
1706 bRx = mrq->cmd->arg & 0x80000000 ? 1 : 0;
1707 }
1708
1709 if (!mrq->cmd->error)
1710 msdc_performance(opcode, sizes, bRx, ticks);
1711 }
1712 }
1713 #endif /* end of --- */
1714 spin_unlock(&host->lock);
1715
1716 mmc_request_done(mmc, mrq);
1717
1718 return;
1719 }
1720
1721 /* called by ops.set_ios */
1722 static void msdc_set_buswidth(struct msdc_host *host, u32 width)
1723 {
1724 void __iomem *base = host->base;
1725 u32 val = sdr_read32(SDC_CFG);
1726
1727 val &= ~SDC_CFG_BUSWIDTH;
1728
1729 switch (width) {
1730 default:
1731 case MMC_BUS_WIDTH_1:
1732 width = 1;
1733 val |= (MSDC_BUS_1BITS << 16);
1734 break;
1735 case MMC_BUS_WIDTH_4:
1736 val |= (MSDC_BUS_4BITS << 16);
1737 break;
1738 case MMC_BUS_WIDTH_8:
1739 val |= (MSDC_BUS_8BITS << 16);
1740 break;
1741 }
1742
1743 sdr_write32(SDC_CFG, val);
1744
1745 N_MSG(CFG, "Bus Width = %d", width);
1746 }
1747
1748 /* ops.set_ios */
1749 static void msdc_ops_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1750 {
1751 struct msdc_host *host = mmc_priv(mmc);
1752 void __iomem *base = host->base;
1753 u32 ddr = 0;
1754
1755 #ifdef MT6575_SD_DEBUG
1756 static char *vdd[] = {
1757 "1.50v", "1.55v", "1.60v", "1.65v", "1.70v", "1.80v", "1.90v",
1758 "2.00v", "2.10v", "2.20v", "2.30v", "2.40v", "2.50v", "2.60v",
1759 "2.70v", "2.80v", "2.90v", "3.00v", "3.10v", "3.20v", "3.30v",
1760 "3.40v", "3.50v", "3.60v"
1761 };
1762 static char *power_mode[] = {
1763 "OFF", "UP", "ON"
1764 };
1765 static char *bus_mode[] = {
1766 "UNKNOWN", "OPENDRAIN", "PUSHPULL"
1767 };
1768 static char *timing[] = {
1769 "LEGACY", "MMC_HS", "SD_HS"
1770 };
1771
1772 printk("SET_IOS: CLK(%dkHz), BUS(%s), BW(%u), PWR(%s), VDD(%s), TIMING(%s)",
1773 ios->clock / 1000, bus_mode[ios->bus_mode],
1774 (ios->bus_width == MMC_BUS_WIDTH_4) ? 4 : 1,
1775 power_mode[ios->power_mode], vdd[ios->vdd], timing[ios->timing]);
1776 #endif
1777
1778 msdc_set_buswidth(host, ios->bus_width);
1779
1780 /* Power control ??? */
1781 switch (ios->power_mode) {
1782 case MMC_POWER_OFF:
1783 case MMC_POWER_UP:
1784 // msdc_set_power_mode(host, ios->power_mode); /* --- by chhung */
1785 break;
1786 case MMC_POWER_ON:
1787 host->power_mode = MMC_POWER_ON;
1788 break;
1789 default:
1790 break;
1791 }
1792
1793 /* Clock control */
1794 if (host->mclk != ios->clock) {
1795 if (ios->clock > 25000000) {
1796 //if (!(host->hw->flags & MSDC_REMOVABLE)) {
1797 INIT_MSG("SD data latch edge<%d>", MSDC_SMPL_FALLING);
1798 sdr_set_field(MSDC_IOCON, MSDC_IOCON_RSPL,
1799 MSDC_SMPL_FALLING);
1800 sdr_set_field(MSDC_IOCON, MSDC_IOCON_DSPL,
1801 MSDC_SMPL_FALLING);
1802 //} /* for tuning debug */
1803 } else { /* default value */
1804 sdr_write32(MSDC_IOCON, 0x00000000);
1805 // sdr_write32(MSDC_DAT_RDDLY0, 0x00000000);
1806 sdr_write32(MSDC_DAT_RDDLY0, 0x10101010); // for MT7620 E2 and afterward
1807 sdr_write32(MSDC_DAT_RDDLY1, 0x00000000);
1808 // sdr_write32(MSDC_PAD_TUNE, 0x00000000);
1809 sdr_write32(MSDC_PAD_TUNE, 0x84101010); // for MT7620 E2 and afterward
1810 }
1811 msdc_set_mclk(host, ddr, ios->clock);
1812 }
1813 }
1814
1815 /* ops.get_ro */
1816 static int msdc_ops_get_ro(struct mmc_host *mmc)
1817 {
1818 struct msdc_host *host = mmc_priv(mmc);
1819 void __iomem *base = host->base;
1820 unsigned long flags;
1821 int ro = 0;
1822
1823 if (host->hw->flags & MSDC_WP_PIN_EN) { /* set for card */
1824 spin_lock_irqsave(&host->lock, flags);
1825 ro = (sdr_read32(MSDC_PS) >> 31);
1826 spin_unlock_irqrestore(&host->lock, flags);
1827 }
1828 return ro;
1829 }
1830
1831 /* ops.get_cd */
1832 static int msdc_ops_get_cd(struct mmc_host *mmc)
1833 {
1834 struct msdc_host *host = mmc_priv(mmc);
1835 void __iomem *base = host->base;
1836 unsigned long flags;
1837 int present = 1;
1838
1839 /* for sdio, MSDC_REMOVABLE not set, always return 1 */
1840 if (!(host->hw->flags & MSDC_REMOVABLE)) {
1841 /* For sdio, read H/W always get<1>, but may timeout some times */
1842 #if 1
1843 host->card_inserted = 1;
1844 return 1;
1845 #else
1846 host->card_inserted = (host->pm_state.event == PM_EVENT_USER_RESUME) ? 1 : 0;
1847 INIT_MSG("sdio ops_get_cd<%d>", host->card_inserted);
1848 return host->card_inserted;
1849 #endif
1850 }
1851
1852 /* MSDC_CD_PIN_EN set for card */
1853 if (host->hw->flags & MSDC_CD_PIN_EN) {
1854 spin_lock_irqsave(&host->lock, flags);
1855 #if 0
1856 present = host->card_inserted; /* why not read from H/W: Fix me*/
1857 #else
1858 // CD
1859 if (cd_active_low)
1860 present = (sdr_read32(MSDC_PS) & MSDC_PS_CDSTS) ? 0 : 1;
1861 else
1862 present = (sdr_read32(MSDC_PS) & MSDC_PS_CDSTS) ? 1 : 0;
1863 if (host->mmc->caps & MMC_CAP_NEEDS_POLL)
1864 present = 1;
1865 host->card_inserted = present;
1866 #endif
1867 spin_unlock_irqrestore(&host->lock, flags);
1868 } else {
1869 present = 0; /* TODO? Check DAT3 pins for card detection */
1870 }
1871
1872 INIT_MSG("ops_get_cd return<%d>", present);
1873 return present;
1874 }
1875
1876 static struct mmc_host_ops mt_msdc_ops = {
1877 .request = msdc_ops_request,
1878 .set_ios = msdc_ops_set_ios,
1879 .get_ro = msdc_ops_get_ro,
1880 .get_cd = msdc_ops_get_cd,
1881 };
1882
1883 /*--------------------------------------------------------------------------*/
1884 /* interrupt handler */
1885 /*--------------------------------------------------------------------------*/
1886 static irqreturn_t msdc_irq(int irq, void *dev_id)
1887 {
1888 struct msdc_host *host = (struct msdc_host *)dev_id;
1889 struct mmc_data *data = host->data;
1890 struct mmc_command *cmd = host->cmd;
1891 void __iomem *base = host->base;
1892
1893 u32 cmdsts = MSDC_INT_RSPCRCERR | MSDC_INT_CMDTMO | MSDC_INT_CMDRDY |
1894 MSDC_INT_ACMDCRCERR | MSDC_INT_ACMDTMO | MSDC_INT_ACMDRDY |
1895 MSDC_INT_ACMD19_DONE;
1896 u32 datsts = MSDC_INT_DATCRCERR | MSDC_INT_DATTMO;
1897
1898 u32 intsts = sdr_read32(MSDC_INT);
1899 u32 inten = sdr_read32(MSDC_INTEN); inten &= intsts;
1900
1901 sdr_write32(MSDC_INT, intsts); /* clear interrupts */
1902 /* MSG will cause fatal error */
1903
1904 /* card change interrupt */
1905 if (intsts & MSDC_INT_CDSC) {
1906 if (host->mmc->caps & MMC_CAP_NEEDS_POLL)
1907 return IRQ_HANDLED;
1908 IRQ_MSG("MSDC_INT_CDSC irq<0x%.8x>", intsts);
1909 schedule_delayed_work(&host->card_delaywork, HZ);
1910 /* tuning when plug card ? */
1911 }
1912
1913 /* sdio interrupt */
1914 if (intsts & MSDC_INT_SDIOIRQ) {
1915 IRQ_MSG("XXX MSDC_INT_SDIOIRQ"); /* seems not sdio irq */
1916 //mmc_signal_sdio_irq(host->mmc);
1917 }
1918
1919 /* transfer complete interrupt */
1920 if (data != NULL) {
1921 if (inten & MSDC_INT_XFER_COMPL) {
1922 data->bytes_xfered = host->xfer_size;
1923 complete(&host->xfer_done);
1924 }
1925
1926 if (intsts & datsts) {
1927 /* do basic reset, or stop command will sdc_busy */
1928 msdc_reset_hw(host);
1929 msdc_clr_fifo();
1930 msdc_clr_int();
1931
1932 if (intsts & MSDC_INT_DATTMO) {
1933 IRQ_MSG("XXX CMD<%d> MSDC_INT_DATTMO", host->mrq->cmd->opcode);
1934 data->error = -ETIMEDOUT;
1935 } else if (intsts & MSDC_INT_DATCRCERR) {
1936 IRQ_MSG("XXX CMD<%d> MSDC_INT_DATCRCERR, SDC_DCRC_STS<0x%x>", host->mrq->cmd->opcode, sdr_read32(SDC_DCRC_STS));
1937 data->error = -EIO;
1938 }
1939
1940 //if(sdr_read32(MSDC_INTEN) & MSDC_INT_XFER_COMPL) {
1941 complete(&host->xfer_done); /* Read CRC come fast, XFER_COMPL not enabled */
1942 }
1943 }
1944
1945 /* command interrupts */
1946 if ((cmd != NULL) && (intsts & cmdsts)) {
1947 if ((intsts & MSDC_INT_CMDRDY) || (intsts & MSDC_INT_ACMDRDY) ||
1948 (intsts & MSDC_INT_ACMD19_DONE)) {
1949 u32 *rsp = &cmd->resp[0];
1950
1951 switch (host->cmd_rsp) {
1952 case RESP_NONE:
1953 break;
1954 case RESP_R2:
1955 *rsp++ = sdr_read32(SDC_RESP3); *rsp++ = sdr_read32(SDC_RESP2);
1956 *rsp++ = sdr_read32(SDC_RESP1); *rsp++ = sdr_read32(SDC_RESP0);
1957 break;
1958 default: /* Response types 1, 3, 4, 5, 6, 7(1b) */
1959 if ((intsts & MSDC_INT_ACMDRDY) || (intsts & MSDC_INT_ACMD19_DONE))
1960 *rsp = sdr_read32(SDC_ACMD_RESP);
1961 else
1962 *rsp = sdr_read32(SDC_RESP0);
1963 break;
1964 }
1965 } else if ((intsts & MSDC_INT_RSPCRCERR) || (intsts & MSDC_INT_ACMDCRCERR)) {
1966 if (intsts & MSDC_INT_ACMDCRCERR)
1967 IRQ_MSG("XXX CMD<%d> MSDC_INT_ACMDCRCERR", cmd->opcode);
1968 else
1969 IRQ_MSG("XXX CMD<%d> MSDC_INT_RSPCRCERR", cmd->opcode);
1970 cmd->error = -EIO;
1971 } else if ((intsts & MSDC_INT_CMDTMO) || (intsts & MSDC_INT_ACMDTMO)) {
1972 if (intsts & MSDC_INT_ACMDTMO)
1973 IRQ_MSG("XXX CMD<%d> MSDC_INT_ACMDTMO", cmd->opcode);
1974 else
1975 IRQ_MSG("XXX CMD<%d> MSDC_INT_CMDTMO", cmd->opcode);
1976 cmd->error = -ETIMEDOUT;
1977 msdc_reset_hw(host);
1978 msdc_clr_fifo();
1979 msdc_clr_int();
1980 }
1981 complete(&host->cmd_done);
1982 }
1983
1984 /* mmc irq interrupts */
1985 if (intsts & MSDC_INT_MMCIRQ)
1986 printk(KERN_INFO "msdc[%d] MMCIRQ: SDC_CSTS=0x%.8x\r\n", host->id, sdr_read32(SDC_CSTS));
1987
1988 #ifdef MT6575_SD_DEBUG
1989 {
1990 /* msdc_int_reg *int_reg = (msdc_int_reg*)&intsts;*/
1991 N_MSG(INT, "IRQ_EVT(0x%x): MMCIRQ(%d) CDSC(%d), ACRDY(%d), ACTMO(%d), ACCRE(%d) AC19DN(%d)",
1992 intsts,
1993 int_reg->mmcirq,
1994 int_reg->cdsc,
1995 int_reg->atocmdrdy,
1996 int_reg->atocmdtmo,
1997 int_reg->atocmdcrc,
1998 int_reg->atocmd19done);
1999 N_MSG(INT, "IRQ_EVT(0x%x): SDIO(%d) CMDRDY(%d), CMDTMO(%d), RSPCRC(%d), CSTA(%d)",
2000 intsts,
2001 int_reg->sdioirq,
2002 int_reg->cmdrdy,
2003 int_reg->cmdtmo,
2004 int_reg->rspcrc,
2005 int_reg->csta);
2006 N_MSG(INT, "IRQ_EVT(0x%x): XFCMP(%d) DXDONE(%d), DATTMO(%d), DATCRC(%d), DMAEMP(%d)",
2007 intsts,
2008 int_reg->xfercomp,
2009 int_reg->dxferdone,
2010 int_reg->dattmo,
2011 int_reg->datcrc,
2012 int_reg->dmaqempty);
2013 }
2014 #endif
2015
2016 return IRQ_HANDLED;
2017 }
2018
2019 /*--------------------------------------------------------------------------*/
2020 /* platform_driver members */
2021 /*--------------------------------------------------------------------------*/
2022 /* called by msdc_drv_probe/remove */
2023 static void msdc_enable_cd_irq(struct msdc_host *host, int enable)
2024 {
2025 struct msdc_hw *hw = host->hw;
2026 void __iomem *base = host->base;
2027
2028 /* for sdio, not set */
2029 if ((hw->flags & MSDC_CD_PIN_EN) == 0) {
2030 /* Pull down card detection pin since it is not avaiable */
2031 /*
2032 if (hw->config_gpio_pin)
2033 hw->config_gpio_pin(MSDC_CD_PIN, GPIO_PULL_DOWN);
2034 */
2035 sdr_clr_bits(MSDC_PS, MSDC_PS_CDEN);
2036 sdr_clr_bits(MSDC_INTEN, MSDC_INTEN_CDSC);
2037 sdr_clr_bits(SDC_CFG, SDC_CFG_INSWKUP);
2038 return;
2039 }
2040
2041 N_MSG(CFG, "CD IRQ Eanable(%d)", enable);
2042
2043 if (enable) {
2044 /* card detection circuit relies on the core power so that the core power
2045 * shouldn't be turned off. Here adds a reference count to keep
2046 * the core power alive.
2047 */
2048 //msdc_vcore_on(host); //did in msdc_init_hw()
2049
2050 if (hw->config_gpio_pin) /* NULL */
2051 hw->config_gpio_pin(MSDC_CD_PIN, GPIO_PULL_UP);
2052
2053 sdr_set_field(MSDC_PS, MSDC_PS_CDDEBOUNCE, DEFAULT_DEBOUNCE);
2054 sdr_set_bits(MSDC_PS, MSDC_PS_CDEN);
2055 sdr_set_bits(MSDC_INTEN, MSDC_INTEN_CDSC);
2056 sdr_set_bits(SDC_CFG, SDC_CFG_INSWKUP); /* not in document! Fix me */
2057 } else {
2058 if (hw->config_gpio_pin) /* NULL */
2059 hw->config_gpio_pin(MSDC_CD_PIN, GPIO_PULL_DOWN);
2060
2061 sdr_clr_bits(SDC_CFG, SDC_CFG_INSWKUP);
2062 sdr_clr_bits(MSDC_PS, MSDC_PS_CDEN);
2063 sdr_clr_bits(MSDC_INTEN, MSDC_INTEN_CDSC);
2064
2065 /* Here decreases a reference count to core power since card
2066 * detection circuit is shutdown.
2067 */
2068 //msdc_vcore_off(host);
2069 }
2070 }
2071
2072 /* called by msdc_drv_probe */
2073 static void msdc_init_hw(struct msdc_host *host)
2074 {
2075 void __iomem *base = host->base;
2076
2077 /* Power on */
2078 #if 0 /* --- by chhung */
2079 msdc_vcore_on(host);
2080 msdc_pin_reset(host, MSDC_PIN_PULL_UP);
2081 msdc_select_clksrc(host, hw->clk_src);
2082 enable_clock(PERI_MSDC0_PDN + host->id, "SD");
2083 msdc_vdd_on(host);
2084 #endif /* end of --- */
2085 /* Configure to MMC/SD mode */
2086 sdr_set_field(MSDC_CFG, MSDC_CFG_MODE, MSDC_SDMMC);
2087
2088 /* Reset */
2089 msdc_reset_hw(host);
2090 msdc_clr_fifo();
2091
2092 /* Disable card detection */
2093 sdr_clr_bits(MSDC_PS, MSDC_PS_CDEN);
2094
2095 /* Disable and clear all interrupts */
2096 sdr_clr_bits(MSDC_INTEN, sdr_read32(MSDC_INTEN));
2097 sdr_write32(MSDC_INT, sdr_read32(MSDC_INT));
2098
2099 #if 1
2100 /* reset tuning parameter */
2101 sdr_write32(MSDC_PAD_CTL0, 0x00090000);
2102 sdr_write32(MSDC_PAD_CTL1, 0x000A0000);
2103 sdr_write32(MSDC_PAD_CTL2, 0x000A0000);
2104 // sdr_write32(MSDC_PAD_TUNE, 0x00000000);
2105 sdr_write32(MSDC_PAD_TUNE, 0x84101010); // for MT7620 E2 and afterward
2106 // sdr_write32(MSDC_DAT_RDDLY0, 0x00000000);
2107 sdr_write32(MSDC_DAT_RDDLY0, 0x10101010); // for MT7620 E2 and afterward
2108 sdr_write32(MSDC_DAT_RDDLY1, 0x00000000);
2109 sdr_write32(MSDC_IOCON, 0x00000000);
2110 #if 0 // use MT7620 default value: 0x403c004f
2111 sdr_write32(MSDC_PATCH_BIT0, 0x003C000F); /* bit0 modified: Rx Data Clock Source: 1 -> 2.0*/
2112 #endif
2113
2114 if (sdr_read32(MSDC_ECO_VER) >= 4) {
2115 if (host->id == 1) {
2116 sdr_set_field(MSDC_PATCH_BIT1, MSDC_PATCH_BIT1_WRDAT_CRCS, 1);
2117 sdr_set_field(MSDC_PATCH_BIT1, MSDC_PATCH_BIT1_CMD_RSP, 1);
2118
2119 /* internal clock: latch read data */
2120 sdr_set_bits(MSDC_PATCH_BIT0, MSDC_PATCH_BIT_CKGEN_CK);
2121 }
2122 }
2123 #endif
2124
2125 /* for safety, should clear SDC_CFG.SDIO_INT_DET_EN & set SDC_CFG.SDIO in
2126 pre-loader,uboot,kernel drivers. and SDC_CFG.SDIO_INT_DET_EN will be only
2127 set when kernel driver wants to use SDIO bus interrupt */
2128 /* Configure to enable SDIO mode. it's must otherwise sdio cmd5 failed */
2129 sdr_set_bits(SDC_CFG, SDC_CFG_SDIO);
2130
2131 /* disable detect SDIO device interupt function */
2132 sdr_clr_bits(SDC_CFG, SDC_CFG_SDIOIDE);
2133
2134 /* eneable SMT for glitch filter */
2135 sdr_set_bits(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKSMT);
2136 sdr_set_bits(MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDSMT);
2137 sdr_set_bits(MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATSMT);
2138
2139 #if 1
2140 /* set clk, cmd, dat pad driving */
2141 sdr_set_field(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKDRVN, 4);
2142 sdr_set_field(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKDRVP, 4);
2143 sdr_set_field(MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDDRVN, 4);
2144 sdr_set_field(MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDDRVP, 4);
2145 sdr_set_field(MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATDRVN, 4);
2146 sdr_set_field(MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATDRVP, 4);
2147 #else
2148 sdr_set_field(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKDRVN, 0);
2149 sdr_set_field(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKDRVP, 0);
2150 sdr_set_field(MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDDRVN, 0);
2151 sdr_set_field(MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDDRVP, 0);
2152 sdr_set_field(MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATDRVN, 0);
2153 sdr_set_field(MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATDRVP, 0);
2154 #endif
2155
2156 /* set sampling edge */
2157
2158 /* write crc timeout detection */
2159 sdr_set_field(MSDC_PATCH_BIT0, 1 << 30, 1);
2160
2161 /* Configure to default data timeout */
2162 sdr_set_field(SDC_CFG, SDC_CFG_DTOC, DEFAULT_DTOC);
2163
2164 msdc_set_buswidth(host, MMC_BUS_WIDTH_1);
2165
2166 N_MSG(FUC, "init hardware done!");
2167 }
2168
2169 /* called by msdc_drv_remove */
2170 static void msdc_deinit_hw(struct msdc_host *host)
2171 {
2172 void __iomem *base = host->base;
2173
2174 /* Disable and clear all interrupts */
2175 sdr_clr_bits(MSDC_INTEN, sdr_read32(MSDC_INTEN));
2176 sdr_write32(MSDC_INT, sdr_read32(MSDC_INT));
2177
2178 /* Disable card detection */
2179 msdc_enable_cd_irq(host, 0);
2180 // msdc_set_power_mode(host, MMC_POWER_OFF); /* make sure power down */ /* --- by chhung */
2181 }
2182
2183 /* init gpd and bd list in msdc_drv_probe */
2184 static void msdc_init_gpd_bd(struct msdc_host *host, struct msdc_dma *dma)
2185 {
2186 struct gpd *gpd = dma->gpd;
2187 struct bd *bd = dma->bd;
2188 int i;
2189
2190 /* we just support one gpd, but gpd->next must be set for desc
2191 * DMA. That's why we alloc 2 gpd structurs.
2192 */
2193
2194 memset(gpd, 0, sizeof(struct gpd) * 2);
2195
2196 gpd->bdp = 1; /* hwo, cs, bd pointer */
2197 gpd->ptr = (void *)dma->bd_addr; /* physical address */
2198 gpd->next = (void *)((u32)dma->gpd_addr + sizeof(struct gpd));
2199
2200 memset(bd, 0, sizeof(struct bd) * MAX_BD_NUM);
2201 for (i = 0; i < (MAX_BD_NUM - 1); i++)
2202 bd[i].next = (void *)(dma->bd_addr + sizeof(*bd) * (i + 1));
2203 }
2204
2205 static int msdc_drv_probe(struct platform_device *pdev)
2206 {
2207 struct resource *res;
2208 __iomem void *base;
2209 struct mmc_host *mmc;
2210 struct msdc_host *host;
2211 struct msdc_hw *hw;
2212 int ret;
2213
2214 //FIXME: this should be done by pinconf and not by the sd driver
2215 if ((ralink_soc == MT762X_SOC_MT7688 ||
2216 ralink_soc == MT762X_SOC_MT7628AN) &&
2217 (!(rt_sysc_r32(0x60) & BIT(15))))
2218 rt_sysc_m32(0xf << 17, 0xf << 17, 0x3c);
2219
2220 hw = &msdc0_hw;
2221
2222 if (of_property_read_bool(pdev->dev.of_node, "mtk,wp-en"))
2223 msdc0_hw.flags |= MSDC_WP_PIN_EN;
2224
2225 /* Allocate MMC host for this device */
2226 mmc = mmc_alloc_host(sizeof(struct msdc_host), &pdev->dev);
2227 if (!mmc)
2228 return -ENOMEM;
2229
2230 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2231 base = devm_ioremap_resource(&pdev->dev, res);
2232 if (IS_ERR(base)) {
2233 ret = PTR_ERR(base);
2234 goto host_free;
2235 }
2236
2237 /* Set host parameters to mmc */
2238 mmc->ops = &mt_msdc_ops;
2239 mmc->f_min = HOST_MIN_MCLK;
2240 mmc->f_max = HOST_MAX_MCLK;
2241 mmc->ocr_avail = MSDC_OCR_AVAIL;
2242
2243 mmc->caps = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED;
2244
2245 //TODO: read this as bus-width from dt (via mmc_of_parse)
2246 mmc->caps |= MMC_CAP_4_BIT_DATA;
2247
2248 cd_active_low = !of_property_read_bool(pdev->dev.of_node, "mediatek,cd-high");
2249
2250 if (of_property_read_bool(pdev->dev.of_node, "mediatek,cd-poll"))
2251 mmc->caps |= MMC_CAP_NEEDS_POLL;
2252
2253 /* MMC core transfer sizes tunable parameters */
2254 mmc->max_segs = MAX_HW_SGMTS;
2255
2256 mmc->max_seg_size = MAX_SGMT_SZ;
2257 mmc->max_blk_size = HOST_MAX_BLKSZ;
2258 mmc->max_req_size = MAX_REQ_SZ;
2259 mmc->max_blk_count = mmc->max_req_size;
2260
2261 host = mmc_priv(mmc);
2262 host->hw = hw;
2263 host->mmc = mmc;
2264 host->id = pdev->id;
2265 if (host->id < 0 || host->id >= 4)
2266 host->id = 0;
2267 host->error = 0;
2268
2269 host->irq = platform_get_irq(pdev, 0);
2270 if (host->irq < 0) {
2271 ret = -EINVAL;
2272 goto host_free;
2273 }
2274
2275 host->base = base;
2276 host->mclk = 0; /* mclk: the request clock of mmc sub-system */
2277 host->hclk = hclks[hw->clk_src]; /* hclk: clock of clock source to msdc controller */
2278 host->sclk = 0; /* sclk: the really clock after divition */
2279 host->pm_state = PMSG_RESUME;
2280 host->suspend = 0;
2281 host->core_clkon = 0;
2282 host->card_clkon = 0;
2283 host->core_power = 0;
2284 host->power_mode = MMC_POWER_OFF;
2285 // host->card_inserted = hw->flags & MSDC_REMOVABLE ? 0 : 1;
2286 host->timeout_ns = 0;
2287 host->timeout_clks = DEFAULT_DTOC * 65536;
2288
2289 host->mrq = NULL;
2290 //init_MUTEX(&host->sem); /* we don't need to support multiple threads access */
2291
2292 dma_coerce_mask_and_coherent(mmc_dev(mmc), DMA_BIT_MASK(32));
2293
2294 /* using dma_alloc_coherent*/ /* todo: using 1, for all 4 slots */
2295 host->dma.gpd = dma_alloc_coherent(&pdev->dev,
2296 MAX_GPD_NUM * sizeof(struct gpd),
2297 &host->dma.gpd_addr, GFP_KERNEL);
2298 host->dma.bd = dma_alloc_coherent(&pdev->dev,
2299 MAX_BD_NUM * sizeof(struct bd),
2300 &host->dma.bd_addr, GFP_KERNEL);
2301 if (!host->dma.gpd || !host->dma.bd) {
2302 ret = -ENOMEM;
2303 goto release_mem;
2304 }
2305 msdc_init_gpd_bd(host, &host->dma);
2306
2307 INIT_DELAYED_WORK(&host->card_delaywork, msdc_tasklet_card);
2308 spin_lock_init(&host->lock);
2309 msdc_init_hw(host);
2310
2311 /* TODO check weather flags 0 is correct, the mtk-sd driver uses
2312 * IRQF_TRIGGER_LOW | IRQF_ONESHOT for flags
2313 *
2314 * for flags 0 the trigger polarity is determined by the
2315 * device tree, but not the oneshot flag, but maybe it is also
2316 * not needed because the soc could be oneshot safe.
2317 */
2318 ret = devm_request_irq(&pdev->dev, host->irq, msdc_irq, 0, pdev->name,
2319 host);
2320 if (ret)
2321 goto release;
2322
2323 platform_set_drvdata(pdev, mmc);
2324
2325 ret = mmc_add_host(mmc);
2326 if (ret)
2327 goto release;
2328
2329 /* Config card detection pin and enable interrupts */
2330 if (hw->flags & MSDC_CD_PIN_EN) { /* set for card */
2331 msdc_enable_cd_irq(host, 1);
2332 } else {
2333 msdc_enable_cd_irq(host, 0);
2334 }
2335
2336 return 0;
2337
2338 release:
2339 platform_set_drvdata(pdev, NULL);
2340 msdc_deinit_hw(host);
2341 cancel_delayed_work_sync(&host->card_delaywork);
2342
2343 release_mem:
2344 if (host->dma.gpd)
2345 dma_free_coherent(&pdev->dev, MAX_GPD_NUM * sizeof(struct gpd),
2346 host->dma.gpd, host->dma.gpd_addr);
2347 if (host->dma.bd)
2348 dma_free_coherent(&pdev->dev, MAX_BD_NUM * sizeof(struct bd),
2349 host->dma.bd, host->dma.bd_addr);
2350 host_free:
2351 mmc_free_host(mmc);
2352
2353 return ret;
2354 }
2355
2356 /* 4 device share one driver, using "drvdata" to show difference */
2357 static int msdc_drv_remove(struct platform_device *pdev)
2358 {
2359 struct mmc_host *mmc;
2360 struct msdc_host *host;
2361
2362 mmc = platform_get_drvdata(pdev);
2363 BUG_ON(!mmc);
2364
2365 host = mmc_priv(mmc);
2366 BUG_ON(!host);
2367
2368 ERR_MSG("removed !!!");
2369
2370 platform_set_drvdata(pdev, NULL);
2371 mmc_remove_host(host->mmc);
2372 msdc_deinit_hw(host);
2373
2374 cancel_delayed_work_sync(&host->card_delaywork);
2375
2376 dma_free_coherent(&pdev->dev, MAX_GPD_NUM * sizeof(struct gpd),
2377 host->dma.gpd, host->dma.gpd_addr);
2378 dma_free_coherent(&pdev->dev, MAX_BD_NUM * sizeof(struct bd),
2379 host->dma.bd, host->dma.bd_addr);
2380
2381 mmc_free_host(host->mmc);
2382
2383 return 0;
2384 }
2385
2386 /* Fix me: Power Flow */
2387 #ifdef CONFIG_PM
2388
2389 static void msdc_drv_pm(struct platform_device *pdev, pm_message_t state)
2390 {
2391 struct mmc_host *mmc = platform_get_drvdata(pdev);
2392 if (mmc) {
2393 struct msdc_host *host = mmc_priv(mmc);
2394 msdc_pm(state, (void *)host);
2395 }
2396 }
2397
2398 static int msdc_drv_suspend(struct platform_device *pdev, pm_message_t state)
2399 {
2400 if (state.event == PM_EVENT_SUSPEND)
2401 msdc_drv_pm(pdev, state);
2402 return 0;
2403 }
2404
2405 static int msdc_drv_resume(struct platform_device *pdev)
2406 {
2407 struct pm_message state;
2408
2409 state.event = PM_EVENT_RESUME;
2410 msdc_drv_pm(pdev, state);
2411 return 0;
2412 }
2413 #endif
2414
2415 static const struct of_device_id mt7620_sdhci_match[] = {
2416 { .compatible = "ralink,mt7620-sdhci" },
2417 {},
2418 };
2419 MODULE_DEVICE_TABLE(of, mt7620_sdhci_match);
2420
2421 static struct platform_driver mt_msdc_driver = {
2422 .probe = msdc_drv_probe,
2423 .remove = msdc_drv_remove,
2424 #ifdef CONFIG_PM
2425 .suspend = msdc_drv_suspend,
2426 .resume = msdc_drv_resume,
2427 #endif
2428 .driver = {
2429 .name = DRV_NAME,
2430 .of_match_table = mt7620_sdhci_match,
2431 },
2432 };
2433
2434 /*--------------------------------------------------------------------------*/
2435 /* module init/exit */
2436 /*--------------------------------------------------------------------------*/
2437 static int __init mt_msdc_init(void)
2438 {
2439 int ret;
2440
2441 ret = platform_driver_register(&mt_msdc_driver);
2442 if (ret) {
2443 printk(KERN_ERR DRV_NAME ": Can't register driver");
2444 return ret;
2445 }
2446
2447 #if defined(MT6575_SD_DEBUG)
2448 msdc_debug_proc_init();
2449 #endif
2450 return 0;
2451 }
2452
2453 static void __exit mt_msdc_exit(void)
2454 {
2455 platform_driver_unregister(&mt_msdc_driver);
2456 }
2457
2458 module_init(mt_msdc_init);
2459 module_exit(mt_msdc_exit);
2460 MODULE_LICENSE("GPL");
2461 MODULE_DESCRIPTION("MediaTek MT6575 SD/MMC Card Driver");
2462 MODULE_AUTHOR("Infinity Chen <infinity.chen@mediatek.com>");
Staging tree of Mathias Kresin