target/linux/ramips/files/drivers/net/ethernet/ralink/gsw_mt7620.c

   1 /*   This program is free software; you can redistribute it and/or modify
   2  *   it under the terms of the GNU General Public License as published by
   3  *   the Free Software Foundation; version 2 of the License
   4  *
   5  *   This program is distributed in the hope that it will be useful,
   6  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
   7  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   8  *   GNU General Public License for more details.
   9  *
  10  *   Copyright (C) 2009-2015 John Crispin <blogic@openwrt.org>
  11  *   Copyright (C) 2009-2015 Felix Fietkau <nbd@nbd.name>
  12  *   Copyright (C) 2013-2015 Michael Lee <igvtee@gmail.com>
  13  */
  14
  15 #include <linux/module.h>
  16 #include <linux/kernel.h>
  17 #include <linux/types.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/of_device.h>
  20 #include <linux/of_irq.h>
  21
  22 #include <ralink_regs.h>
  23
  24 #include "mtk_eth_soc.h"
  25 #include "gsw_mt7620.h"
  26
  27 void mtk_switch_w32(struct mt7620_gsw *gsw, u32 val, unsigned reg)
  28 {
  29         iowrite32(val, gsw->base + reg);
  30 }
  31
  32 u32 mtk_switch_r32(struct mt7620_gsw *gsw, unsigned reg)
  33 {
  34         return ioread32(gsw->base + reg);
  35 }
  36
  37 static irqreturn_t gsw_interrupt_mt7620(int irq, void *_priv)
  38 {
  39         struct fe_priv *priv = (struct fe_priv *)_priv;
  40         struct mt7620_gsw *gsw = (struct mt7620_gsw *)priv->soc->swpriv;
  41         u32 status;
  42         int i, max = (gsw->port4 == PORT4_EPHY) ? (4) : (3);
  43
  44         status = mtk_switch_r32(gsw, GSW_REG_ISR);
  45         if (status & PORT_IRQ_ST_CHG)
  46                 for (i = 0; i <= max; i++) {
  47                         u32 status = mtk_switch_r32(gsw, GSW_REG_PORT_STATUS(i));
  48                         int link = status & 0x1;
  49
  50                         if (link != priv->link[i])
  51                                 mt7620_print_link_state(priv, i, link,
  52                                                         (status >> 2) & 3,
  53                                                         (status & 0x2));
  54
  55                         priv->link[i] = link;
  56                 }
  57         mt7620_handle_carrier(priv);
  58         mtk_switch_w32(gsw, status, GSW_REG_ISR);
  59
  60         return IRQ_HANDLED;
  61 }
  62
  63 static int mt7620_mdio_mode(struct device_node *eth_node)
  64 {
  65         struct device_node *phy_node, *mdiobus_node;
  66         const __be32 *id;
  67         int ret = 0;
  68
  69         mdiobus_node = of_get_child_by_name(eth_node, "mdio-bus");
  70
  71         if (mdiobus_node) {
  72                 if (of_property_read_bool(mdiobus_node, "mediatek,mdio-mode"))
  73                         ret = 1;
  74
  75                 for_each_child_of_node(mdiobus_node, phy_node) {
  76                         id = of_get_property(phy_node, "reg", NULL);
  77                         if (id && (be32_to_cpu(*id) == 0x1f))
  78                                 ret = 1;
  79                 }
  80
  81                 of_node_put(mdiobus_node);
  82         }
  83
  84         return ret;
  85 }
  86
  87 static void mt7620_hw_init(struct mt7620_gsw *gsw, int mdio_mode)
  88 {
  89         u32 i;
  90         u32 val;
  91         u32 is_BGA = (rt_sysc_r32(0x0c) >> 16) & 1;
  92
  93         rt_sysc_w32(rt_sysc_r32(SYSC_REG_CFG1) | BIT(8), SYSC_REG_CFG1);
  94         mtk_switch_w32(gsw, mtk_switch_r32(gsw, GSW_REG_CKGCR) & ~(0x3 << 4), GSW_REG_CKGCR);
  95
  96         /* Enable MIB stats */
  97         mtk_switch_w32(gsw, mtk_switch_r32(gsw, GSW_REG_MIB_CNT_EN) | (1 << 1), GSW_REG_MIB_CNT_EN);
  98
  99         if (mdio_mode) {
 100                 u32 val;
 101
 102                 /* turn off ephy and set phy base addr to 12 */
 103                 mtk_switch_w32(gsw, mtk_switch_r32(gsw, GSW_REG_GPC1) |
 104                         (0x1f << 24) | (0xc << 16),
 105                         GSW_REG_GPC1);
 106
 107                 /* set MT7530 central align */
 108                 val = mt7530_mdio_r32(gsw, 0x7830);
 109                 val &= ~BIT(0);
 110                 val |= BIT(1);
 111                 mt7530_mdio_w32(gsw, 0x7830, val);
 112
 113                 val = mt7530_mdio_r32(gsw, 0x7a40);
 114                 val &= ~BIT(30);
 115                 mt7530_mdio_w32(gsw, 0x7a40, val);
 116
 117                 mt7530_mdio_w32(gsw, 0x7a78, 0x855);
 118         } else {
 119
 120                 if (gsw->ephy_base) {
 121                         /* set phy base addr to ephy_base */
 122                         mtk_switch_w32(gsw, mtk_switch_r32(gsw, GSW_REG_GPC1) |
 123                                 (gsw->ephy_base << 16),
 124                                 GSW_REG_GPC1);
 125                         fe_reset(BIT(24)); /* Resets the Ethernet PHY block. */
 126                 }
 127
 128                 /* global page 4 */
 129                 _mt7620_mii_write(gsw, gsw->ephy_base + 1, 31, 0x4000);
 130
 131                 _mt7620_mii_write(gsw, gsw->ephy_base + 1, 17, 0x7444);
 132                 if (is_BGA)
 133                         _mt7620_mii_write(gsw, gsw->ephy_base + 1, 19, 0x0114);
 134                 else
 135                         _mt7620_mii_write(gsw, gsw->ephy_base + 1, 19, 0x0117);
 136
 137                 _mt7620_mii_write(gsw, gsw->ephy_base + 1, 22, 0x10cf);
 138                 _mt7620_mii_write(gsw, gsw->ephy_base + 1, 25, 0x6212);
 139                 _mt7620_mii_write(gsw, gsw->ephy_base + 1, 26, 0x0777);
 140                 _mt7620_mii_write(gsw, gsw->ephy_base + 1, 29, 0x4000);
 141                 _mt7620_mii_write(gsw, gsw->ephy_base + 1, 28, 0xc077);
 142                 _mt7620_mii_write(gsw, gsw->ephy_base + 1, 24, 0x0000);
 143
 144                 /* global page 3 */
 145                 _mt7620_mii_write(gsw, gsw->ephy_base + 1, 31, 0x3000);
 146                 _mt7620_mii_write(gsw, gsw->ephy_base + 1, 17, 0x4838);
 147
 148                 /* global page 2 */
 149                 _mt7620_mii_write(gsw, gsw->ephy_base + 1, 31, 0x2000);
 150                 if (is_BGA) {
 151                         _mt7620_mii_write(gsw, gsw->ephy_base + 1, 21, 0x0515);
 152                         _mt7620_mii_write(gsw, gsw->ephy_base + 1, 22, 0x0053);
 153                         _mt7620_mii_write(gsw, gsw->ephy_base + 1, 23, 0x00bf);
 154                         _mt7620_mii_write(gsw, gsw->ephy_base + 1, 24, 0x0aaf);
 155                         _mt7620_mii_write(gsw, gsw->ephy_base + 1, 25, 0x0fad);
 156                         _mt7620_mii_write(gsw, gsw->ephy_base + 1, 26, 0x0fc1);
 157                 } else {
 158                         _mt7620_mii_write(gsw, gsw->ephy_base + 1, 21, 0x0517);
 159                         _mt7620_mii_write(gsw, gsw->ephy_base + 1, 22, 0x0fd2);
 160                         _mt7620_mii_write(gsw, gsw->ephy_base + 1, 23, 0x00bf);
 161                         _mt7620_mii_write(gsw, gsw->ephy_base + 1, 24, 0x0aab);
 162                         _mt7620_mii_write(gsw, gsw->ephy_base + 1, 25, 0x00ae);
 163                         _mt7620_mii_write(gsw, gsw->ephy_base + 1, 26, 0x0fff);
 164                 }
 165                 /* global page 1 */
 166                 _mt7620_mii_write(gsw, gsw->ephy_base + 1, 31, 0x1000);
 167                 _mt7620_mii_write(gsw, gsw->ephy_base + 1, 17, 0xe7f8);
 168
 169                 /* turn on all PHYs */
 170                 for (i = 0; i <= 4; i++) {
 171                         val = _mt7620_mii_read(gsw, gsw->ephy_base + i, 0);
 172                         val &= ~BIT(11);
 173                         _mt7620_mii_write(gsw, gsw->ephy_base + i, 0, val);
 174                 }
 175         }
 176
 177         /* global page 0 */
 178         _mt7620_mii_write(gsw, gsw->ephy_base + 1, 31, 0x8000);
 179         _mt7620_mii_write(gsw, gsw->ephy_base + 0, 30, 0xa000);
 180         _mt7620_mii_write(gsw, gsw->ephy_base + 1, 30, 0xa000);
 181         _mt7620_mii_write(gsw, gsw->ephy_base + 2, 30, 0xa000);
 182         _mt7620_mii_write(gsw, gsw->ephy_base + 3, 30, 0xa000);
 183
 184         _mt7620_mii_write(gsw, gsw->ephy_base + 0, 4, 0x05e1);
 185         _mt7620_mii_write(gsw, gsw->ephy_base + 1, 4, 0x05e1);
 186         _mt7620_mii_write(gsw, gsw->ephy_base + 2, 4, 0x05e1);
 187         _mt7620_mii_write(gsw, gsw->ephy_base + 3, 4, 0x05e1);
 188
 189         /* global page 2 */
 190         _mt7620_mii_write(gsw, gsw->ephy_base + 1, 31, 0xa000);
 191         _mt7620_mii_write(gsw, gsw->ephy_base + 0, 16, 0x1111);
 192         _mt7620_mii_write(gsw, gsw->ephy_base + 1, 16, 0x1010);
 193         _mt7620_mii_write(gsw, gsw->ephy_base + 2, 16, 0x1515);
 194         _mt7620_mii_write(gsw, gsw->ephy_base + 3, 16, 0x0f0f);
 195
 196         /* CPU Port6 Force Link 1G, FC ON */
 197         mtk_switch_w32(gsw, 0x5e33b, GSW_REG_PORT_PMCR(6));
 198
 199         /* Set Port 6 as CPU Port */
 200         mtk_switch_w32(gsw, 0x7f7f7fe0, 0x0010);
 201
 202         /* setup port 4 */
 203         if (gsw->port4 == PORT4_EPHY) {
 204                 u32 val = rt_sysc_r32(SYSC_REG_CFG1);
 205
 206                 val |= 3 << 14;
 207                 rt_sysc_w32(val, SYSC_REG_CFG1);
 208                 _mt7620_mii_write(gsw, gsw->ephy_base + 4, 30, 0xa000);
 209                 _mt7620_mii_write(gsw, gsw->ephy_base + 4, 4, 0x05e1);
 210                 _mt7620_mii_write(gsw, gsw->ephy_base + 4, 16, 0x1313);
 211                 pr_info("gsw: setting port4 to ephy mode\n");
 212         } else if (!mdio_mode) {
 213                 u32 val = rt_sysc_r32(SYSC_REG_CFG1);
 214
 215                 val &= ~(3 << 14);
 216                 rt_sysc_w32(val, SYSC_REG_CFG1);
 217                 pr_info("gsw: setting port4 to gmac mode\n");
 218         }
 219 }
 220
 221 static const struct of_device_id mediatek_gsw_match[] = {
 222         { .compatible = "mediatek,mt7620-gsw" },
 223         {},
 224 };
 225 MODULE_DEVICE_TABLE(of, mediatek_gsw_match);
 226
 227 int mtk_gsw_init(struct fe_priv *priv)
 228 {
 229         struct device_node *np = priv->switch_np;
 230         struct platform_device *pdev = of_find_device_by_node(np);
 231         struct mt7620_gsw *gsw;
 232
 233         if (!pdev)
 234                 return -ENODEV;
 235
 236         if (!of_device_is_compatible(np, mediatek_gsw_match->compatible))
 237                 return -EINVAL;
 238
 239         gsw = platform_get_drvdata(pdev);
 240         priv->soc->swpriv = gsw;
 241
 242         mt7620_hw_init(gsw, mt7620_mdio_mode(priv->dev->of_node));
 243
 244         if (gsw->irq) {
 245                 request_irq(gsw->irq, gsw_interrupt_mt7620, 0,
 246                             "gsw", priv);
 247                 mtk_switch_w32(gsw, ~PORT_IRQ_ST_CHG, GSW_REG_IMR);
 248         }
 249
 250         return 0;
 251 }
 252
 253 static int mt7620_gsw_probe(struct platform_device *pdev)
 254 {
 255         struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 256         const char *port4 = NULL;
 257         struct mt7620_gsw *gsw;
 258         struct device_node *np = pdev->dev.of_node;
 259         u16 val;
 260
 261         gsw = devm_kzalloc(&pdev->dev, sizeof(struct mt7620_gsw), GFP_KERNEL);
 262         if (!gsw)
 263                 return -ENOMEM;
 264
 265         gsw->base = devm_ioremap_resource(&pdev->dev, res);
 266         if (IS_ERR(gsw->base))
 267                 return PTR_ERR(gsw->base);
 268
 269         gsw->dev = &pdev->dev;
 270
 271         of_property_read_string(np, "mediatek,port4", &port4);
 272         if (port4 && !strcmp(port4, "ephy"))
 273                 gsw->port4 = PORT4_EPHY;
 274         else if (port4 && !strcmp(port4, "gmac"))
 275                 gsw->port4 = PORT4_EXT;
 276         else
 277                 gsw->port4 = PORT4_EPHY;
 278
 279         if (of_property_read_u16(np, "mediatek,ephy-base-address", &val) == 0)
 280                 gsw->ephy_base = val;
 281         else
 282                 gsw->ephy_base = 0;
 283
 284         gsw->irq = platform_get_irq(pdev, 0);
 285
 286         platform_set_drvdata(pdev, gsw);
 287
 288         return 0;
 289 }
 290
 291 static int mt7620_gsw_remove(struct platform_device *pdev)
 292 {
 293         platform_set_drvdata(pdev, NULL);
 294
 295         return 0;
 296 }
 297
 298 static struct platform_driver gsw_driver = {
 299         .probe = mt7620_gsw_probe,
 300         .remove = mt7620_gsw_remove,
 301         .driver = {
 302                 .name = "mt7620-gsw",
 303                 .owner = THIS_MODULE,
 304                 .of_match_table = mediatek_gsw_match,
 305         },
 306 };
 307
 308 module_platform_driver(gsw_driver);
 309
 310 MODULE_LICENSE("GPL");
 311 MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
 312 MODULE_DESCRIPTION("GBit switch driver for Mediatek MT7620 SoC");
 313 MODULE_VERSION(MTK_FE_DRV_VERSION);