target/linux/ramips/files/drivers/net/ethernet/ralink/gsw_mt7620a.c

   1 /*
   2  *   This program is free software; you can redistribute it and/or modify
   3  *   it under the terms of the GNU General Public License as published by
   4  *   the Free Software Foundation; version 2 of the License
   5  *
   6  *   This program is distributed in the hope that it will be useful,
   7  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
   8  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   9  *   GNU General Public License for more details.
  10  *
  11  *   You should have received a copy of the GNU General Public License
  12  *   along with this program; if not, write to the Free Software
  13  *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
  14  *
  15  *   Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
  16  */
  17
  18 #include <linux/module.h>
  19 #include <linux/kernel.h>
  20 #include <linux/types.h>
  21 #include <linux/dma-mapping.h>
  22 #include <linux/init.h>
  23 #include <linux/skbuff.h>
  24 #include <linux/etherdevice.h>
  25 #include <linux/ethtool.h>
  26 #include <linux/platform_device.h>
  27 #include <linux/of_device.h>
  28 #include <linux/clk.h>
  29 #include <linux/of_net.h>
  30 #include <linux/of_mdio.h>
  31 #include <linux/of_irq.h>
  32 #include <linux/of_address.h>
  33 #include <linux/switch.h>
  34
  35 #include <asm/mach-ralink/ralink_regs.h>
  36
  37 #include "ralink_soc_eth.h"
  38
  39 #include <linux/ioport.h>
  40 #include <linux/switch.h>
  41 #include <linux/mii.h>
  42
  43 #include <ralink_regs.h>
  44 #include <asm/mach-ralink/mt7620.h>
  45
  46 #include "ralink_soc_eth.h"
  47 #include "gsw_mt7620a.h"
  48 #include "mt7530.h"
  49 #include "mdio.h"
  50
  51 #define GSW_REG_PHY_TIMEOUT     (5 * HZ)
  52
  53 #define MT7620A_GSW_REG_PIAC    0x7004
  54
  55 #define GSW_NUM_VLANS           16
  56 #define GSW_NUM_VIDS            4096
  57 #define GSW_NUM_PORTS           7
  58 #define GSW_PORT6               6
  59
  60 #define GSW_MDIO_ACCESS         BIT(31)
  61 #define GSW_MDIO_READ           BIT(19)
  62 #define GSW_MDIO_WRITE          BIT(18)
  63 #define GSW_MDIO_START          BIT(16)
  64 #define GSW_MDIO_ADDR_SHIFT     20
  65 #define GSW_MDIO_REG_SHIFT      25
  66
  67 #define GSW_REG_PORT_PMCR(x)    (0x3000 + (x * 0x100))
  68 #define GSW_REG_PORT_STATUS(x)  (0x3008 + (x * 0x100))
  69 #define GSW_REG_SMACCR0         0x3fE4
  70 #define GSW_REG_SMACCR1         0x3fE8
  71 #define GSW_REG_CKGCR           0x3ff0
  72
  73 #define GSW_REG_IMR             0x7008
  74 #define GSW_REG_ISR             0x700c
  75 #define GSW_REG_GPC1            0x7014
  76 #define GSW_PHY1_DISABLE        BIT(25)
  77
  78 #define SYSC_REG_CFG1           0x14
  79
  80 #define PORT_IRQ_ST_CHG         0x7f
  81
  82 #define SYSCFG1                 0x14
  83
  84 #define ESW_PHY_POLLING         0x7000
  85
  86 #define PMCR_IPG                BIT(18)
  87 #define PMCR_MAC_MODE           BIT(16)
  88 #define PMCR_FORCE              BIT(15)
  89 #define PMCR_TX_EN              BIT(14)
  90 #define PMCR_RX_EN              BIT(13)
  91 #define PMCR_BACKOFF            BIT(9)
  92 #define PMCR_BACKPRES           BIT(8)
  93 #define PMCR_RX_FC              BIT(5)
  94 #define PMCR_TX_FC              BIT(4)
  95 #define PMCR_SPEED(_x)          (_x << 2)
  96 #define PMCR_DUPLEX             BIT(1)
  97 #define PMCR_LINK               BIT(0)
  98
  99 #define PHY_AN_EN               BIT(31)
 100 #define PHY_PRE_EN              BIT(30)
 101 #define PMY_MDC_CONF(_x)        ((_x & 0x3f) << 24)
 102
 103 enum {
 104         /* Global attributes. */
 105         GSW_ATTR_ENABLE_VLAN,
 106         /* Port attributes. */
 107         GSW_ATTR_PORT_UNTAG,
 108 };
 109
 110 enum {
 111         PORT4_EPHY = 0,
 112         PORT4_EXT,
 113 };
 114
 115 struct mt7620_gsw {
 116         struct device           *dev;
 117         void __iomem            *base;
 118         int                     irq;
 119         int                     port4;
 120         long unsigned int       autopoll;
 121 };
 122
 123 static inline void gsw_w32(struct mt7620_gsw *gsw, u32 val, unsigned reg)
 124 {
 125         iowrite32(val, gsw->base + reg);
 126 }
 127
 128 static inline u32 gsw_r32(struct mt7620_gsw *gsw, unsigned reg)
 129 {
 130         return ioread32(gsw->base + reg);
 131 }
 132
 133 static int mt7620_mii_busy_wait(struct mt7620_gsw *gsw)
 134 {
 135         unsigned long t_start = jiffies;
 136
 137         while (1) {
 138                 if (!(gsw_r32(gsw, MT7620A_GSW_REG_PIAC) & GSW_MDIO_ACCESS))
 139                         return 0;
 140                 if (time_after(jiffies, t_start + GSW_REG_PHY_TIMEOUT)) {
 141                         break;
 142                 }
 143         }
 144
 145         printk(KERN_ERR "mdio: MDIO timeout\n");
 146         return -1;
 147 }
 148
 149 static u32 _mt7620_mii_write(struct mt7620_gsw *gsw, u32 phy_addr, u32 phy_register,
 150                                 u32 write_data)
 151 {
 152         if (mt7620_mii_busy_wait(gsw))
 153                 return -1;
 154
 155         write_data &= 0xffff;
 156
 157         gsw_w32(gsw, GSW_MDIO_ACCESS | GSW_MDIO_START | GSW_MDIO_WRITE |
 158                 (phy_register << GSW_MDIO_REG_SHIFT) |
 159                 (phy_addr << GSW_MDIO_ADDR_SHIFT) | write_data,
 160                 MT7620A_GSW_REG_PIAC);
 161
 162         if (mt7620_mii_busy_wait(gsw))
 163                 return -1;
 164
 165         return 0;
 166 }
 167
 168 static u32 _mt7620_mii_read(struct mt7620_gsw *gsw, int phy_addr, int phy_reg)
 169 {
 170         u32 d;
 171
 172         if (mt7620_mii_busy_wait(gsw))
 173                 return 0xffff;
 174
 175         gsw_w32(gsw, GSW_MDIO_ACCESS | GSW_MDIO_START | GSW_MDIO_READ |
 176                 (phy_reg << GSW_MDIO_REG_SHIFT) |
 177                 (phy_addr << GSW_MDIO_ADDR_SHIFT),
 178                 MT7620A_GSW_REG_PIAC);
 179
 180         if (mt7620_mii_busy_wait(gsw))
 181                 return 0xffff;
 182
 183         d = gsw_r32(gsw, MT7620A_GSW_REG_PIAC) & 0xffff;
 184
 185         return d;
 186 }
 187
 188 int mt7620_mdio_write(struct mii_bus *bus, int phy_addr, int phy_reg, u16 val)
 189 {
 190         struct fe_priv *priv = bus->priv;
 191         struct mt7620_gsw *gsw = (struct mt7620_gsw *) priv->soc->swpriv;
 192
 193         return _mt7620_mii_write(gsw, phy_addr, phy_reg, val);
 194 }
 195
 196 int mt7620_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg)
 197 {
 198         struct fe_priv *priv = bus->priv;
 199         struct mt7620_gsw *gsw = (struct mt7620_gsw *) priv->soc->swpriv;
 200
 201         return _mt7620_mii_read(gsw, phy_addr, phy_reg);
 202 }
 203
 204 static unsigned char *fe_speed_str(int speed)
 205 {
 206         switch (speed) {
 207         case 2:
 208         case SPEED_1000:
 209                 return "1000";
 210         case 1:
 211         case SPEED_100:
 212                 return "100";
 213         case 0:
 214         case SPEED_10:
 215                 return "10";
 216         }
 217
 218         return "? ";
 219 }
 220
 221 int mt7620a_has_carrier(struct fe_priv *priv)
 222 {
 223         struct mt7620_gsw *gsw = (struct mt7620_gsw *) priv->soc->swpriv;
 224         int i;
 225
 226         for (i = 0; i < GSW_PORT6; i++)
 227                 if (gsw_r32(gsw, GSW_REG_PORT_STATUS(i)) & 0x1)
 228                         return 1;
 229         return 0;
 230 }
 231
 232 static void mt7620a_handle_carrier(struct fe_priv *priv)
 233 {
 234         if (!priv->phy)
 235                 return;
 236
 237         if (mt7620a_has_carrier(priv))
 238                 netif_carrier_on(priv->netdev);
 239         else
 240                 netif_carrier_off(priv->netdev);
 241 }
 242
 243 void mt7620_mdio_link_adjust(struct fe_priv *priv, int port)
 244 {
 245         if (priv->link[port])
 246                 netdev_info(priv->netdev, "port %d link up (%sMbps/%s duplex)\n",
 247                         port, fe_speed_str(priv->phy->speed[port]),
 248                         (DUPLEX_FULL == priv->phy->duplex[port]) ? "Full" : "Half");
 249         else
 250                 netdev_info(priv->netdev, "port %d link down\n", port);
 251         mt7620a_handle_carrier(priv);
 252 }
 253
 254 static irqreturn_t gsw_interrupt(int irq, void *_priv)
 255 {
 256         struct fe_priv *priv = (struct fe_priv *) _priv;
 257         struct mt7620_gsw *gsw = (struct mt7620_gsw *) priv->soc->swpriv;
 258         u32 status;
 259         int i, max = (gsw->port4 == PORT4_EPHY) ? (4) : (3);
 260
 261         status = gsw_r32(gsw, GSW_REG_ISR);
 262         if (status & PORT_IRQ_ST_CHG)
 263                 for (i = 0; i <= max; i++) {
 264                         u32 status = gsw_r32(gsw, GSW_REG_PORT_STATUS(i));
 265                         int link = status & 0x1;
 266
 267                         if (link != priv->link[i]) {
 268                                 if (link)
 269                                         netdev_info(priv->netdev, "port %d link up (%sMbps/%s duplex)\n",
 270                                                         i, fe_speed_str((status >> 2) & 3),
 271                                                         (status & 0x2) ? "Full" : "Half");
 272                                 else
 273                                         netdev_info(priv->netdev, "port %d link down\n", i);
 274                         }
 275
 276                         priv->link[i] = link;
 277                 }
 278         mt7620a_handle_carrier(priv);
 279
 280         gsw_w32(gsw, status, GSW_REG_ISR);
 281
 282         return IRQ_HANDLED;
 283 }
 284
 285 static int mt7620_is_bga(void)
 286 {
 287         u32 bga = rt_sysc_r32(0x0c);
 288
 289         return (bga >> 16) & 1;
 290 }
 291
 292 static void gsw_auto_poll(struct mt7620_gsw *gsw)
 293 {
 294         int phy;
 295         int lsb = -1, msb = 0;
 296
 297         for_each_set_bit(phy, &gsw->autopoll, 32) {
 298                 if (lsb < 0)
 299                         lsb = phy;
 300                 msb = phy;
 301         }
 302
 303         gsw_w32(gsw, PHY_AN_EN | PHY_PRE_EN | PMY_MDC_CONF(5) | (msb << 8) | lsb, ESW_PHY_POLLING);
 304 }
 305
 306 void mt7620_port_init(struct fe_priv *priv, struct device_node *np)
 307 {
 308         struct mt7620_gsw *gsw = (struct mt7620_gsw *) priv->soc->swpriv;
 309         const __be32 *_id = of_get_property(np, "reg", NULL);
 310         int phy_mode, size, id;
 311         int shift = 12;
 312         u32 val, mask = 0;
 313         int min = (gsw->port4 == PORT4_EPHY) ? (5) : (4);
 314
 315         if (!_id || (be32_to_cpu(*_id) < min) || (be32_to_cpu(*_id) > 5)) {
 316                 if (_id)
 317                         pr_err("%s: invalid port id %d\n", np->name, be32_to_cpu(*_id));
 318                 else
 319                         pr_err("%s: invalid port id\n", np->name);
 320                 return;
 321         }
 322
 323         id = be32_to_cpu(*_id);
 324
 325         if (id == 4)
 326                 shift = 14;
 327
 328         priv->phy->phy_fixed[id] = of_get_property(np, "ralink,fixed-link", &size);
 329         if (priv->phy->phy_fixed[id] && (size != (4 * sizeof(*priv->phy->phy_fixed[id])))) {
 330                 pr_err("%s: invalid fixed link property\n", np->name);
 331                 priv->phy->phy_fixed[id] = NULL;
 332                 return;
 333         }
 334
 335         phy_mode = of_get_phy_mode(np);
 336         switch (phy_mode) {
 337         case PHY_INTERFACE_MODE_RGMII:
 338                 mask = 0;
 339                 break;
 340         case PHY_INTERFACE_MODE_MII:
 341                 mask = 1;
 342                 break;
 343         case PHY_INTERFACE_MODE_RMII:
 344                 mask = 2;
 345                 break;
 346         default:
 347                 dev_err(priv->device, "port %d - invalid phy mode\n", id);
 348                 return;
 349         }
 350
 351         priv->phy->phy_node[id] = of_parse_phandle(np, "phy-handle", 0);
 352         if (!priv->phy->phy_node[id] && !priv->phy->phy_fixed[id])
 353                 return;
 354
 355         val = rt_sysc_r32(SYSCFG1);
 356         val &= ~(3 << shift);
 357         val |= mask << shift;
 358         rt_sysc_w32(val, SYSCFG1);
 359
 360         if (priv->phy->phy_fixed[id]) {
 361                 const __be32 *link = priv->phy->phy_fixed[id];
 362                 int tx_fc, rx_fc;
 363                 u32 val = 0;
 364
 365                 priv->phy->speed[id] = be32_to_cpup(link++);
 366                 tx_fc = be32_to_cpup(link++);
 367                 rx_fc = be32_to_cpup(link++);
 368                 priv->phy->duplex[id] = be32_to_cpup(link++);
 369                 priv->link[id] = 1;
 370
 371                 switch (priv->phy->speed[id]) {
 372                 case SPEED_10:
 373                         val = 0;
 374                         break;
 375                 case SPEED_100:
 376                         val = 1;
 377                         break;
 378                 case SPEED_1000:
 379                         val = 2;
 380                         break;
 381                 default:
 382                         dev_err(priv->device, "invalid link speed: %d\n", priv->phy->speed[id]);
 383                         priv->phy->phy_fixed[id] = 0;
 384                         return;
 385                 }
 386                 val = PMCR_SPEED(val);
 387                 val |= PMCR_LINK | PMCR_BACKPRES | PMCR_BACKOFF | PMCR_RX_EN |
 388                         PMCR_TX_EN | PMCR_FORCE | PMCR_MAC_MODE | PMCR_IPG;
 389                 if (tx_fc)
 390                         val |= PMCR_TX_FC;
 391                 if (rx_fc)
 392                         val |= PMCR_RX_FC;
 393                 if (priv->phy->duplex[id])
 394                         val |= PMCR_DUPLEX;
 395                 gsw_w32(gsw, val, GSW_REG_PORT_PMCR(id));
 396                 dev_info(priv->device, "using fixed link parameters\n");
 397                 return;
 398         }
 399
 400         if (priv->phy->phy_node[id] && priv->mii_bus->phy_map[id]) {
 401                 u32 val = PMCR_BACKPRES | PMCR_BACKOFF | PMCR_RX_EN |
 402                         PMCR_TX_EN |  PMCR_MAC_MODE | PMCR_IPG;
 403
 404                 gsw_w32(gsw, val, GSW_REG_PORT_PMCR(id));
 405                 fe_connect_phy_node(priv, priv->phy->phy_node[id]);
 406                 gsw->autopoll |= BIT(id);
 407                 gsw_auto_poll(gsw);
 408                 return;
 409         }
 410 }
 411
 412 static void gsw_hw_init(struct mt7620_gsw *gsw)
 413 {
 414         u32 is_BGA = mt7620_is_bga();
 415
 416         rt_sysc_w32(rt_sysc_r32(SYSC_REG_CFG1) | BIT(8), SYSC_REG_CFG1);
 417         gsw_w32(gsw, gsw_r32(gsw, GSW_REG_CKGCR) & ~(0x3 << 4), GSW_REG_CKGCR);
 418
 419         /* EPHY1 fixup - only run if the ephy is enabled */
 420         if (gsw_r32(gsw, GSW_REG_GPC1) & GSW_PHY1_DISABLE == GSW_PHY1_DISABLE) {
 421                 /*correct  PHY  setting L3.0 BGA*/
 422                 _mt7620_mii_write(gsw, 1, 31, 0x4000); //global, page 4
 423
 424                 _mt7620_mii_write(gsw, 1, 17, 0x7444);
 425                 if (is_BGA)
 426                         _mt7620_mii_write(gsw, 1, 19, 0x0114);
 427                 else
 428                         _mt7620_mii_write(gsw, 1, 19, 0x0117);
 429
 430                 _mt7620_mii_write(gsw, 1, 22, 0x10cf);
 431                 _mt7620_mii_write(gsw, 1, 25, 0x6212);
 432                 _mt7620_mii_write(gsw, 1, 26, 0x0777);
 433                 _mt7620_mii_write(gsw, 1, 29, 0x4000);
 434                 _mt7620_mii_write(gsw, 1, 28, 0xc077);
 435                 _mt7620_mii_write(gsw, 1, 24, 0x0000);
 436
 437                 _mt7620_mii_write(gsw, 1, 31, 0x3000); //global, page 3
 438                 _mt7620_mii_write(gsw, 1, 17, 0x4838);
 439
 440                 _mt7620_mii_write(gsw, 1, 31, 0x2000); //global, page 2
 441                 if (is_BGA) {
 442                         _mt7620_mii_write(gsw, 1, 21, 0x0515);
 443                         _mt7620_mii_write(gsw, 1, 22, 0x0053);
 444                         _mt7620_mii_write(gsw, 1, 23, 0x00bf);
 445                         _mt7620_mii_write(gsw, 1, 24, 0x0aaf);
 446                         _mt7620_mii_write(gsw, 1, 25, 0x0fad);
 447                         _mt7620_mii_write(gsw, 1, 26, 0x0fc1);
 448                 } else {
 449                         _mt7620_mii_write(gsw, 1, 21, 0x0517);
 450                         _mt7620_mii_write(gsw, 1, 22, 0x0fd2);
 451                         _mt7620_mii_write(gsw, 1, 23, 0x00bf);
 452                         _mt7620_mii_write(gsw, 1, 24, 0x0aab);
 453                         _mt7620_mii_write(gsw, 1, 25, 0x00ae);
 454                         _mt7620_mii_write(gsw, 1, 26, 0x0fff);
 455                 }
 456                 _mt7620_mii_write(gsw, 1, 31, 0x1000); //global, page 1
 457                 _mt7620_mii_write(gsw, 1, 17, 0xe7f8);
 458         }
 459
 460         _mt7620_mii_write(gsw, 1, 31, 0x8000); //local, page 0
 461         _mt7620_mii_write(gsw, 0, 30, 0xa000);
 462         _mt7620_mii_write(gsw, 1, 30, 0xa000);
 463         _mt7620_mii_write(gsw, 2, 30, 0xa000);
 464         _mt7620_mii_write(gsw, 3, 30, 0xa000);
 465
 466         _mt7620_mii_write(gsw, 0, 4, 0x05e1);
 467         _mt7620_mii_write(gsw, 1, 4, 0x05e1);
 468         _mt7620_mii_write(gsw, 2, 4, 0x05e1);
 469         _mt7620_mii_write(gsw, 3, 4, 0x05e1);
 470
 471         _mt7620_mii_write(gsw, 1, 31, 0xa000); //local, page 2
 472         _mt7620_mii_write(gsw, 0, 16, 0x1111);
 473         _mt7620_mii_write(gsw, 1, 16, 0x1010);
 474         _mt7620_mii_write(gsw, 2, 16, 0x1515);
 475         _mt7620_mii_write(gsw, 3, 16, 0x0f0f);
 476
 477         /* CPU Port6 Force Link 1G, FC ON */
 478         gsw_w32(gsw, 0x5e33b, GSW_REG_PORT_PMCR(6));
 479         /* Set Port6 CPU Port */
 480         gsw_w32(gsw, 0x7f7f7fe0, 0x0010);
 481
 482         /* setup port 4 */
 483         if (gsw->port4 == PORT4_EPHY) {
 484                 u32 val = rt_sysc_r32(SYSCFG1);
 485                 val |= 3 << 14;
 486                 rt_sysc_w32(val, SYSCFG1);
 487                 _mt7620_mii_write(gsw, 4, 30, 0xa000);
 488                 _mt7620_mii_write(gsw, 4, 4, 0x05e1);
 489                 _mt7620_mii_write(gsw, 4, 16, 0x1313);
 490                 pr_info("gsw: setting port4 to ephy mode\n");
 491         }
 492 }
 493
 494 void mt7620_set_mac(struct fe_priv *priv, unsigned char *mac)
 495 {
 496         struct mt7620_gsw *gsw = (struct mt7620_gsw *) priv->soc->swpriv;
 497         unsigned long flags;
 498
 499         spin_lock_irqsave(&priv->page_lock, flags);
 500         gsw_w32(gsw, (mac[0] << 8) | mac[1], GSW_REG_SMACCR1);
 501         gsw_w32(gsw, (mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5],
 502                 GSW_REG_SMACCR0);
 503         spin_unlock_irqrestore(&priv->page_lock, flags);
 504 }
 505
 506 static struct of_device_id gsw_match[] = {
 507         { .compatible = "ralink,mt7620a-gsw" },
 508         {}
 509 };
 510
 511 int mt7620_gsw_config(struct fe_priv *priv)
 512 {
 513         struct mt7620_gsw *gsw = (struct mt7620_gsw *) priv->soc->swpriv;
 514
 515         /* is the mt7530 internal or external */
 516         if (priv->mii_bus && priv->mii_bus->phy_map[0x1f]) {
 517                 mt7530_probe(priv->device, gsw->base, NULL, 0);
 518                 mt7530_probe(priv->device, NULL, priv->mii_bus, 1);
 519         } else {
 520                 mt7530_probe(priv->device, gsw->base, NULL, 1);
 521         }
 522
 523         return 0;
 524 }
 525
 526 int mt7620_gsw_probe(struct fe_priv *priv)
 527 {
 528         struct mt7620_gsw *gsw;
 529         struct device_node *np;
 530         const char *port4 = NULL;
 531
 532         np = of_find_matching_node(NULL, gsw_match);
 533         if (!np) {
 534                 dev_err(priv->device, "no gsw node found\n");
 535                 return -EINVAL;
 536         }
 537         np = of_node_get(np);
 538
 539         gsw = devm_kzalloc(priv->device, sizeof(struct mt7620_gsw), GFP_KERNEL);
 540         if (!gsw) {
 541                 dev_err(priv->device, "no gsw memory for private data\n");
 542                 return -ENOMEM;
 543         }
 544
 545         gsw->irq = irq_of_parse_and_map(np, 0);
 546         if (!gsw->irq) {
 547                 dev_err(priv->device, "no gsw irq resource found\n");
 548                 return -ENOMEM;
 549         }
 550
 551         gsw->base = of_iomap(np, 0);
 552         if (!gsw->base) {
 553                 dev_err(priv->device, "gsw ioremap failed\n");
 554                 return -ENOMEM;
 555         }
 556
 557         gsw->dev = priv->device;
 558         priv->soc->swpriv = gsw;
 559
 560         of_property_read_string(np, "ralink,port4", &port4);
 561         if (port4 && !strcmp(port4, "ephy"))
 562                 gsw->port4 = PORT4_EPHY;
 563         else if (port4 && !strcmp(port4, "gmac"))
 564                 gsw->port4 = PORT4_EXT;
 565         else
 566                 WARN_ON(port4);
 567
 568         gsw_hw_init(gsw);
 569
 570         gsw_w32(gsw, ~PORT_IRQ_ST_CHG, GSW_REG_IMR);
 571         request_irq(gsw->irq, gsw_interrupt, 0, "gsw", priv);
 572
 573         return 0;
 574 }