target/linux/ramips/files/drivers/net/ethernet/ralink/gsw_mt7620a.c

   1 /*
   2  *   This program is free software; you can redistribute it and/or modify
   3  *   it under the terms of the GNU General Public License as published by
   4  *   the Free Software Foundation; version 2 of the License
   5  *
   6  *   This program is distributed in the hope that it will be useful,
   7  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
   8  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   9  *   GNU General Public License for more details.
  10  *
  11  *   You should have received a copy of the GNU General Public License
  12  *   along with this program; if not, write to the Free Software
  13  *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
  14  *
  15  *   Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
  16  */
  17
  18 #include <linux/module.h>
  19 #include <linux/kernel.h>
  20 #include <linux/types.h>
  21 #include <linux/dma-mapping.h>
  22 #include <linux/init.h>
  23 #include <linux/skbuff.h>
  24 #include <linux/etherdevice.h>
  25 #include <linux/ethtool.h>
  26 #include <linux/platform_device.h>
  27 #include <linux/of_device.h>
  28 #include <linux/clk.h>
  29 #include <linux/of_net.h>
  30 #include <linux/of_mdio.h>
  31 #include <linux/of_irq.h>
  32 #include <linux/of_address.h>
  33 #include <linux/switch.h>
  34
  35 #include <asm/mach-ralink/ralink_regs.h>
  36
  37 #include "ralink_soc_eth.h"
  38
  39 #include <linux/ioport.h>
  40 #include <linux/switch.h>
  41 #include <linux/mii.h>
  42
  43 #include <ralink_regs.h>
  44 #include <asm/mach-ralink/mt7620.h>
  45
  46 #include "ralink_soc_eth.h"
  47 #include "gsw_mt7620a.h"
  48 #include "mt7530.h"
  49 #include "mdio.h"
  50
  51 #define GSW_REG_PHY_TIMEOUT     (5 * HZ)
  52
  53 #define MT7620A_GSW_REG_PIAC    0x7004
  54
  55 #define GSW_NUM_VLANS           16
  56 #define GSW_NUM_VIDS            4096
  57 #define GSW_NUM_PORTS           7
  58 #define GSW_PORT6               6
  59
  60 #define GSW_MDIO_ACCESS         BIT(31)
  61 #define GSW_MDIO_READ           BIT(19)
  62 #define GSW_MDIO_WRITE          BIT(18)
  63 #define GSW_MDIO_START          BIT(16)
  64 #define GSW_MDIO_ADDR_SHIFT     20
  65 #define GSW_MDIO_REG_SHIFT      25
  66
  67 #define GSW_REG_PORT_PMCR(x)    (0x3000 + (x * 0x100))
  68 #define GSW_REG_PORT_STATUS(x)  (0x3008 + (x * 0x100))
  69 #define GSW_REG_SMACCR0         0x3fE4
  70 #define GSW_REG_SMACCR1         0x3fE8
  71 #define GSW_REG_CKGCR           0x3ff0
  72
  73 #define GSW_REG_IMR             0x7008
  74 #define GSW_REG_ISR             0x700c
  75 #define GSW_REG_GPC1            0x7014
  76
  77 #define SYSC_REG_CFG1           0x14
  78
  79 #define PORT_IRQ_ST_CHG         0x7f
  80
  81 #define SYSCFG1                 0x14
  82
  83 #define ESW_PHY_POLLING         0x7000
  84
  85 #define PMCR_IPG                BIT(18)
  86 #define PMCR_MAC_MODE           BIT(16)
  87 #define PMCR_FORCE              BIT(15)
  88 #define PMCR_TX_EN              BIT(14)
  89 #define PMCR_RX_EN              BIT(13)
  90 #define PMCR_BACKOFF            BIT(9)
  91 #define PMCR_BACKPRES           BIT(8)
  92 #define PMCR_RX_FC              BIT(5)
  93 #define PMCR_TX_FC              BIT(4)
  94 #define PMCR_SPEED(_x)          (_x << 2)
  95 #define PMCR_DUPLEX             BIT(1)
  96 #define PMCR_LINK               BIT(0)
  97
  98 #define PHY_AN_EN               BIT(31)
  99 #define PHY_PRE_EN              BIT(30)
 100 #define PMY_MDC_CONF(_x)        ((_x & 0x3f) << 24)
 101
 102 enum {
 103         /* Global attributes. */
 104         GSW_ATTR_ENABLE_VLAN,
 105         /* Port attributes. */
 106         GSW_ATTR_PORT_UNTAG,
 107 };
 108
 109 enum {
 110         PORT4_EPHY = 0,
 111         PORT4_EXT,
 112 };
 113
 114 struct mt7620_gsw {
 115         struct device           *dev;
 116         void __iomem            *base;
 117         int                     irq;
 118         int                     port4;
 119         long unsigned int       autopoll;
 120 };
 121
 122 static inline void gsw_w32(struct mt7620_gsw *gsw, u32 val, unsigned reg)
 123 {
 124         iowrite32(val, gsw->base + reg);
 125 }
 126
 127 static inline u32 gsw_r32(struct mt7620_gsw *gsw, unsigned reg)
 128 {
 129         return ioread32(gsw->base + reg);
 130 }
 131
 132 static int mt7620_mii_busy_wait(struct mt7620_gsw *gsw)
 133 {
 134         unsigned long t_start = jiffies;
 135
 136         while (1) {
 137                 if (!(gsw_r32(gsw, MT7620A_GSW_REG_PIAC) & GSW_MDIO_ACCESS))
 138                         return 0;
 139                 if (time_after(jiffies, t_start + GSW_REG_PHY_TIMEOUT)) {
 140                         break;
 141                 }
 142         }
 143
 144         printk(KERN_ERR "mdio: MDIO timeout\n");
 145         return -1;
 146 }
 147
 148 static u32 _mt7620_mii_write(struct mt7620_gsw *gsw, u32 phy_addr, u32 phy_register,
 149                                 u32 write_data)
 150 {
 151         if (mt7620_mii_busy_wait(gsw))
 152                 return -1;
 153
 154         write_data &= 0xffff;
 155
 156         gsw_w32(gsw, GSW_MDIO_ACCESS | GSW_MDIO_START | GSW_MDIO_WRITE |
 157                 (phy_register << GSW_MDIO_REG_SHIFT) |
 158                 (phy_addr << GSW_MDIO_ADDR_SHIFT) | write_data,
 159                 MT7620A_GSW_REG_PIAC);
 160
 161         if (mt7620_mii_busy_wait(gsw))
 162                 return -1;
 163
 164         return 0;
 165 }
 166
 167 static u32 _mt7620_mii_read(struct mt7620_gsw *gsw, int phy_addr, int phy_reg)
 168 {
 169         u32 d;
 170
 171         if (mt7620_mii_busy_wait(gsw))
 172                 return 0xffff;
 173
 174         gsw_w32(gsw, GSW_MDIO_ACCESS | GSW_MDIO_START | GSW_MDIO_READ |
 175                 (phy_reg << GSW_MDIO_REG_SHIFT) |
 176                 (phy_addr << GSW_MDIO_ADDR_SHIFT),
 177                 MT7620A_GSW_REG_PIAC);
 178
 179         if (mt7620_mii_busy_wait(gsw))
 180                 return 0xffff;
 181
 182         d = gsw_r32(gsw, MT7620A_GSW_REG_PIAC) & 0xffff;
 183
 184         return d;
 185 }
 186
 187 int mt7620_mdio_write(struct mii_bus *bus, int phy_addr, int phy_reg, u16 val)
 188 {
 189         struct fe_priv *priv = bus->priv;
 190         struct mt7620_gsw *gsw = (struct mt7620_gsw *) priv->soc->swpriv;
 191
 192         return _mt7620_mii_write(gsw, phy_addr, phy_reg, val);
 193 }
 194
 195 int mt7620_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg)
 196 {
 197         struct fe_priv *priv = bus->priv;
 198         struct mt7620_gsw *gsw = (struct mt7620_gsw *) priv->soc->swpriv;
 199
 200         return _mt7620_mii_read(gsw, phy_addr, phy_reg);
 201 }
 202
 203 static unsigned char *fe_speed_str(int speed)
 204 {
 205         switch (speed) {
 206         case 2:
 207         case SPEED_1000:
 208                 return "1000";
 209         case 1:
 210         case SPEED_100:
 211                 return "100";
 212         case 0:
 213         case SPEED_10:
 214                 return "10";
 215         }
 216
 217         return "? ";
 218 }
 219
 220 int mt7620a_has_carrier(struct fe_priv *priv)
 221 {
 222         struct mt7620_gsw *gsw = (struct mt7620_gsw *) priv->soc->swpriv;
 223         int i;
 224
 225         for (i = 0; i < GSW_PORT6; i++)
 226                 if (gsw_r32(gsw, GSW_REG_PORT_STATUS(i)) & 0x1)
 227                         return 1;
 228         return 0;
 229 }
 230
 231 static void mt7620a_handle_carrier(struct fe_priv *priv)
 232 {
 233         if (!priv->phy)
 234                 return;
 235
 236         if (mt7620a_has_carrier(priv))
 237                 netif_carrier_on(priv->netdev);
 238         else
 239                 netif_carrier_off(priv->netdev);
 240 }
 241
 242 void mt7620_mdio_link_adjust(struct fe_priv *priv, int port)
 243 {
 244         if (priv->link[port])
 245                 netdev_info(priv->netdev, "port %d link up (%sMbps/%s duplex)\n",
 246                         port, fe_speed_str(priv->phy->speed[port]),
 247                         (DUPLEX_FULL == priv->phy->duplex[port]) ? "Full" : "Half");
 248         else
 249                 netdev_info(priv->netdev, "port %d link down\n", port);
 250         mt7620a_handle_carrier(priv);
 251 }
 252
 253 static irqreturn_t gsw_interrupt(int irq, void *_priv)
 254 {
 255         struct fe_priv *priv = (struct fe_priv *) _priv;
 256         struct mt7620_gsw *gsw = (struct mt7620_gsw *) priv->soc->swpriv;
 257         u32 status;
 258         int i, max = (gsw->port4 == PORT4_EPHY) ? (4) : (3);
 259
 260         status = gsw_r32(gsw, GSW_REG_ISR);
 261         if (status & PORT_IRQ_ST_CHG)
 262                 for (i = 0; i <= max; i++) {
 263                         u32 status = gsw_r32(gsw, GSW_REG_PORT_STATUS(i));
 264                         int link = status & 0x1;
 265
 266                         if (link != priv->link[i]) {
 267                                 if (link)
 268                                         netdev_info(priv->netdev, "port %d link up (%sMbps/%s duplex)\n",
 269                                                         i, fe_speed_str((status >> 2) & 3),
 270                                                         (status & 0x2) ? "Full" : "Half");
 271                                 else
 272                                         netdev_info(priv->netdev, "port %d link down\n", i);
 273                         }
 274
 275                         priv->link[i] = link;
 276                 }
 277         mt7620a_handle_carrier(priv);
 278
 279         gsw_w32(gsw, status, GSW_REG_ISR);
 280
 281         return IRQ_HANDLED;
 282 }
 283
 284 static int mt7620_is_bga(void)
 285 {
 286         u32 bga = rt_sysc_r32(0x0c);
 287
 288         return (bga >> 16) & 1;
 289 }
 290
 291 static void gsw_auto_poll(struct mt7620_gsw *gsw)
 292 {
 293         int phy;
 294         int lsb = -1, msb = 0;
 295
 296         for_each_set_bit(phy, &gsw->autopoll, 32) {
 297                 if (lsb < 0)
 298                         lsb = phy;
 299                 msb = phy;
 300         }
 301
 302         gsw_w32(gsw, PHY_AN_EN | PHY_PRE_EN | PMY_MDC_CONF(5) | (msb << 8) | lsb, ESW_PHY_POLLING);
 303 }
 304
 305 void mt7620_port_init(struct fe_priv *priv, struct device_node *np)
 306 {
 307         struct mt7620_gsw *gsw = (struct mt7620_gsw *) priv->soc->swpriv;
 308         const __be32 *_id = of_get_property(np, "reg", NULL);
 309         int phy_mode, size, id;
 310         int shift = 12;
 311         u32 val, mask = 0;
 312         int min = (gsw->port4 == PORT4_EPHY) ? (5) : (4);
 313
 314         if (!_id || (be32_to_cpu(*_id) < min) || (be32_to_cpu(*_id) > 5)) {
 315                 if (_id)
 316                         pr_err("%s: invalid port id %d\n", np->name, be32_to_cpu(*_id));
 317                 else
 318                         pr_err("%s: invalid port id\n", np->name);
 319                 return;
 320         }
 321
 322         id = be32_to_cpu(*_id);
 323
 324         if (id == 4)
 325                 shift = 14;
 326
 327         priv->phy->phy_fixed[id] = of_get_property(np, "ralink,fixed-link", &size);
 328         if (priv->phy->phy_fixed[id] && (size != (4 * sizeof(*priv->phy->phy_fixed[id])))) {
 329                 pr_err("%s: invalid fixed link property\n", np->name);
 330                 priv->phy->phy_fixed[id] = NULL;
 331                 return;
 332         }
 333
 334         phy_mode = of_get_phy_mode(np);
 335         switch (phy_mode) {
 336         case PHY_INTERFACE_MODE_RGMII:
 337                 mask = 0;
 338                 break;
 339         case PHY_INTERFACE_MODE_MII:
 340                 mask = 1;
 341                 break;
 342         case PHY_INTERFACE_MODE_RMII:
 343                 mask = 2;
 344                 break;
 345         default:
 346                 dev_err(priv->device, "port %d - invalid phy mode\n", id);
 347                 return;
 348         }
 349
 350         priv->phy->phy_node[id] = of_parse_phandle(np, "phy-handle", 0);
 351         if (!priv->phy->phy_node[id] && !priv->phy->phy_fixed[id])
 352                 return;
 353
 354         val = rt_sysc_r32(SYSCFG1);
 355         val &= ~(3 << shift);
 356         val |= mask << shift;
 357         rt_sysc_w32(val, SYSCFG1);
 358
 359         if (priv->phy->phy_fixed[id]) {
 360                 const __be32 *link = priv->phy->phy_fixed[id];
 361                 int tx_fc, rx_fc;
 362                 u32 val = 0;
 363
 364                 priv->phy->speed[id] = be32_to_cpup(link++);
 365                 tx_fc = be32_to_cpup(link++);
 366                 rx_fc = be32_to_cpup(link++);
 367                 priv->phy->duplex[id] = be32_to_cpup(link++);
 368                 priv->link[id] = 1;
 369
 370                 switch (priv->phy->speed[id]) {
 371                 case SPEED_10:
 372                         val = 0;
 373                         break;
 374                 case SPEED_100:
 375                         val = 1;
 376                         break;
 377                 case SPEED_1000:
 378                         val = 2;
 379                         break;
 380                 default:
 381                         dev_err(priv->device, "invalid link speed: %d\n", priv->phy->speed[id]);
 382                         priv->phy->phy_fixed[id] = 0;
 383                         return;
 384                 }
 385                 val = PMCR_SPEED(val);
 386                 val |= PMCR_LINK | PMCR_BACKPRES | PMCR_BACKOFF | PMCR_RX_EN |
 387                         PMCR_TX_EN | PMCR_FORCE | PMCR_MAC_MODE | PMCR_IPG;
 388                 if (tx_fc)
 389                         val |= PMCR_TX_FC;
 390                 if (rx_fc)
 391                         val |= PMCR_RX_FC;
 392                 if (priv->phy->duplex[id])
 393                         val |= PMCR_DUPLEX;
 394                 gsw_w32(gsw, val, GSW_REG_PORT_PMCR(id));
 395                 dev_info(priv->device, "using fixed link parameters\n");
 396                 return;
 397         }
 398
 399         if (priv->phy->phy_node[id] && priv->mii_bus->phy_map[id]) {
 400                 u32 val = PMCR_BACKPRES | PMCR_BACKOFF | PMCR_RX_EN |
 401                         PMCR_TX_EN |  PMCR_MAC_MODE | PMCR_IPG;
 402
 403                 gsw_w32(gsw, val, GSW_REG_PORT_PMCR(id));
 404                 fe_connect_phy_node(priv, priv->phy->phy_node[id]);
 405                 gsw->autopoll |= BIT(id);
 406                 gsw_auto_poll(gsw);
 407                 return;
 408         }
 409 }
 410
 411 static void gsw_hw_init(struct mt7620_gsw *gsw, struct device_node *np)
 412 {
 413         u32 is_BGA = mt7620_is_bga();
 414
 415         rt_sysc_w32(rt_sysc_r32(SYSC_REG_CFG1) | BIT(8), SYSC_REG_CFG1);
 416         gsw_w32(gsw, gsw_r32(gsw, GSW_REG_CKGCR) & ~(0x3 << 4), GSW_REG_CKGCR);
 417
 418         if (of_property_read_bool(np, "mediatek,mt7530")) {
 419                 gsw_w32(gsw, gsw_r32(gsw, GSW_REG_GPC1) | (0x1f << 24), GSW_REG_GPC1);
 420                 pr_info("gsw: truning EPHY off\n");
 421         } else {
 422                 /* EPHY1 fixup - only run if the ephy is enabled */
 423
 424                 /*correct  PHY  setting L3.0 BGA*/
 425                 _mt7620_mii_write(gsw, 1, 31, 0x4000); //global, page 4
 426
 427                 _mt7620_mii_write(gsw, 1, 17, 0x7444);
 428                 if (is_BGA)
 429                         _mt7620_mii_write(gsw, 1, 19, 0x0114);
 430                 else
 431                         _mt7620_mii_write(gsw, 1, 19, 0x0117);
 432
 433                 _mt7620_mii_write(gsw, 1, 22, 0x10cf);
 434                 _mt7620_mii_write(gsw, 1, 25, 0x6212);
 435                 _mt7620_mii_write(gsw, 1, 26, 0x0777);
 436                 _mt7620_mii_write(gsw, 1, 29, 0x4000);
 437                 _mt7620_mii_write(gsw, 1, 28, 0xc077);
 438                 _mt7620_mii_write(gsw, 1, 24, 0x0000);
 439
 440                 _mt7620_mii_write(gsw, 1, 31, 0x3000); //global, page 3
 441                 _mt7620_mii_write(gsw, 1, 17, 0x4838);
 442
 443                 _mt7620_mii_write(gsw, 1, 31, 0x2000); //global, page 2
 444                 if (is_BGA) {
 445                         _mt7620_mii_write(gsw, 1, 21, 0x0515);
 446                         _mt7620_mii_write(gsw, 1, 22, 0x0053);
 447                         _mt7620_mii_write(gsw, 1, 23, 0x00bf);
 448                         _mt7620_mii_write(gsw, 1, 24, 0x0aaf);
 449                         _mt7620_mii_write(gsw, 1, 25, 0x0fad);
 450                         _mt7620_mii_write(gsw, 1, 26, 0x0fc1);
 451                 } else {
 452                         _mt7620_mii_write(gsw, 1, 21, 0x0517);
 453                         _mt7620_mii_write(gsw, 1, 22, 0x0fd2);
 454                         _mt7620_mii_write(gsw, 1, 23, 0x00bf);
 455                         _mt7620_mii_write(gsw, 1, 24, 0x0aab);
 456                         _mt7620_mii_write(gsw, 1, 25, 0x00ae);
 457                         _mt7620_mii_write(gsw, 1, 26, 0x0fff);
 458                 }
 459                 _mt7620_mii_write(gsw, 1, 31, 0x1000); //global, page 1
 460                 _mt7620_mii_write(gsw, 1, 17, 0xe7f8);
 461         }
 462
 463         _mt7620_mii_write(gsw, 1, 31, 0x8000); //local, page 0
 464         _mt7620_mii_write(gsw, 0, 30, 0xa000);
 465         _mt7620_mii_write(gsw, 1, 30, 0xa000);
 466         _mt7620_mii_write(gsw, 2, 30, 0xa000);
 467         _mt7620_mii_write(gsw, 3, 30, 0xa000);
 468
 469         _mt7620_mii_write(gsw, 0, 4, 0x05e1);
 470         _mt7620_mii_write(gsw, 1, 4, 0x05e1);
 471         _mt7620_mii_write(gsw, 2, 4, 0x05e1);
 472         _mt7620_mii_write(gsw, 3, 4, 0x05e1);
 473
 474         _mt7620_mii_write(gsw, 1, 31, 0xa000); //local, page 2
 475         _mt7620_mii_write(gsw, 0, 16, 0x1111);
 476         _mt7620_mii_write(gsw, 1, 16, 0x1010);
 477         _mt7620_mii_write(gsw, 2, 16, 0x1515);
 478         _mt7620_mii_write(gsw, 3, 16, 0x0f0f);
 479
 480         /* CPU Port6 Force Link 1G, FC ON */
 481         gsw_w32(gsw, 0x5e33b, GSW_REG_PORT_PMCR(6));
 482         /* Set Port6 CPU Port */
 483         gsw_w32(gsw, 0x7f7f7fe0, 0x0010);
 484
 485         /* setup port 4 */
 486         if (gsw->port4 == PORT4_EPHY) {
 487                 u32 val = rt_sysc_r32(SYSCFG1);
 488                 val |= 3 << 14;
 489                 rt_sysc_w32(val, SYSCFG1);
 490                 _mt7620_mii_write(gsw, 4, 30, 0xa000);
 491                 _mt7620_mii_write(gsw, 4, 4, 0x05e1);
 492                 _mt7620_mii_write(gsw, 4, 16, 0x1313);
 493                 pr_info("gsw: setting port4 to ephy mode\n");
 494         }
 495 }
 496
 497 void mt7620_set_mac(struct fe_priv *priv, unsigned char *mac)
 498 {
 499         struct mt7620_gsw *gsw = (struct mt7620_gsw *) priv->soc->swpriv;
 500         unsigned long flags;
 501
 502         spin_lock_irqsave(&priv->page_lock, flags);
 503         gsw_w32(gsw, (mac[0] << 8) | mac[1], GSW_REG_SMACCR1);
 504         gsw_w32(gsw, (mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5],
 505                 GSW_REG_SMACCR0);
 506         spin_unlock_irqrestore(&priv->page_lock, flags);
 507 }
 508
 509 static struct of_device_id gsw_match[] = {
 510         { .compatible = "ralink,mt7620a-gsw" },
 511         {}
 512 };
 513
 514 int mt7620_gsw_config(struct fe_priv *priv)
 515 {
 516         struct mt7620_gsw *gsw = (struct mt7620_gsw *) priv->soc->swpriv;
 517
 518         /* is the mt7530 internal or external */
 519         if (priv->mii_bus && priv->mii_bus->phy_map[0x1f]) {
 520                 mt7530_probe(priv->device, gsw->base, NULL, 0);
 521                 mt7530_probe(priv->device, NULL, priv->mii_bus, 1);
 522         } else {
 523                 mt7530_probe(priv->device, gsw->base, NULL, 1);
 524         }
 525
 526         return 0;
 527 }
 528
 529 int mt7620_gsw_probe(struct fe_priv *priv)
 530 {
 531         struct mt7620_gsw *gsw;
 532         struct device_node *np;
 533         const char *port4 = NULL;
 534
 535         np = of_find_matching_node(NULL, gsw_match);
 536         if (!np) {
 537                 dev_err(priv->device, "no gsw node found\n");
 538                 return -EINVAL;
 539         }
 540         np = of_node_get(np);
 541
 542         gsw = devm_kzalloc(priv->device, sizeof(struct mt7620_gsw), GFP_KERNEL);
 543         if (!gsw) {
 544                 dev_err(priv->device, "no gsw memory for private data\n");
 545                 return -ENOMEM;
 546         }
 547
 548         gsw->irq = irq_of_parse_and_map(np, 0);
 549         if (!gsw->irq) {
 550                 dev_err(priv->device, "no gsw irq resource found\n");
 551                 return -ENOMEM;
 552         }
 553
 554         gsw->base = of_iomap(np, 0);
 555         if (!gsw->base) {
 556                 dev_err(priv->device, "gsw ioremap failed\n");
 557                 return -ENOMEM;
 558         }
 559
 560         gsw->dev = priv->device;
 561         priv->soc->swpriv = gsw;
 562
 563         of_property_read_string(np, "ralink,port4", &port4);
 564         if (port4 && !strcmp(port4, "ephy"))
 565                 gsw->port4 = PORT4_EPHY;
 566         else if (port4 && !strcmp(port4, "gmac"))
 567                 gsw->port4 = PORT4_EXT;
 568         else
 569                 WARN_ON(port4);
 570
 571         gsw_hw_init(gsw, np);
 572
 573         gsw_w32(gsw, ~PORT_IRQ_ST_CHG, GSW_REG_IMR);
 574         request_irq(gsw->irq, gsw_interrupt, 0, "gsw", priv);
 575
 576         return 0;
 577 }