1 /* This program is free software; you can redistribute it and/or modify
2 * it under the terms of the GNU General Public License as published by
3 * the Free Software Foundation; version 2 of the License
5 * This program is distributed in the hope that it will be useful,
6 * but WITHOUT ANY WARRANTY; without even the implied warranty of
7 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
8 * GNU General Public License for more details.
10 * Copyright (C) 2009-2015 John Crispin <blogic@openwrt.org>
11 * Copyright (C) 2009-2015 Felix Fietkau <nbd@nbd.name>
12 * Copyright (C) 2013-2015 Michael Lee <igvtee@gmail.com>
15 #include <linux/module.h>
16 #include <linux/kernel.h>
17 #include <linux/types.h>
18 #include <linux/dma-mapping.h>
19 #include <linux/init.h>
20 #include <linux/skbuff.h>
21 #include <linux/etherdevice.h>
22 #include <linux/ethtool.h>
23 #include <linux/platform_device.h>
24 #include <linux/of_device.h>
25 #include <linux/clk.h>
26 #include <linux/of_net.h>
27 #include <linux/of_mdio.h>
28 #include <linux/if_vlan.h>
29 #include <linux/reset.h>
30 #include <linux/tcp.h>
32 #include <linux/bug.h>
33 #include <linux/netfilter.h>
34 #include <net/netfilter/nf_flow_table.h>
35 #include <linux/of_gpio.h>
36 #include <linux/gpio.h>
37 #include <linux/gpio/consumer.h>
39 #include <asm/mach-ralink/ralink_regs.h>
41 #include "mtk_eth_soc.h"
45 #define MAX_RX_LENGTH 1536
46 #define FE_RX_ETH_HLEN (VLAN_ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN)
47 #define FE_RX_HLEN (NET_SKB_PAD + FE_RX_ETH_HLEN + NET_IP_ALIGN)
48 #define DMA_DUMMY_DESC 0xffffffff
49 #define FE_DEFAULT_MSG_ENABLE \
59 #define TX_DMA_DESP2_DEF (TX_DMA_LS0 | TX_DMA_DONE)
60 #define TX_DMA_DESP4_DEF (TX_DMA_QN(3) | TX_DMA_PN(1))
61 #define NEXT_TX_DESP_IDX(X) (((X) + 1) & (ring->tx_ring_size - 1))
62 #define NEXT_RX_DESP_IDX(X) (((X) + 1) & (ring->rx_ring_size - 1))
64 static int fe_msg_level
= -1;
65 module_param_named(msg_level
, fe_msg_level
, int, 0);
66 MODULE_PARM_DESC(msg_level
, "Message level (-1=defaults,0=none,...,16=all)");
68 static const u16 fe_reg_table_default
[FE_REG_COUNT
] = {
69 [FE_REG_PDMA_GLO_CFG
] = FE_PDMA_GLO_CFG
,
70 [FE_REG_PDMA_RST_CFG
] = FE_PDMA_RST_CFG
,
71 [FE_REG_DLY_INT_CFG
] = FE_DLY_INT_CFG
,
72 [FE_REG_TX_BASE_PTR0
] = FE_TX_BASE_PTR0
,
73 [FE_REG_TX_MAX_CNT0
] = FE_TX_MAX_CNT0
,
74 [FE_REG_TX_CTX_IDX0
] = FE_TX_CTX_IDX0
,
75 [FE_REG_TX_DTX_IDX0
] = FE_TX_DTX_IDX0
,
76 [FE_REG_RX_BASE_PTR0
] = FE_RX_BASE_PTR0
,
77 [FE_REG_RX_MAX_CNT0
] = FE_RX_MAX_CNT0
,
78 [FE_REG_RX_CALC_IDX0
] = FE_RX_CALC_IDX0
,
79 [FE_REG_RX_DRX_IDX0
] = FE_RX_DRX_IDX0
,
80 [FE_REG_FE_INT_ENABLE
] = FE_FE_INT_ENABLE
,
81 [FE_REG_FE_INT_STATUS
] = FE_FE_INT_STATUS
,
82 [FE_REG_FE_DMA_VID_BASE
] = FE_DMA_VID0
,
83 [FE_REG_FE_COUNTER_BASE
] = FE_GDMA1_TX_GBCNT
,
84 [FE_REG_FE_RST_GL
] = FE_FE_RST_GL
,
87 static const u16
*fe_reg_table
= fe_reg_table_default
;
91 void (*action
)(struct fe_priv
*);
94 static void __iomem
*fe_base
;
96 void fe_w32(u32 val
, unsigned reg
)
98 __raw_writel(val
, fe_base
+ reg
);
101 u32
fe_r32(unsigned reg
)
103 return __raw_readl(fe_base
+ reg
);
106 void fe_reg_w32(u32 val
, enum fe_reg reg
)
108 fe_w32(val
, fe_reg_table
[reg
]);
111 u32
fe_reg_r32(enum fe_reg reg
)
113 return fe_r32(fe_reg_table
[reg
]);
116 void fe_m32(struct fe_priv
*eth
, u32 clear
, u32 set
, unsigned reg
)
120 spin_lock(ð
->page_lock
);
121 val
= __raw_readl(fe_base
+ reg
);
124 __raw_writel(val
, fe_base
+ reg
);
125 spin_unlock(ð
->page_lock
);
128 static void fe_reset_fe(struct fe_priv
*priv
)
133 reset_control_assert(priv
->resets
);
134 usleep_range(60, 120);
135 reset_control_deassert(priv
->resets
);
136 usleep_range(1000, 1200);
139 static inline void fe_int_disable(u32 mask
)
141 fe_reg_w32(fe_reg_r32(FE_REG_FE_INT_ENABLE
) & ~mask
,
142 FE_REG_FE_INT_ENABLE
);
144 fe_reg_r32(FE_REG_FE_INT_ENABLE
);
147 static inline void fe_int_enable(u32 mask
)
149 fe_reg_w32(fe_reg_r32(FE_REG_FE_INT_ENABLE
) | mask
,
150 FE_REG_FE_INT_ENABLE
);
152 fe_reg_r32(FE_REG_FE_INT_ENABLE
);
155 static inline void fe_hw_set_macaddr(struct fe_priv
*priv
, const unsigned char *mac
)
159 spin_lock_irqsave(&priv
->page_lock
, flags
);
160 fe_w32((mac
[0] << 8) | mac
[1], FE_GDMA1_MAC_ADRH
);
161 fe_w32((mac
[2] << 24) | (mac
[3] << 16) | (mac
[4] << 8) | mac
[5],
163 spin_unlock_irqrestore(&priv
->page_lock
, flags
);
166 static int fe_set_mac_address(struct net_device
*dev
, void *p
)
168 int ret
= eth_mac_addr(dev
, p
);
171 struct fe_priv
*priv
= netdev_priv(dev
);
173 if (priv
->soc
->set_mac
)
174 priv
->soc
->set_mac(priv
, dev
->dev_addr
);
176 fe_hw_set_macaddr(priv
, p
);
182 static inline int fe_max_frag_size(int mtu
)
184 /* make sure buf_size will be at least MAX_RX_LENGTH */
185 if (mtu
+ FE_RX_ETH_HLEN
< MAX_RX_LENGTH
)
186 mtu
= MAX_RX_LENGTH
- FE_RX_ETH_HLEN
;
188 return SKB_DATA_ALIGN(FE_RX_HLEN
+ mtu
) +
189 SKB_DATA_ALIGN(sizeof(struct skb_shared_info
));
192 static inline int fe_max_buf_size(int frag_size
)
194 int buf_size
= frag_size
- NET_SKB_PAD
- NET_IP_ALIGN
-
195 SKB_DATA_ALIGN(sizeof(struct skb_shared_info
));
197 BUG_ON(buf_size
< MAX_RX_LENGTH
);
201 static inline void fe_get_rxd(struct fe_rx_dma
*rxd
, struct fe_rx_dma
*dma_rxd
)
203 rxd
->rxd1
= dma_rxd
->rxd1
;
204 rxd
->rxd2
= dma_rxd
->rxd2
;
205 rxd
->rxd3
= dma_rxd
->rxd3
;
206 rxd
->rxd4
= dma_rxd
->rxd4
;
209 static inline void fe_set_txd(struct fe_tx_dma
*txd
, struct fe_tx_dma
*dma_txd
)
211 dma_txd
->txd1
= txd
->txd1
;
212 dma_txd
->txd3
= txd
->txd3
;
213 dma_txd
->txd4
= txd
->txd4
;
214 /* clean dma done flag last */
215 dma_txd
->txd2
= txd
->txd2
;
218 static void fe_clean_rx(struct fe_priv
*priv
)
220 struct fe_rx_ring
*ring
= &priv
->rx_ring
;
225 for (i
= 0; i
< ring
->rx_ring_size
; i
++)
226 if (ring
->rx_data
[i
]) {
227 if (ring
->rx_dma
&& ring
->rx_dma
[i
].rxd1
)
228 dma_unmap_single(priv
->dev
,
229 ring
->rx_dma
[i
].rxd1
,
232 skb_free_frag(ring
->rx_data
[i
]);
235 kfree(ring
->rx_data
);
236 ring
->rx_data
= NULL
;
240 dma_free_coherent(priv
->dev
,
241 ring
->rx_ring_size
* sizeof(*ring
->rx_dma
),
247 if (!ring
->frag_cache
.va
)
250 page
= virt_to_page(ring
->frag_cache
.va
);
251 __page_frag_cache_drain(page
, ring
->frag_cache
.pagecnt_bias
);
252 memset(&ring
->frag_cache
, 0, sizeof(ring
->frag_cache
));
255 static int fe_alloc_rx(struct fe_priv
*priv
)
257 struct fe_rx_ring
*ring
= &priv
->rx_ring
;
260 ring
->rx_data
= kcalloc(ring
->rx_ring_size
, sizeof(*ring
->rx_data
),
265 for (i
= 0; i
< ring
->rx_ring_size
; i
++) {
266 ring
->rx_data
[i
] = page_frag_alloc(&ring
->frag_cache
,
269 if (!ring
->rx_data
[i
])
273 ring
->rx_dma
= dma_alloc_coherent(priv
->dev
,
274 ring
->rx_ring_size
* sizeof(*ring
->rx_dma
),
276 GFP_ATOMIC
| __GFP_ZERO
);
280 if (priv
->flags
& FE_FLAG_RX_2B_OFFSET
)
284 for (i
= 0; i
< ring
->rx_ring_size
; i
++) {
285 dma_addr_t dma_addr
= dma_map_single(priv
->dev
,
286 ring
->rx_data
[i
] + NET_SKB_PAD
+ pad
,
289 if (unlikely(dma_mapping_error(priv
->dev
, dma_addr
)))
291 ring
->rx_dma
[i
].rxd1
= (unsigned int)dma_addr
;
293 if (priv
->flags
& FE_FLAG_RX_SG_DMA
)
294 ring
->rx_dma
[i
].rxd2
= RX_DMA_PLEN0(ring
->rx_buf_size
);
296 ring
->rx_dma
[i
].rxd2
= RX_DMA_LSO
;
298 ring
->rx_calc_idx
= ring
->rx_ring_size
- 1;
299 /* make sure that all changes to the dma ring are flushed before we
304 fe_reg_w32(ring
->rx_phys
, FE_REG_RX_BASE_PTR0
);
305 fe_reg_w32(ring
->rx_ring_size
, FE_REG_RX_MAX_CNT0
);
306 fe_reg_w32(ring
->rx_calc_idx
, FE_REG_RX_CALC_IDX0
);
307 fe_reg_w32(FE_PST_DRX_IDX0
, FE_REG_PDMA_RST_CFG
);
315 static void fe_txd_unmap(struct device
*dev
, struct fe_tx_buf
*tx_buf
)
317 if (dma_unmap_len(tx_buf
, dma_len0
))
319 dma_unmap_addr(tx_buf
, dma_addr0
),
320 dma_unmap_len(tx_buf
, dma_len0
),
323 if (dma_unmap_len(tx_buf
, dma_len1
))
325 dma_unmap_addr(tx_buf
, dma_addr1
),
326 dma_unmap_len(tx_buf
, dma_len1
),
329 dma_unmap_len_set(tx_buf
, dma_addr0
, 0);
330 dma_unmap_len_set(tx_buf
, dma_addr1
, 0);
331 if (tx_buf
->skb
&& (tx_buf
->skb
!= (struct sk_buff
*)DMA_DUMMY_DESC
))
332 dev_kfree_skb_any(tx_buf
->skb
);
336 static void fe_clean_tx(struct fe_priv
*priv
)
339 struct device
*dev
= priv
->dev
;
340 struct fe_tx_ring
*ring
= &priv
->tx_ring
;
343 for (i
= 0; i
< ring
->tx_ring_size
; i
++)
344 fe_txd_unmap(dev
, &ring
->tx_buf
[i
]);
350 dma_free_coherent(dev
,
351 ring
->tx_ring_size
* sizeof(*ring
->tx_dma
),
357 netdev_reset_queue(priv
->netdev
);
360 static int fe_alloc_tx(struct fe_priv
*priv
)
363 struct fe_tx_ring
*ring
= &priv
->tx_ring
;
365 ring
->tx_free_idx
= 0;
366 ring
->tx_next_idx
= 0;
367 ring
->tx_thresh
= max((unsigned long)ring
->tx_ring_size
>> 2,
370 ring
->tx_buf
= kcalloc(ring
->tx_ring_size
, sizeof(*ring
->tx_buf
),
375 ring
->tx_dma
= dma_alloc_coherent(priv
->dev
,
376 ring
->tx_ring_size
* sizeof(*ring
->tx_dma
),
378 GFP_ATOMIC
| __GFP_ZERO
);
382 for (i
= 0; i
< ring
->tx_ring_size
; i
++) {
383 if (priv
->soc
->tx_dma
)
384 priv
->soc
->tx_dma(&ring
->tx_dma
[i
]);
385 ring
->tx_dma
[i
].txd2
= TX_DMA_DESP2_DEF
;
387 /* make sure that all changes to the dma ring are flushed before we
392 fe_reg_w32(ring
->tx_phys
, FE_REG_TX_BASE_PTR0
);
393 fe_reg_w32(ring
->tx_ring_size
, FE_REG_TX_MAX_CNT0
);
394 fe_reg_w32(0, FE_REG_TX_CTX_IDX0
);
395 fe_reg_w32(FE_PST_DTX_IDX0
, FE_REG_PDMA_RST_CFG
);
403 static int fe_init_dma(struct fe_priv
*priv
)
407 err
= fe_alloc_tx(priv
);
411 err
= fe_alloc_rx(priv
);
418 static void fe_free_dma(struct fe_priv
*priv
)
424 void fe_stats_update(struct fe_priv
*priv
)
426 struct fe_hw_stats
*hwstats
= priv
->hw_stats
;
427 unsigned int base
= fe_reg_table
[FE_REG_FE_COUNTER_BASE
];
430 u64_stats_update_begin(&hwstats
->syncp
);
432 if (IS_ENABLED(CONFIG_SOC_MT7621
)) {
433 hwstats
->rx_bytes
+= fe_r32(base
);
434 stats
= fe_r32(base
+ 0x04);
436 hwstats
->rx_bytes
+= (stats
<< 32);
437 hwstats
->rx_packets
+= fe_r32(base
+ 0x08);
438 hwstats
->rx_overflow
+= fe_r32(base
+ 0x10);
439 hwstats
->rx_fcs_errors
+= fe_r32(base
+ 0x14);
440 hwstats
->rx_short_errors
+= fe_r32(base
+ 0x18);
441 hwstats
->rx_long_errors
+= fe_r32(base
+ 0x1c);
442 hwstats
->rx_checksum_errors
+= fe_r32(base
+ 0x20);
443 hwstats
->rx_flow_control_packets
+= fe_r32(base
+ 0x24);
444 hwstats
->tx_skip
+= fe_r32(base
+ 0x28);
445 hwstats
->tx_collisions
+= fe_r32(base
+ 0x2c);
446 hwstats
->tx_bytes
+= fe_r32(base
+ 0x30);
447 stats
= fe_r32(base
+ 0x34);
449 hwstats
->tx_bytes
+= (stats
<< 32);
450 hwstats
->tx_packets
+= fe_r32(base
+ 0x38);
452 hwstats
->tx_bytes
+= fe_r32(base
);
453 hwstats
->tx_packets
+= fe_r32(base
+ 0x04);
454 hwstats
->tx_skip
+= fe_r32(base
+ 0x08);
455 hwstats
->tx_collisions
+= fe_r32(base
+ 0x0c);
456 hwstats
->rx_bytes
+= fe_r32(base
+ 0x20);
457 hwstats
->rx_packets
+= fe_r32(base
+ 0x24);
458 hwstats
->rx_overflow
+= fe_r32(base
+ 0x28);
459 hwstats
->rx_fcs_errors
+= fe_r32(base
+ 0x2c);
460 hwstats
->rx_short_errors
+= fe_r32(base
+ 0x30);
461 hwstats
->rx_long_errors
+= fe_r32(base
+ 0x34);
462 hwstats
->rx_checksum_errors
+= fe_r32(base
+ 0x38);
463 hwstats
->rx_flow_control_packets
+= fe_r32(base
+ 0x3c);
466 u64_stats_update_end(&hwstats
->syncp
);
469 static void fe_get_stats64(struct net_device
*dev
,
470 struct rtnl_link_stats64
*storage
)
472 struct fe_priv
*priv
= netdev_priv(dev
);
473 struct fe_hw_stats
*hwstats
= priv
->hw_stats
;
474 unsigned int base
= fe_reg_table
[FE_REG_FE_COUNTER_BASE
];
478 netdev_stats_to_stats64(storage
, &dev
->stats
);
482 if (netif_running(dev
) && netif_device_present(dev
)) {
483 if (spin_trylock_bh(&hwstats
->stats_lock
)) {
484 fe_stats_update(priv
);
485 spin_unlock_bh(&hwstats
->stats_lock
);
490 start
= u64_stats_fetch_begin(&hwstats
->syncp
);
491 storage
->rx_packets
= hwstats
->rx_packets
;
492 storage
->tx_packets
= hwstats
->tx_packets
;
493 storage
->rx_bytes
= hwstats
->rx_bytes
;
494 storage
->tx_bytes
= hwstats
->tx_bytes
;
495 storage
->collisions
= hwstats
->tx_collisions
;
496 storage
->rx_length_errors
= hwstats
->rx_short_errors
+
497 hwstats
->rx_long_errors
;
498 storage
->rx_over_errors
= hwstats
->rx_overflow
;
499 storage
->rx_crc_errors
= hwstats
->rx_fcs_errors
;
500 storage
->rx_errors
= hwstats
->rx_checksum_errors
;
501 storage
->tx_aborted_errors
= hwstats
->tx_skip
;
502 } while (u64_stats_fetch_retry(&hwstats
->syncp
, start
));
504 storage
->tx_errors
= priv
->netdev
->stats
.tx_errors
;
505 storage
->rx_dropped
= priv
->netdev
->stats
.rx_dropped
;
506 storage
->tx_dropped
= priv
->netdev
->stats
.tx_dropped
;
509 static int fe_vlan_rx_add_vid(struct net_device
*dev
,
510 __be16 proto
, u16 vid
)
512 struct fe_priv
*priv
= netdev_priv(dev
);
513 u32 idx
= (vid
& 0xf);
516 if (!((fe_reg_table
[FE_REG_FE_DMA_VID_BASE
]) &&
517 (dev
->features
& NETIF_F_HW_VLAN_CTAG_TX
)))
520 if (test_bit(idx
, &priv
->vlan_map
)) {
521 netdev_warn(dev
, "disable tx vlan offload\n");
522 dev
->wanted_features
&= ~NETIF_F_HW_VLAN_CTAG_TX
;
523 netdev_update_features(dev
);
525 vlan_cfg
= fe_r32(fe_reg_table
[FE_REG_FE_DMA_VID_BASE
] +
529 vlan_cfg
|= (vid
<< 16);
531 vlan_cfg
&= 0xffff0000;
534 fe_w32(vlan_cfg
, fe_reg_table
[FE_REG_FE_DMA_VID_BASE
] +
536 set_bit(idx
, &priv
->vlan_map
);
542 static int fe_vlan_rx_kill_vid(struct net_device
*dev
,
543 __be16 proto
, u16 vid
)
545 struct fe_priv
*priv
= netdev_priv(dev
);
546 u32 idx
= (vid
& 0xf);
548 if (!((fe_reg_table
[FE_REG_FE_DMA_VID_BASE
]) &&
549 (dev
->features
& NETIF_F_HW_VLAN_CTAG_TX
)))
552 clear_bit(idx
, &priv
->vlan_map
);
557 static inline u32
fe_empty_txd(struct fe_tx_ring
*ring
)
560 return (u32
)(ring
->tx_ring_size
-
561 ((ring
->tx_next_idx
- ring
->tx_free_idx
) &
562 (ring
->tx_ring_size
- 1)));
565 struct fe_map_state
{
567 struct fe_tx_dma txd
;
573 static void fe_tx_dma_write_desc(struct fe_tx_ring
*ring
, struct fe_map_state
*st
)
575 fe_set_txd(&st
->txd
, &ring
->tx_dma
[st
->ring_idx
]);
576 memset(&st
->txd
, 0, sizeof(st
->txd
));
577 st
->txd
.txd4
= st
->def_txd4
;
578 st
->ring_idx
= NEXT_TX_DESP_IDX(st
->ring_idx
);
581 static int __fe_tx_dma_map_page(struct fe_tx_ring
*ring
, struct fe_map_state
*st
,
582 struct page
*page
, size_t offset
, size_t size
)
584 struct device
*dev
= st
->dev
;
585 struct fe_tx_buf
*tx_buf
;
586 dma_addr_t mapped_addr
;
588 mapped_addr
= dma_map_page(dev
, page
, offset
, size
, DMA_TO_DEVICE
);
589 if (unlikely(dma_mapping_error(dev
, mapped_addr
)))
592 if (st
->i
&& !(st
->i
& 1))
593 fe_tx_dma_write_desc(ring
, st
);
595 tx_buf
= &ring
->tx_buf
[st
->ring_idx
];
597 st
->txd
.txd3
= mapped_addr
;
598 st
->txd
.txd2
|= TX_DMA_PLEN1(size
);
599 dma_unmap_addr_set(tx_buf
, dma_addr1
, mapped_addr
);
600 dma_unmap_len_set(tx_buf
, dma_len1
, size
);
602 tx_buf
->skb
= (struct sk_buff
*)DMA_DUMMY_DESC
;
603 st
->txd
.txd1
= mapped_addr
;
604 st
->txd
.txd2
= TX_DMA_PLEN0(size
);
605 dma_unmap_addr_set(tx_buf
, dma_addr0
, mapped_addr
);
606 dma_unmap_len_set(tx_buf
, dma_len0
, size
);
613 static int fe_tx_dma_map_page(struct fe_tx_ring
*ring
, struct fe_map_state
*st
,
614 struct page
*page
, size_t offset
, size_t size
)
620 cur_size
= min_t(size_t, size
, TX_DMA_BUF_LEN
);
622 ret
= __fe_tx_dma_map_page(ring
, st
, page
, offset
, cur_size
);
633 static int fe_tx_dma_map_skb(struct fe_tx_ring
*ring
, struct fe_map_state
*st
,
636 struct page
*page
= virt_to_page(skb
->data
);
637 size_t offset
= offset_in_page(skb
->data
);
638 size_t size
= skb_headlen(skb
);
640 return fe_tx_dma_map_page(ring
, st
, page
, offset
, size
);
643 static inline struct sk_buff
*
644 fe_next_frag(struct sk_buff
*head
, struct sk_buff
*skb
)
649 if (skb_has_frag_list(skb
))
650 return skb_shinfo(skb
)->frag_list
;
656 static int fe_tx_map_dma(struct sk_buff
*skb
, struct net_device
*dev
,
657 int tx_num
, struct fe_tx_ring
*ring
)
659 struct fe_priv
*priv
= netdev_priv(dev
);
660 struct fe_map_state st
= {
662 .ring_idx
= ring
->tx_next_idx
,
664 struct sk_buff
*head
= skb
;
665 struct fe_tx_buf
*tx_buf
;
666 unsigned int nr_frags
;
669 /* init tx descriptor */
670 if (priv
->soc
->tx_dma
)
671 priv
->soc
->tx_dma(&st
.txd
);
673 st
.txd
.txd4
= TX_DMA_DESP4_DEF
;
674 st
.def_txd4
= st
.txd
.txd4
;
676 /* TX Checksum offload */
677 if (skb
->ip_summed
== CHECKSUM_PARTIAL
)
678 st
.txd
.txd4
|= TX_DMA_CHKSUM
;
680 /* VLAN header offload */
681 if (skb_vlan_tag_present(skb
)) {
682 u16 tag
= skb_vlan_tag_get(skb
);
684 if (IS_ENABLED(CONFIG_SOC_MT7621
))
685 st
.txd
.txd4
|= TX_DMA_INS_VLAN_MT7621
| tag
;
687 st
.txd
.txd4
|= TX_DMA_INS_VLAN
|
688 ((tag
>> VLAN_PRIO_SHIFT
) << 4) |
692 /* TSO: fill MSS info in tcp checksum field */
693 if (skb_is_gso(skb
)) {
694 if (skb_cow_head(skb
, 0)) {
695 netif_warn(priv
, tx_err
, dev
,
696 "GSO expand head fail.\n");
699 if (skb_shinfo(skb
)->gso_type
&
700 (SKB_GSO_TCPV4
| SKB_GSO_TCPV6
)) {
701 st
.txd
.txd4
|= TX_DMA_TSO
;
702 tcp_hdr(skb
)->check
= htons(skb_shinfo(skb
)->gso_size
);
707 if (skb_headlen(skb
) && fe_tx_dma_map_skb(ring
, &st
, skb
))
711 nr_frags
= skb_shinfo(skb
)->nr_frags
;
712 for (i
= 0; i
< nr_frags
; i
++) {
715 frag
= &skb_shinfo(skb
)->frags
[i
];
716 if (fe_tx_dma_map_page(ring
, &st
, skb_frag_page(frag
),
717 skb_frag_off(frag
), skb_frag_size(frag
)))
721 skb
= fe_next_frag(head
, skb
);
725 /* set last segment */
727 st
.txd
.txd2
|= TX_DMA_LS0
;
729 st
.txd
.txd2
|= TX_DMA_LS1
;
731 /* store skb to cleanup */
732 tx_buf
= &ring
->tx_buf
[st
.ring_idx
];
735 netdev_sent_queue(dev
, head
->len
);
736 skb_tx_timestamp(head
);
738 fe_tx_dma_write_desc(ring
, &st
);
739 ring
->tx_next_idx
= st
.ring_idx
;
741 /* make sure that all changes to the dma ring are flushed before we
745 if (unlikely(fe_empty_txd(ring
) <= ring
->tx_thresh
)) {
746 netif_stop_queue(dev
);
748 if (unlikely(fe_empty_txd(ring
) > ring
->tx_thresh
))
749 netif_wake_queue(dev
);
752 if (netif_xmit_stopped(netdev_get_tx_queue(dev
, 0)) || !netdev_xmit_more())
753 fe_reg_w32(ring
->tx_next_idx
, FE_REG_TX_CTX_IDX0
);
758 j
= ring
->tx_next_idx
;
759 for (i
= 0; i
< tx_num
; i
++) {
761 fe_txd_unmap(priv
->dev
, &ring
->tx_buf
[j
]);
762 ring
->tx_dma
[j
].txd2
= TX_DMA_DESP2_DEF
;
764 j
= NEXT_TX_DESP_IDX(j
);
766 /* make sure that all changes to the dma ring are flushed before we
775 static inline int fe_skb_padto(struct sk_buff
*skb
, struct fe_priv
*priv
)
781 if (unlikely(skb
->len
< VLAN_ETH_ZLEN
)) {
782 if ((priv
->flags
& FE_FLAG_PADDING_64B
) &&
783 !(priv
->flags
& FE_FLAG_PADDING_BUG
))
786 if (skb_vlan_tag_present(skb
))
788 else if (skb
->protocol
== cpu_to_be16(ETH_P_8021Q
))
790 else if (!(priv
->flags
& FE_FLAG_PADDING_64B
))
795 if (skb
->len
< len
) {
796 ret
= skb_pad(skb
, len
- skb
->len
);
800 skb_set_tail_pointer(skb
, len
);
807 static inline int fe_cal_txd_req(struct sk_buff
*skb
)
809 struct sk_buff
*head
= skb
;
815 if (skb_is_gso(skb
)) {
816 for (i
= 0; i
< skb_shinfo(skb
)->nr_frags
; i
++) {
817 frag
= &skb_shinfo(skb
)->frags
[i
];
818 nfrags
+= DIV_ROUND_UP(skb_frag_size(frag
), TX_DMA_BUF_LEN
);
821 nfrags
+= skb_shinfo(skb
)->nr_frags
;
824 skb
= fe_next_frag(head
, skb
);
828 return DIV_ROUND_UP(nfrags
, 2);
831 static int fe_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
833 struct fe_priv
*priv
= netdev_priv(dev
);
834 struct fe_tx_ring
*ring
= &priv
->tx_ring
;
835 struct net_device_stats
*stats
= &dev
->stats
;
839 if (fe_skb_padto(skb
, priv
)) {
840 netif_warn(priv
, tx_err
, dev
, "tx padding failed!\n");
844 tx_num
= fe_cal_txd_req(skb
);
845 if (unlikely(fe_empty_txd(ring
) <= tx_num
)) {
846 netif_stop_queue(dev
);
847 netif_err(priv
, tx_queued
, dev
,
848 "Tx Ring full when queue awake!\n");
849 return NETDEV_TX_BUSY
;
852 if (fe_tx_map_dma(skb
, dev
, tx_num
, ring
) < 0) {
856 stats
->tx_bytes
+= len
;
862 static int fe_poll_rx(struct napi_struct
*napi
, int budget
,
863 struct fe_priv
*priv
, u32 rx_intr
)
865 struct net_device
*netdev
= priv
->netdev
;
866 struct net_device_stats
*stats
= &netdev
->stats
;
867 struct fe_soc_data
*soc
= priv
->soc
;
868 struct fe_rx_ring
*ring
= &priv
->rx_ring
;
869 int idx
= ring
->rx_calc_idx
;
873 struct fe_rx_dma
*rxd
, trxd
;
876 if (netdev
->features
& NETIF_F_RXCSUM
)
877 checksum_bit
= soc
->checksum_bit
;
881 if (priv
->flags
& FE_FLAG_RX_2B_OFFSET
)
886 while (done
< budget
) {
890 idx
= NEXT_RX_DESP_IDX(idx
);
891 rxd
= &ring
->rx_dma
[idx
];
892 data
= ring
->rx_data
[idx
];
894 fe_get_rxd(&trxd
, rxd
);
895 if (!(trxd
.rxd2
& RX_DMA_DONE
))
898 /* alloc new buffer */
899 new_data
= page_frag_alloc(&ring
->frag_cache
, ring
->frag_size
,
901 if (unlikely(!new_data
)) {
905 dma_addr
= dma_map_single(priv
->dev
,
906 new_data
+ NET_SKB_PAD
+ pad
,
909 if (unlikely(dma_mapping_error(priv
->dev
, dma_addr
))) {
910 skb_free_frag(new_data
);
915 skb
= build_skb(data
, ring
->frag_size
);
916 if (unlikely(!skb
)) {
917 skb_free_frag(new_data
);
920 skb_reserve(skb
, NET_SKB_PAD
+ NET_IP_ALIGN
);
922 dma_unmap_single(priv
->dev
, trxd
.rxd1
,
923 ring
->rx_buf_size
, DMA_FROM_DEVICE
);
924 pktlen
= RX_DMA_GET_PLEN0(trxd
.rxd2
);
926 skb_put(skb
, pktlen
);
927 if (trxd
.rxd4
& checksum_bit
)
928 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
930 skb_checksum_none_assert(skb
);
931 skb
->protocol
= eth_type_trans(skb
, netdev
);
933 if (netdev
->features
& NETIF_F_HW_VLAN_CTAG_RX
&&
934 RX_DMA_VID(trxd
.rxd3
))
935 __vlan_hwaccel_put_tag(skb
, htons(ETH_P_8021Q
),
936 RX_DMA_VID(trxd
.rxd3
));
939 stats
->rx_bytes
+= pktlen
;
941 napi_gro_receive(napi
, skb
);
943 ring
->rx_data
[idx
] = new_data
;
944 rxd
->rxd1
= (unsigned int)dma_addr
;
947 if (priv
->flags
& FE_FLAG_RX_SG_DMA
)
948 rxd
->rxd2
= RX_DMA_PLEN0(ring
->rx_buf_size
);
950 rxd
->rxd2
= RX_DMA_LSO
;
952 ring
->rx_calc_idx
= idx
;
953 /* make sure that all changes to the dma ring are flushed before
957 fe_reg_w32(ring
->rx_calc_idx
, FE_REG_RX_CALC_IDX0
);
962 fe_reg_w32(rx_intr
, FE_REG_FE_INT_STATUS
);
967 static int fe_poll_tx(struct fe_priv
*priv
, int budget
, u32 tx_intr
,
970 struct net_device
*netdev
= priv
->netdev
;
971 unsigned int bytes_compl
= 0;
973 struct fe_tx_buf
*tx_buf
;
976 struct fe_tx_ring
*ring
= &priv
->tx_ring
;
978 idx
= ring
->tx_free_idx
;
979 hwidx
= fe_reg_r32(FE_REG_TX_DTX_IDX0
);
981 while ((idx
!= hwidx
) && budget
) {
982 tx_buf
= &ring
->tx_buf
[idx
];
988 if (skb
!= (struct sk_buff
*)DMA_DUMMY_DESC
) {
989 bytes_compl
+= skb
->len
;
993 fe_txd_unmap(priv
->dev
, tx_buf
);
994 idx
= NEXT_TX_DESP_IDX(idx
);
996 ring
->tx_free_idx
= idx
;
999 /* read hw index again make sure no new tx packet */
1000 hwidx
= fe_reg_r32(FE_REG_TX_DTX_IDX0
);
1002 fe_reg_w32(tx_intr
, FE_REG_FE_INT_STATUS
);
1010 netdev_completed_queue(netdev
, done
, bytes_compl
);
1012 if (unlikely(netif_queue_stopped(netdev
) &&
1013 (fe_empty_txd(ring
) > ring
->tx_thresh
)))
1014 netif_wake_queue(netdev
);
1020 static int fe_poll(struct napi_struct
*napi
, int budget
)
1022 struct fe_priv
*priv
= container_of(napi
, struct fe_priv
, rx_napi
);
1023 struct fe_hw_stats
*hwstat
= priv
->hw_stats
;
1024 int tx_done
, rx_done
, tx_again
;
1025 u32 status
, fe_status
, status_reg
, mask
;
1026 u32 tx_intr
, rx_intr
, status_intr
;
1028 status
= fe_reg_r32(FE_REG_FE_INT_STATUS
);
1030 tx_intr
= priv
->soc
->tx_int
;
1031 rx_intr
= priv
->soc
->rx_int
;
1032 status_intr
= priv
->soc
->status_int
;
1037 if (fe_reg_table
[FE_REG_FE_INT_STATUS2
]) {
1038 fe_status
= fe_reg_r32(FE_REG_FE_INT_STATUS2
);
1039 status_reg
= FE_REG_FE_INT_STATUS2
;
1041 status_reg
= FE_REG_FE_INT_STATUS
;
1044 if (status
& tx_intr
)
1045 tx_done
= fe_poll_tx(priv
, budget
, tx_intr
, &tx_again
);
1047 if (status
& rx_intr
)
1048 rx_done
= fe_poll_rx(napi
, budget
, priv
, rx_intr
);
1050 if (unlikely(fe_status
& status_intr
)) {
1051 if (hwstat
&& spin_trylock(&hwstat
->stats_lock
)) {
1052 fe_stats_update(priv
);
1053 spin_unlock(&hwstat
->stats_lock
);
1055 fe_reg_w32(status_intr
, status_reg
);
1058 if (unlikely(netif_msg_intr(priv
))) {
1059 mask
= fe_reg_r32(FE_REG_FE_INT_ENABLE
);
1060 netdev_info(priv
->netdev
,
1061 "done tx %d, rx %d, intr 0x%08x/0x%x\n",
1062 tx_done
, rx_done
, status
, mask
);
1065 if (!tx_again
&& (rx_done
< budget
)) {
1066 status
= fe_reg_r32(FE_REG_FE_INT_STATUS
);
1067 if (status
& (tx_intr
| rx_intr
)) {
1068 /* let napi poll again */
1073 napi_complete_done(napi
, rx_done
);
1074 fe_int_enable(tx_intr
| rx_intr
);
1083 static void fe_tx_timeout(struct net_device
*dev
, unsigned int txqueue
)
1085 struct fe_priv
*priv
= netdev_priv(dev
);
1086 struct fe_tx_ring
*ring
= &priv
->tx_ring
;
1088 priv
->netdev
->stats
.tx_errors
++;
1089 netif_err(priv
, tx_err
, dev
,
1090 "transmit timed out\n");
1091 netif_info(priv
, drv
, dev
, "dma_cfg:%08x\n",
1092 fe_reg_r32(FE_REG_PDMA_GLO_CFG
));
1093 netif_info(priv
, drv
, dev
, "tx_ring=%d, "
1094 "base=%08x, max=%u, ctx=%u, dtx=%u, fdx=%hu, next=%hu\n",
1095 0, fe_reg_r32(FE_REG_TX_BASE_PTR0
),
1096 fe_reg_r32(FE_REG_TX_MAX_CNT0
),
1097 fe_reg_r32(FE_REG_TX_CTX_IDX0
),
1098 fe_reg_r32(FE_REG_TX_DTX_IDX0
),
1101 netif_info(priv
, drv
, dev
,
1102 "rx_ring=%d, base=%08x, max=%u, calc=%u, drx=%u\n",
1103 0, fe_reg_r32(FE_REG_RX_BASE_PTR0
),
1104 fe_reg_r32(FE_REG_RX_MAX_CNT0
),
1105 fe_reg_r32(FE_REG_RX_CALC_IDX0
),
1106 fe_reg_r32(FE_REG_RX_DRX_IDX0
));
1108 if (!test_and_set_bit(FE_FLAG_RESET_PENDING
, priv
->pending_flags
))
1109 schedule_work(&priv
->pending_work
);
1112 static irqreturn_t
fe_handle_irq(int irq
, void *dev
)
1114 struct fe_priv
*priv
= netdev_priv(dev
);
1115 u32 status
, int_mask
;
1117 status
= fe_reg_r32(FE_REG_FE_INT_STATUS
);
1119 if (unlikely(!status
))
1122 int_mask
= (priv
->soc
->rx_int
| priv
->soc
->tx_int
);
1123 if (likely(status
& int_mask
)) {
1124 if (likely(napi_schedule_prep(&priv
->rx_napi
))) {
1125 fe_int_disable(int_mask
);
1126 __napi_schedule(&priv
->rx_napi
);
1129 fe_reg_w32(status
, FE_REG_FE_INT_STATUS
);
1135 #ifdef CONFIG_NET_POLL_CONTROLLER
1136 static void fe_poll_controller(struct net_device
*dev
)
1138 struct fe_priv
*priv
= netdev_priv(dev
);
1139 u32 int_mask
= priv
->soc
->tx_int
| priv
->soc
->rx_int
;
1141 fe_int_disable(int_mask
);
1142 fe_handle_irq(dev
->irq
, dev
);
1143 fe_int_enable(int_mask
);
1147 int fe_set_clock_cycle(struct fe_priv
*priv
)
1149 unsigned long sysclk
= priv
->sysclk
;
1151 sysclk
/= FE_US_CYC_CNT_DIVISOR
;
1152 sysclk
<<= FE_US_CYC_CNT_SHIFT
;
1154 fe_w32((fe_r32(FE_FE_GLO_CFG
) &
1155 ~(FE_US_CYC_CNT_MASK
<< FE_US_CYC_CNT_SHIFT
)) |
1161 void fe_fwd_config(struct fe_priv
*priv
)
1165 fwd_cfg
= fe_r32(FE_GDMA1_FWD_CFG
);
1167 /* disable jumbo frame */
1168 if (priv
->flags
& FE_FLAG_JUMBO_FRAME
)
1169 fwd_cfg
&= ~FE_GDM1_JMB_EN
;
1171 /* set unicast/multicast/broadcast frame to cpu */
1174 fe_w32(fwd_cfg
, FE_GDMA1_FWD_CFG
);
1177 static void fe_rxcsum_config(bool enable
)
1180 fe_w32(fe_r32(FE_GDMA1_FWD_CFG
) | (FE_GDM1_ICS_EN
|
1181 FE_GDM1_TCS_EN
| FE_GDM1_UCS_EN
),
1184 fe_w32(fe_r32(FE_GDMA1_FWD_CFG
) & ~(FE_GDM1_ICS_EN
|
1185 FE_GDM1_TCS_EN
| FE_GDM1_UCS_EN
),
1189 static void fe_txcsum_config(bool enable
)
1192 fe_w32(fe_r32(FE_CDMA_CSG_CFG
) | (FE_ICS_GEN_EN
|
1193 FE_TCS_GEN_EN
| FE_UCS_GEN_EN
),
1196 fe_w32(fe_r32(FE_CDMA_CSG_CFG
) & ~(FE_ICS_GEN_EN
|
1197 FE_TCS_GEN_EN
| FE_UCS_GEN_EN
),
1201 void fe_csum_config(struct fe_priv
*priv
)
1203 struct net_device
*dev
= priv_netdev(priv
);
1205 fe_txcsum_config((dev
->features
& NETIF_F_IP_CSUM
));
1206 fe_rxcsum_config((dev
->features
& NETIF_F_RXCSUM
));
1209 static int fe_hw_init(struct net_device
*dev
)
1211 struct fe_priv
*priv
= netdev_priv(dev
);
1214 err
= devm_request_irq(priv
->dev
, dev
->irq
, fe_handle_irq
, 0,
1215 dev_name(priv
->dev
), dev
);
1219 if (priv
->soc
->set_mac
)
1220 priv
->soc
->set_mac(priv
, dev
->dev_addr
);
1222 fe_hw_set_macaddr(priv
, dev
->dev_addr
);
1224 /* disable delay interrupt */
1225 fe_reg_w32(0, FE_REG_DLY_INT_CFG
);
1227 fe_int_disable(priv
->soc
->tx_int
| priv
->soc
->rx_int
);
1229 /* frame engine will push VLAN tag regarding to VIDX feild in Tx desc */
1230 if (fe_reg_table
[FE_REG_FE_DMA_VID_BASE
])
1231 for (i
= 0; i
< 16; i
+= 2)
1232 fe_w32(((i
+ 1) << 16) + i
,
1233 fe_reg_table
[FE_REG_FE_DMA_VID_BASE
] +
1236 if (priv
->soc
->fwd_config(priv
))
1237 netdev_err(dev
, "unable to get clock\n");
1239 if (fe_reg_table
[FE_REG_FE_RST_GL
]) {
1240 fe_reg_w32(1, FE_REG_FE_RST_GL
);
1241 fe_reg_w32(0, FE_REG_FE_RST_GL
);
1247 static int fe_open(struct net_device
*dev
)
1249 struct fe_priv
*priv
= netdev_priv(dev
);
1250 unsigned long flags
;
1254 err
= fe_init_dma(priv
);
1260 spin_lock_irqsave(&priv
->page_lock
, flags
);
1262 val
= FE_TX_WB_DDONE
| FE_RX_DMA_EN
| FE_TX_DMA_EN
;
1263 if (priv
->flags
& FE_FLAG_RX_2B_OFFSET
)
1264 val
|= FE_RX_2B_OFFSET
;
1265 val
|= priv
->soc
->pdma_glo_cfg
;
1266 fe_reg_w32(val
, FE_REG_PDMA_GLO_CFG
);
1268 spin_unlock_irqrestore(&priv
->page_lock
, flags
);
1271 priv
->phy
->start(priv
);
1273 if (priv
->soc
->has_carrier
&& priv
->soc
->has_carrier(priv
))
1274 netif_carrier_on(dev
);
1276 napi_enable(&priv
->rx_napi
);
1277 fe_int_enable(priv
->soc
->tx_int
| priv
->soc
->rx_int
);
1278 netif_start_queue(dev
);
1283 static int fe_stop(struct net_device
*dev
)
1285 struct fe_priv
*priv
= netdev_priv(dev
);
1286 unsigned long flags
;
1289 netif_tx_disable(dev
);
1290 fe_int_disable(priv
->soc
->tx_int
| priv
->soc
->rx_int
);
1291 napi_disable(&priv
->rx_napi
);
1294 priv
->phy
->stop(priv
);
1296 spin_lock_irqsave(&priv
->page_lock
, flags
);
1298 fe_reg_w32(fe_reg_r32(FE_REG_PDMA_GLO_CFG
) &
1299 ~(FE_TX_WB_DDONE
| FE_RX_DMA_EN
| FE_TX_DMA_EN
),
1300 FE_REG_PDMA_GLO_CFG
);
1301 spin_unlock_irqrestore(&priv
->page_lock
, flags
);
1304 for (i
= 0; i
< 10; i
++) {
1305 if (fe_reg_r32(FE_REG_PDMA_GLO_CFG
) &
1306 (FE_TX_DMA_BUSY
| FE_RX_DMA_BUSY
)) {
1318 static void fe_reset_phy(struct fe_priv
*priv
)
1321 struct gpio_desc
*phy_reset
;
1323 phy_reset
= devm_gpiod_get_optional(priv
->dev
, "phy-reset",
1328 if (IS_ERR(phy_reset
)) {
1329 dev_err(priv
->dev
, "Error acquiring reset gpio pins: %ld\n",
1330 PTR_ERR(phy_reset
));
1334 err
= of_property_read_u32(priv
->dev
->of_node
, "phy-reset-duration",
1336 if (!err
&& msec
> 1000)
1342 usleep_range(msec
* 1000, msec
* 1000 + 1000);
1344 gpiod_set_value(phy_reset
, 0);
1347 static int __init
fe_init(struct net_device
*dev
)
1349 struct fe_priv
*priv
= netdev_priv(dev
);
1350 struct device_node
*port
;
1355 if (priv
->soc
->switch_init
) {
1356 err
= priv
->soc
->switch_init(priv
);
1358 if (err
== -EPROBE_DEFER
)
1361 netdev_err(dev
, "failed to initialize switch core\n");
1368 /* Set the MAC address if it is correct, if not use a random MAC address */
1369 if (of_get_ethdev_address(priv
->dev
->of_node
, dev
)) {
1370 eth_hw_addr_random(dev
);
1371 dev_err(priv
->dev
, "generated random MAC address %pM\n",
1375 err
= fe_mdio_init(priv
);
1379 if (priv
->soc
->port_init
)
1380 for_each_child_of_node(priv
->dev
->of_node
, port
)
1381 if (of_device_is_compatible(port
, "mediatek,eth-port") &&
1382 of_device_is_available(port
))
1383 priv
->soc
->port_init(priv
, port
);
1386 err
= priv
->phy
->connect(priv
);
1388 goto err_phy_disconnect
;
1391 err
= fe_hw_init(dev
);
1393 goto err_phy_disconnect
;
1395 if ((priv
->flags
& FE_FLAG_HAS_SWITCH
) && priv
->soc
->switch_config
)
1396 priv
->soc
->switch_config(priv
);
1402 priv
->phy
->disconnect(priv
);
1403 fe_mdio_cleanup(priv
);
1408 static void fe_uninit(struct net_device
*dev
)
1410 struct fe_priv
*priv
= netdev_priv(dev
);
1413 priv
->phy
->disconnect(priv
);
1414 fe_mdio_cleanup(priv
);
1416 fe_reg_w32(0, FE_REG_FE_INT_ENABLE
);
1419 static int fe_do_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
1421 struct fe_priv
*priv
= netdev_priv(dev
);
1427 return phy_mii_ioctl(priv
->phy_dev
, ifr
, cmd
);
1430 static int fe_change_mtu(struct net_device
*dev
, int new_mtu
)
1432 struct fe_priv
*priv
= netdev_priv(dev
);
1433 int frag_size
, old_mtu
;
1439 if (!(priv
->flags
& FE_FLAG_JUMBO_FRAME
))
1442 /* return early if the buffer sizes will not change */
1443 if (old_mtu
<= ETH_DATA_LEN
&& new_mtu
<= ETH_DATA_LEN
)
1445 if (old_mtu
> ETH_DATA_LEN
&& new_mtu
> ETH_DATA_LEN
)
1448 if (new_mtu
<= ETH_DATA_LEN
)
1449 priv
->rx_ring
.frag_size
= fe_max_frag_size(ETH_DATA_LEN
);
1451 priv
->rx_ring
.frag_size
= PAGE_SIZE
;
1452 priv
->rx_ring
.rx_buf_size
= fe_max_buf_size(priv
->rx_ring
.frag_size
);
1454 if (!netif_running(dev
))
1458 if (!IS_ENABLED(CONFIG_SOC_MT7621
)) {
1459 fwd_cfg
= fe_r32(FE_GDMA1_FWD_CFG
);
1460 if (new_mtu
<= ETH_DATA_LEN
) {
1461 fwd_cfg
&= ~FE_GDM1_JMB_EN
;
1463 frag_size
= fe_max_frag_size(new_mtu
);
1464 fwd_cfg
&= ~(FE_GDM1_JMB_LEN_MASK
<< FE_GDM1_JMB_LEN_SHIFT
);
1465 fwd_cfg
|= (DIV_ROUND_UP(frag_size
, 1024) <<
1466 FE_GDM1_JMB_LEN_SHIFT
) | FE_GDM1_JMB_EN
;
1468 fe_w32(fwd_cfg
, FE_GDMA1_FWD_CFG
);
1471 return fe_open(dev
);
1474 static const struct net_device_ops fe_netdev_ops
= {
1475 .ndo_init
= fe_init
,
1476 .ndo_uninit
= fe_uninit
,
1477 .ndo_open
= fe_open
,
1478 .ndo_stop
= fe_stop
,
1479 .ndo_start_xmit
= fe_start_xmit
,
1480 .ndo_set_mac_address
= fe_set_mac_address
,
1481 .ndo_validate_addr
= eth_validate_addr
,
1482 .ndo_eth_ioctl
= fe_do_ioctl
,
1483 .ndo_change_mtu
= fe_change_mtu
,
1484 .ndo_tx_timeout
= fe_tx_timeout
,
1485 .ndo_get_stats64
= fe_get_stats64
,
1486 .ndo_vlan_rx_add_vid
= fe_vlan_rx_add_vid
,
1487 .ndo_vlan_rx_kill_vid
= fe_vlan_rx_kill_vid
,
1488 #ifdef CONFIG_NET_POLL_CONTROLLER
1489 .ndo_poll_controller
= fe_poll_controller
,
1493 static void fe_reset_pending(struct fe_priv
*priv
)
1495 struct net_device
*dev
= priv
->netdev
;
1503 netif_alert(priv
, ifup
, dev
,
1504 "Driver up/down cycle failed, closing device.\n");
1510 static const struct fe_work_t fe_work
[] = {
1511 {FE_FLAG_RESET_PENDING
, fe_reset_pending
},
1514 static void fe_pending_work(struct work_struct
*work
)
1516 struct fe_priv
*priv
= container_of(work
, struct fe_priv
, pending_work
);
1520 for (i
= 0; i
< ARRAY_SIZE(fe_work
); i
++) {
1521 pending
= test_and_clear_bit(fe_work
[i
].bitnr
,
1522 priv
->pending_flags
);
1524 fe_work
[i
].action(priv
);
1528 static int fe_probe(struct platform_device
*pdev
)
1530 struct resource
*res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1531 const struct of_device_id
*match
;
1532 struct fe_soc_data
*soc
;
1533 struct net_device
*netdev
;
1534 struct fe_priv
*priv
;
1536 int err
, napi_weight
;
1538 err
= device_reset(&pdev
->dev
);
1540 dev_err(&pdev
->dev
, "failed to reset device\n");
1542 match
= of_match_device(of_fe_match
, &pdev
->dev
);
1543 soc
= (struct fe_soc_data
*)match
->data
;
1546 fe_reg_table
= soc
->reg_table
;
1548 soc
->reg_table
= fe_reg_table
;
1550 fe_base
= devm_ioremap_resource(&pdev
->dev
, res
);
1551 if (IS_ERR(fe_base
)) {
1552 err
= -EADDRNOTAVAIL
;
1556 netdev
= alloc_etherdev(sizeof(*priv
));
1558 dev_err(&pdev
->dev
, "alloc_etherdev failed\n");
1563 SET_NETDEV_DEV(netdev
, &pdev
->dev
);
1564 netdev
->netdev_ops
= &fe_netdev_ops
;
1565 netdev
->base_addr
= (unsigned long)fe_base
;
1567 netdev
->irq
= platform_get_irq(pdev
, 0);
1568 if (netdev
->irq
< 0) {
1569 dev_err(&pdev
->dev
, "no IRQ resource found\n");
1574 priv
= netdev_priv(netdev
);
1575 spin_lock_init(&priv
->page_lock
);
1576 priv
->resets
= devm_reset_control_array_get_exclusive(&pdev
->dev
);
1577 if (IS_ERR(priv
->resets
)) {
1578 dev_err(&pdev
->dev
, "Failed to get resets for FE and ESW cores: %pe\n", priv
->resets
);
1579 priv
->resets
= NULL
;
1583 soc
->init_data(soc
, netdev
);
1584 netdev
->vlan_features
= netdev
->hw_features
&
1585 ~(NETIF_F_HW_VLAN_CTAG_TX
|
1586 NETIF_F_HW_VLAN_CTAG_RX
);
1587 netdev
->features
|= netdev
->hw_features
;
1589 if (IS_ENABLED(CONFIG_SOC_MT7621
))
1590 netdev
->max_mtu
= 2048;
1592 /* fake rx vlan filter func. to support tx vlan offload func */
1593 if (fe_reg_table
[FE_REG_FE_DMA_VID_BASE
])
1594 netdev
->features
|= NETIF_F_HW_VLAN_CTAG_FILTER
;
1596 if (fe_reg_table
[FE_REG_FE_COUNTER_BASE
]) {
1597 priv
->hw_stats
= kzalloc(sizeof(*priv
->hw_stats
), GFP_KERNEL
);
1598 if (!priv
->hw_stats
) {
1602 spin_lock_init(&priv
->hw_stats
->stats_lock
);
1603 u64_stats_init(&priv
->hw_stats
->syncp
);
1606 sysclk
= devm_clk_get(&pdev
->dev
, NULL
);
1607 if (!IS_ERR(sysclk
)) {
1608 priv
->sysclk
= clk_get_rate(sysclk
);
1609 } else if ((priv
->flags
& FE_FLAG_CALIBRATE_CLK
)) {
1610 dev_err(&pdev
->dev
, "this soc needs a clk for calibration\n");
1615 priv
->switch_np
= of_parse_phandle(pdev
->dev
.of_node
, "mediatek,switch", 0);
1616 if ((priv
->flags
& FE_FLAG_HAS_SWITCH
) && !priv
->switch_np
) {
1617 dev_err(&pdev
->dev
, "failed to read switch phandle\n");
1622 priv
->netdev
= netdev
;
1623 priv
->dev
= &pdev
->dev
;
1625 priv
->msg_enable
= netif_msg_init(fe_msg_level
, FE_DEFAULT_MSG_ENABLE
);
1626 priv
->rx_ring
.frag_size
= fe_max_frag_size(ETH_DATA_LEN
);
1627 priv
->rx_ring
.rx_buf_size
= fe_max_buf_size(priv
->rx_ring
.frag_size
);
1628 priv
->tx_ring
.tx_ring_size
= NUM_DMA_DESC
;
1629 priv
->rx_ring
.rx_ring_size
= NUM_DMA_DESC
;
1630 INIT_WORK(&priv
->pending_work
, fe_pending_work
);
1633 if (priv
->flags
& FE_FLAG_NAPI_WEIGHT
) {
1635 priv
->tx_ring
.tx_ring_size
*= 4;
1636 priv
->rx_ring
.rx_ring_size
*= 4;
1638 netif_napi_add_weight(netdev
, &priv
->rx_napi
, fe_poll
, napi_weight
);
1639 fe_set_ethtool_ops(netdev
);
1641 err
= register_netdev(netdev
);
1643 dev_err(&pdev
->dev
, "error bringing up device\n");
1647 platform_set_drvdata(pdev
, netdev
);
1649 netif_info(priv
, probe
, netdev
, "mediatek frame engine at 0x%08lx, irq %d\n",
1650 netdev
->base_addr
, netdev
->irq
);
1655 free_netdev(netdev
);
1657 devm_iounmap(&pdev
->dev
, fe_base
);
1662 static int fe_remove(struct platform_device
*pdev
)
1664 struct net_device
*dev
= platform_get_drvdata(pdev
);
1665 struct fe_priv
*priv
= netdev_priv(dev
);
1667 netif_napi_del(&priv
->rx_napi
);
1668 kfree(priv
->hw_stats
);
1670 cancel_work_sync(&priv
->pending_work
);
1672 unregister_netdev(dev
);
1674 platform_set_drvdata(pdev
, NULL
);
1679 static struct platform_driver fe_driver
= {
1681 .remove
= fe_remove
,
1683 .name
= "mtk_soc_eth",
1684 .owner
= THIS_MODULE
,
1685 .of_match_table
= of_fe_match
,
1689 module_platform_driver(fe_driver
);
1691 MODULE_LICENSE("GPL");
1692 MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
1693 MODULE_DESCRIPTION("Ethernet driver for Ralink SoC");
1694 MODULE_VERSION(MTK_FE_DRV_VERSION
);