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ramips: improve tx clean up and add fe_tx_ring struct
[openwrt/openwrt.git] / target / linux / ramips / files / drivers / net / ethernet / ralink / ralink_soc_eth.c
1 /*
2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License as published by
4 * the Free Software Foundation; version 2 of the License
5 *
6 * This program is distributed in the hope that it will be useful,
7 * but WITHOUT ANY WARRANTY; without even the implied warranty of
8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9 * GNU General Public License for more details.
10 *
11 * You should have received a copy of the GNU General Public License
12 * along with this program; if not, write to the Free Software
13 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
14 *
15 * Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
16 */
17
18 #include <linux/module.h>
19 #include <linux/kernel.h>
20 #include <linux/types.h>
21 #include <linux/dma-mapping.h>
22 #include <linux/init.h>
23 #include <linux/skbuff.h>
24 #include <linux/etherdevice.h>
25 #include <linux/ethtool.h>
26 #include <linux/platform_device.h>
27 #include <linux/of_device.h>
28 #include <linux/clk.h>
29 #include <linux/of_net.h>
30 #include <linux/of_mdio.h>
31 #include <linux/if_vlan.h>
32 #include <linux/reset.h>
33 #include <linux/tcp.h>
34 #include <linux/io.h>
35
36 #include <asm/mach-ralink/ralink_regs.h>
37
38 #include "ralink_soc_eth.h"
39 #include "esw_rt3052.h"
40 #include "mdio.h"
41 #include "ralink_ethtool.h"
42
43 #define MAX_RX_LENGTH 1536
44 #define FE_RX_HLEN (NET_SKB_PAD + VLAN_ETH_HLEN + VLAN_HLEN + \
45 + NET_IP_ALIGN + ETH_FCS_LEN)
46 #define DMA_DUMMY_DESC 0xffffffff
47 #define FE_DEFAULT_MSG_ENABLE \
48 (NETIF_MSG_DRV | \
49 NETIF_MSG_PROBE | \
50 NETIF_MSG_LINK | \
51 NETIF_MSG_TIMER | \
52 NETIF_MSG_IFDOWN | \
53 NETIF_MSG_IFUP | \
54 NETIF_MSG_RX_ERR | \
55 NETIF_MSG_TX_ERR)
56
57 #define TX_DMA_DESP2_DEF (TX_DMA_LS0 | TX_DMA_DONE)
58 #define TX_DMA_DESP4_DEF (TX_DMA_QN(3) | TX_DMA_PN(1))
59 #define NEXT_TX_DESP_IDX(X) (((X) + 1) & (ring->tx_ring_size - 1))
60 #define NEXT_RX_DESP_IDX(X) (((X) + 1) & (priv->rx_ring_size - 1))
61
62 #define SYSC_REG_RSTCTRL 0x34
63
64 static int fe_msg_level = -1;
65 module_param_named(msg_level, fe_msg_level, int, 0);
66 MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)");
67
68 static const u16 fe_reg_table_default[FE_REG_COUNT] = {
69 [FE_REG_PDMA_GLO_CFG] = FE_PDMA_GLO_CFG,
70 [FE_REG_PDMA_RST_CFG] = FE_PDMA_RST_CFG,
71 [FE_REG_DLY_INT_CFG] = FE_DLY_INT_CFG,
72 [FE_REG_TX_BASE_PTR0] = FE_TX_BASE_PTR0,
73 [FE_REG_TX_MAX_CNT0] = FE_TX_MAX_CNT0,
74 [FE_REG_TX_CTX_IDX0] = FE_TX_CTX_IDX0,
75 [FE_REG_TX_DTX_IDX0] = FE_TX_DTX_IDX0,
76 [FE_REG_RX_BASE_PTR0] = FE_RX_BASE_PTR0,
77 [FE_REG_RX_MAX_CNT0] = FE_RX_MAX_CNT0,
78 [FE_REG_RX_CALC_IDX0] = FE_RX_CALC_IDX0,
79 [FE_REG_RX_DRX_IDX0] = FE_RX_DRX_IDX0,
80 [FE_REG_FE_INT_ENABLE] = FE_FE_INT_ENABLE,
81 [FE_REG_FE_INT_STATUS] = FE_FE_INT_STATUS,
82 [FE_REG_FE_DMA_VID_BASE] = FE_DMA_VID0,
83 [FE_REG_FE_COUNTER_BASE] = FE_GDMA1_TX_GBCNT,
84 [FE_REG_FE_RST_GL] = FE_FE_RST_GL,
85 };
86
87 static const u16 *fe_reg_table = fe_reg_table_default;
88
89 struct fe_work_t {
90 int bitnr;
91 void (*action)(struct fe_priv *);
92 };
93
94 static void __iomem *fe_base = 0;
95
96 void fe_w32(u32 val, unsigned reg)
97 {
98 __raw_writel(val, fe_base + reg);
99 }
100
101 u32 fe_r32(unsigned reg)
102 {
103 return __raw_readl(fe_base + reg);
104 }
105
106 void fe_reg_w32(u32 val, enum fe_reg reg)
107 {
108 fe_w32(val, fe_reg_table[reg]);
109 }
110
111 u32 fe_reg_r32(enum fe_reg reg)
112 {
113 return fe_r32(fe_reg_table[reg]);
114 }
115
116 void fe_reset(u32 reset_bits)
117 {
118 u32 t;
119
120 t = rt_sysc_r32(SYSC_REG_RSTCTRL);
121 t |= reset_bits;
122 rt_sysc_w32(t , SYSC_REG_RSTCTRL);
123 udelay(10);
124
125 t &= ~reset_bits;
126 rt_sysc_w32(t, SYSC_REG_RSTCTRL);
127 udelay(10);
128 }
129
130 static inline void fe_int_disable(u32 mask)
131 {
132 fe_reg_w32(fe_reg_r32(FE_REG_FE_INT_ENABLE) & ~mask,
133 FE_REG_FE_INT_ENABLE);
134 /* flush write */
135 fe_reg_r32(FE_REG_FE_INT_ENABLE);
136 }
137
138 static inline void fe_int_enable(u32 mask)
139 {
140 fe_reg_w32(fe_reg_r32(FE_REG_FE_INT_ENABLE) | mask,
141 FE_REG_FE_INT_ENABLE);
142 /* flush write */
143 fe_reg_r32(FE_REG_FE_INT_ENABLE);
144 }
145
146 static inline void fe_hw_set_macaddr(struct fe_priv *priv, unsigned char *mac)
147 {
148 unsigned long flags;
149
150 spin_lock_irqsave(&priv->page_lock, flags);
151 fe_w32((mac[0] << 8) | mac[1], FE_GDMA1_MAC_ADRH);
152 fe_w32((mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5],
153 FE_GDMA1_MAC_ADRL);
154 spin_unlock_irqrestore(&priv->page_lock, flags);
155 }
156
157 static int fe_set_mac_address(struct net_device *dev, void *p)
158 {
159 int ret = eth_mac_addr(dev, p);
160
161 if (!ret) {
162 struct fe_priv *priv = netdev_priv(dev);
163
164 if (priv->soc->set_mac)
165 priv->soc->set_mac(priv, dev->dev_addr);
166 else
167 fe_hw_set_macaddr(priv, p);
168 }
169
170 return ret;
171 }
172
173 static inline int fe_max_frag_size(int mtu)
174 {
175 return SKB_DATA_ALIGN(FE_RX_HLEN + mtu) +
176 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
177 }
178
179 static inline int fe_max_buf_size(int frag_size)
180 {
181 return frag_size - NET_SKB_PAD - NET_IP_ALIGN -
182 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
183 }
184
185 static inline void fe_get_rxd(struct fe_rx_dma *rxd, struct fe_rx_dma *dma_rxd)
186 {
187 rxd->rxd1 = dma_rxd->rxd1;
188 rxd->rxd2 = dma_rxd->rxd2;
189 rxd->rxd3 = dma_rxd->rxd3;
190 rxd->rxd4 = dma_rxd->rxd4;
191 }
192
193 static inline void fe_set_txd(struct fe_tx_dma *txd, struct fe_tx_dma *dma_txd)
194 {
195 dma_txd->txd1 = txd->txd1;
196 dma_txd->txd3 = txd->txd3;
197 dma_txd->txd4 = txd->txd4;
198 /* clean dma done flag last */
199 dma_txd->txd2 = txd->txd2;
200 }
201
202 static void fe_clean_rx(struct fe_priv *priv)
203 {
204 int i;
205
206 if (priv->rx_data) {
207 for (i = 0; i < priv->rx_ring_size; i++)
208 if (priv->rx_data[i]) {
209 if (priv->rx_dma && priv->rx_dma[i].rxd1)
210 dma_unmap_single(&priv->netdev->dev,
211 priv->rx_dma[i].rxd1,
212 priv->rx_buf_size,
213 DMA_FROM_DEVICE);
214 put_page(virt_to_head_page(priv->rx_data[i]));
215 }
216
217 kfree(priv->rx_data);
218 priv->rx_data = NULL;
219 }
220
221 if (priv->rx_dma) {
222 dma_free_coherent(&priv->netdev->dev,
223 priv->rx_ring_size * sizeof(*priv->rx_dma),
224 priv->rx_dma,
225 priv->rx_phys);
226 priv->rx_dma = NULL;
227 }
228 }
229
230 static int fe_alloc_rx(struct fe_priv *priv)
231 {
232 struct net_device *netdev = priv->netdev;
233 int i, pad;
234
235 priv->rx_data = kcalloc(priv->rx_ring_size, sizeof(*priv->rx_data),
236 GFP_KERNEL);
237 if (!priv->rx_data)
238 goto no_rx_mem;
239
240 for (i = 0; i < priv->rx_ring_size; i++) {
241 priv->rx_data[i] = netdev_alloc_frag(priv->frag_size);
242 if (!priv->rx_data[i])
243 goto no_rx_mem;
244 }
245
246 priv->rx_dma = dma_alloc_coherent(&netdev->dev,
247 priv->rx_ring_size * sizeof(*priv->rx_dma),
248 &priv->rx_phys,
249 GFP_ATOMIC | __GFP_ZERO);
250 if (!priv->rx_dma)
251 goto no_rx_mem;
252
253 if (priv->flags & FE_FLAG_RX_2B_OFFSET)
254 pad = 0;
255 else
256 pad = NET_IP_ALIGN;
257 for (i = 0; i < priv->rx_ring_size; i++) {
258 dma_addr_t dma_addr = dma_map_single(&netdev->dev,
259 priv->rx_data[i] + NET_SKB_PAD + pad,
260 priv->rx_buf_size,
261 DMA_FROM_DEVICE);
262 if (unlikely(dma_mapping_error(&netdev->dev, dma_addr)))
263 goto no_rx_mem;
264 priv->rx_dma[i].rxd1 = (unsigned int) dma_addr;
265
266 if (priv->flags & FE_FLAG_RX_SG_DMA)
267 priv->rx_dma[i].rxd2 = RX_DMA_PLEN0(priv->rx_buf_size);
268 else
269 priv->rx_dma[i].rxd2 = RX_DMA_LSO;
270 }
271 wmb();
272
273 fe_reg_w32(priv->rx_phys, FE_REG_RX_BASE_PTR0);
274 fe_reg_w32(priv->rx_ring_size, FE_REG_RX_MAX_CNT0);
275 fe_reg_w32((priv->rx_ring_size - 1), FE_REG_RX_CALC_IDX0);
276 fe_reg_w32(FE_PST_DRX_IDX0, FE_REG_PDMA_RST_CFG);
277
278 return 0;
279
280 no_rx_mem:
281 return -ENOMEM;
282 }
283
284 static void fe_txd_unmap(struct device *dev, struct fe_tx_buf *tx_buf)
285 {
286 if (tx_buf->flags & FE_TX_FLAGS_SINGLE0) {
287 dma_unmap_single(dev,
288 dma_unmap_addr(tx_buf, dma_addr0),
289 dma_unmap_len(tx_buf, dma_len0),
290 DMA_TO_DEVICE);
291 } else if (tx_buf->flags & FE_TX_FLAGS_PAGE0) {
292 dma_unmap_page(dev,
293 dma_unmap_addr(tx_buf, dma_addr0),
294 dma_unmap_len(tx_buf, dma_len0),
295 DMA_TO_DEVICE);
296 }
297 if (tx_buf->flags & FE_TX_FLAGS_PAGE1)
298 dma_unmap_page(dev,
299 dma_unmap_addr(tx_buf, dma_addr1),
300 dma_unmap_len(tx_buf, dma_len1),
301 DMA_TO_DEVICE);
302
303 tx_buf->flags = 0;
304 if (tx_buf->skb && (tx_buf->skb != (struct sk_buff *) DMA_DUMMY_DESC)) {
305 dev_kfree_skb_any(tx_buf->skb);
306 }
307 tx_buf->skb = NULL;
308 }
309
310 static void fe_clean_tx(struct fe_priv *priv)
311 {
312 int i;
313 struct device *dev = &priv->netdev->dev;
314 struct fe_tx_ring *ring = &priv->tx_ring;
315
316 if (ring->tx_buf) {
317 for (i = 0; i < ring->tx_ring_size; i++)
318 fe_txd_unmap(dev, &ring->tx_buf[i]);
319 kfree(ring->tx_buf);
320 ring->tx_buf = NULL;
321 }
322
323 if (ring->tx_dma) {
324 dma_free_coherent(dev,
325 ring->tx_ring_size * sizeof(*ring->tx_dma),
326 ring->tx_dma,
327 ring->tx_phys);
328 ring->tx_dma = NULL;
329 }
330
331 netdev_reset_queue(priv->netdev);
332 }
333
334 static int fe_alloc_tx(struct fe_priv *priv)
335 {
336 int i;
337 struct fe_tx_ring *ring = &priv->tx_ring;
338
339 ring->tx_free_idx = 0;
340
341 ring->tx_buf = kcalloc(ring->tx_ring_size, sizeof(*ring->tx_buf),
342 GFP_KERNEL);
343 if (!ring->tx_buf)
344 goto no_tx_mem;
345
346 ring->tx_dma = dma_alloc_coherent(&priv->netdev->dev,
347 ring->tx_ring_size * sizeof(*ring->tx_dma),
348 &ring->tx_phys,
349 GFP_ATOMIC | __GFP_ZERO);
350 if (!ring->tx_dma)
351 goto no_tx_mem;
352
353 for (i = 0; i < ring->tx_ring_size; i++) {
354 if (priv->soc->tx_dma) {
355 priv->soc->tx_dma(&ring->tx_dma[i]);
356 }
357 ring->tx_dma[i].txd2 = TX_DMA_DESP2_DEF;
358 }
359 wmb();
360
361 fe_reg_w32(ring->tx_phys, FE_REG_TX_BASE_PTR0);
362 fe_reg_w32(ring->tx_ring_size, FE_REG_TX_MAX_CNT0);
363 fe_reg_w32(0, FE_REG_TX_CTX_IDX0);
364 fe_reg_w32(FE_PST_DTX_IDX0, FE_REG_PDMA_RST_CFG);
365
366 return 0;
367
368 no_tx_mem:
369 return -ENOMEM;
370 }
371
372 static int fe_init_dma(struct fe_priv *priv)
373 {
374 int err;
375
376 err = fe_alloc_tx(priv);
377 if (err)
378 return err;
379
380 err = fe_alloc_rx(priv);
381 if (err)
382 return err;
383
384 return 0;
385 }
386
387 static void fe_free_dma(struct fe_priv *priv)
388 {
389 fe_clean_tx(priv);
390 fe_clean_rx(priv);
391 }
392
393 void fe_stats_update(struct fe_priv *priv)
394 {
395 struct fe_hw_stats *hwstats = priv->hw_stats;
396 unsigned int base = fe_reg_table[FE_REG_FE_COUNTER_BASE];
397 u64 stats;
398
399 u64_stats_update_begin(&hwstats->syncp);
400
401 if (IS_ENABLED(CONFIG_SOC_MT7621)) {
402 hwstats->rx_bytes += fe_r32(base);
403 stats = fe_r32(base + 0x04);
404 if (stats)
405 hwstats->rx_bytes += (stats << 32);
406 hwstats->rx_packets += fe_r32(base + 0x08);
407 hwstats->rx_overflow += fe_r32(base + 0x10);
408 hwstats->rx_fcs_errors += fe_r32(base + 0x14);
409 hwstats->rx_short_errors += fe_r32(base + 0x18);
410 hwstats->rx_long_errors += fe_r32(base + 0x1c);
411 hwstats->rx_checksum_errors += fe_r32(base + 0x20);
412 hwstats->rx_flow_control_packets += fe_r32(base + 0x24);
413 hwstats->tx_skip += fe_r32(base + 0x28);
414 hwstats->tx_collisions += fe_r32(base + 0x2c);
415 hwstats->tx_bytes += fe_r32(base + 0x30);
416 stats = fe_r32(base + 0x34);
417 if (stats)
418 hwstats->tx_bytes += (stats << 32);
419 hwstats->tx_packets += fe_r32(base + 0x38);
420 } else {
421 hwstats->tx_bytes += fe_r32(base);
422 hwstats->tx_packets += fe_r32(base + 0x04);
423 hwstats->tx_skip += fe_r32(base + 0x08);
424 hwstats->tx_collisions += fe_r32(base + 0x0c);
425 hwstats->rx_bytes += fe_r32(base + 0x20);
426 hwstats->rx_packets += fe_r32(base + 0x24);
427 hwstats->rx_overflow += fe_r32(base + 0x28);
428 hwstats->rx_fcs_errors += fe_r32(base + 0x2c);
429 hwstats->rx_short_errors += fe_r32(base + 0x30);
430 hwstats->rx_long_errors += fe_r32(base + 0x34);
431 hwstats->rx_checksum_errors += fe_r32(base + 0x38);
432 hwstats->rx_flow_control_packets += fe_r32(base + 0x3c);
433 }
434
435 u64_stats_update_end(&hwstats->syncp);
436 }
437
438 static struct rtnl_link_stats64 *fe_get_stats64(struct net_device *dev,
439 struct rtnl_link_stats64 *storage)
440 {
441 struct fe_priv *priv = netdev_priv(dev);
442 struct fe_hw_stats *hwstats = priv->hw_stats;
443 unsigned int base = fe_reg_table[FE_REG_FE_COUNTER_BASE];
444 unsigned int start;
445
446 if (!base) {
447 netdev_stats_to_stats64(storage, &dev->stats);
448 return storage;
449 }
450
451 if (netif_running(dev) && netif_device_present(dev)) {
452 if (spin_trylock(&hwstats->stats_lock)) {
453 fe_stats_update(priv);
454 spin_unlock(&hwstats->stats_lock);
455 }
456 }
457
458 do {
459 start = u64_stats_fetch_begin_irq(&hwstats->syncp);
460 storage->rx_packets = hwstats->rx_packets;
461 storage->tx_packets = hwstats->tx_packets;
462 storage->rx_bytes = hwstats->rx_bytes;
463 storage->tx_bytes = hwstats->tx_bytes;
464 storage->collisions = hwstats->tx_collisions;
465 storage->rx_length_errors = hwstats->rx_short_errors +
466 hwstats->rx_long_errors;
467 storage->rx_over_errors = hwstats->rx_overflow;
468 storage->rx_crc_errors = hwstats->rx_fcs_errors;
469 storage->rx_errors = hwstats->rx_checksum_errors;
470 storage->tx_aborted_errors = hwstats->tx_skip;
471 } while (u64_stats_fetch_retry_irq(&hwstats->syncp, start));
472
473 storage->tx_errors = priv->netdev->stats.tx_errors;
474 storage->rx_dropped = priv->netdev->stats.rx_dropped;
475 storage->tx_dropped = priv->netdev->stats.tx_dropped;
476
477 return storage;
478 }
479
480 static int fe_vlan_rx_add_vid(struct net_device *dev,
481 __be16 proto, u16 vid)
482 {
483 struct fe_priv *priv = netdev_priv(dev);
484 u32 idx = (vid & 0xf);
485 u32 vlan_cfg;
486
487 if (!((fe_reg_table[FE_REG_FE_DMA_VID_BASE]) &&
488 (dev->features & NETIF_F_HW_VLAN_CTAG_TX)))
489 return 0;
490
491 if (test_bit(idx, &priv->vlan_map)) {
492 netdev_warn(dev, "disable tx vlan offload\n");
493 dev->wanted_features &= ~NETIF_F_HW_VLAN_CTAG_TX;
494 netdev_update_features(dev);
495 } else {
496 vlan_cfg = fe_r32(fe_reg_table[FE_REG_FE_DMA_VID_BASE] +
497 ((idx >> 1) << 2));
498 if (idx & 0x1) {
499 vlan_cfg &= 0xffff;
500 vlan_cfg |= (vid << 16);
501 } else {
502 vlan_cfg &= 0xffff0000;
503 vlan_cfg |= vid;
504 }
505 fe_w32(vlan_cfg, fe_reg_table[FE_REG_FE_DMA_VID_BASE] +
506 ((idx >> 1) << 2));
507 set_bit(idx, &priv->vlan_map);
508 }
509
510 return 0;
511 }
512
513 static int fe_vlan_rx_kill_vid(struct net_device *dev,
514 __be16 proto, u16 vid)
515 {
516 struct fe_priv *priv = netdev_priv(dev);
517 u32 idx = (vid & 0xf);
518
519 if (!((fe_reg_table[FE_REG_FE_DMA_VID_BASE]) &&
520 (dev->features & NETIF_F_HW_VLAN_CTAG_TX)))
521 return 0;
522
523 clear_bit(idx, &priv->vlan_map);
524
525 return 0;
526 }
527
528 static int fe_tx_map_dma(struct sk_buff *skb, struct net_device *dev,
529 int idx, int tx_num, struct fe_tx_ring *ring)
530 {
531 struct fe_priv *priv = netdev_priv(dev);
532 struct skb_frag_struct *frag;
533 struct fe_tx_dma txd, *ptxd;
534 struct fe_tx_buf *tx_buf;
535 dma_addr_t mapped_addr;
536 unsigned int nr_frags;
537 u32 def_txd4;
538 int i, j, k, frag_size, frag_map_size, offset;
539
540 tx_buf = &ring->tx_buf[idx];
541 memset(tx_buf, 0, sizeof(*tx_buf));
542 memset(&txd, 0, sizeof(txd));
543 nr_frags = skb_shinfo(skb)->nr_frags;
544
545 /* init tx descriptor */
546 if (priv->soc->tx_dma)
547 priv->soc->tx_dma(&txd);
548 else
549 txd.txd4 = TX_DMA_DESP4_DEF;
550 def_txd4 = txd.txd4;
551
552 /* TX Checksum offload */
553 if (skb->ip_summed == CHECKSUM_PARTIAL)
554 txd.txd4 |= TX_DMA_CHKSUM;
555
556 /* VLAN header offload */
557 if (vlan_tx_tag_present(skb)) {
558 if (IS_ENABLED(CONFIG_SOC_MT7621))
559 txd.txd4 |= TX_DMA_INS_VLAN_MT7621 | vlan_tx_tag_get(skb);
560 else
561 txd.txd4 |= TX_DMA_INS_VLAN |
562 ((vlan_tx_tag_get(skb) >> VLAN_PRIO_SHIFT) << 4) |
563 (vlan_tx_tag_get(skb) & 0xF);
564 }
565
566 /* TSO: fill MSS info in tcp checksum field */
567 if (skb_is_gso(skb)) {
568 if (skb_cow_head(skb, 0)) {
569 netif_warn(priv, tx_err, dev,
570 "GSO expand head fail.\n");
571 goto err_out;
572 }
573 if (skb_shinfo(skb)->gso_type &
574 (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) {
575 txd.txd4 |= TX_DMA_TSO;
576 tcp_hdr(skb)->check = htons(skb_shinfo(skb)->gso_size);
577 }
578 }
579
580 mapped_addr = dma_map_single(&dev->dev, skb->data,
581 skb_headlen(skb), DMA_TO_DEVICE);
582 if (unlikely(dma_mapping_error(&dev->dev, mapped_addr)))
583 goto err_out;
584 txd.txd1 = mapped_addr;
585 txd.txd2 = TX_DMA_PLEN0(skb_headlen(skb));
586
587 tx_buf->flags |= FE_TX_FLAGS_SINGLE0;
588 dma_unmap_addr_set(tx_buf, dma_addr0, mapped_addr);
589 dma_unmap_len_set(tx_buf, dma_len0, skb_headlen(skb));
590
591 /* TX SG offload */
592 j = idx;
593 k = 0;
594 for (i = 0; i < nr_frags; i++) {
595 offset = 0;
596 frag = &skb_shinfo(skb)->frags[i];
597 frag_size = skb_frag_size(frag);
598
599 while (frag_size > 0) {
600 frag_map_size = min(frag_size, TX_DMA_BUF_LEN);
601 mapped_addr = skb_frag_dma_map(&dev->dev, frag, offset,
602 frag_map_size, DMA_TO_DEVICE);
603 if (unlikely(dma_mapping_error(&dev->dev, mapped_addr)))
604 goto err_dma;
605
606 if (k & 0x1) {
607 j = NEXT_TX_DESP_IDX(j);
608 txd.txd1 = mapped_addr;
609 txd.txd2 = TX_DMA_PLEN0(frag_map_size);
610 txd.txd4 = def_txd4;
611
612 tx_buf = &ring->tx_buf[j];
613 memset(tx_buf, 0, sizeof(*tx_buf));
614
615 tx_buf->flags |= FE_TX_FLAGS_PAGE0;
616 dma_unmap_addr_set(tx_buf, dma_addr0, mapped_addr);
617 dma_unmap_len_set(tx_buf, dma_len0, frag_map_size);
618 } else {
619 txd.txd3 = mapped_addr;
620 txd.txd2 |= TX_DMA_PLEN1(frag_map_size);
621
622 tx_buf->skb = (struct sk_buff *) DMA_DUMMY_DESC;
623 tx_buf->flags |= FE_TX_FLAGS_PAGE1;
624 dma_unmap_addr_set(tx_buf, dma_addr1, mapped_addr);
625 dma_unmap_len_set(tx_buf, dma_len1, frag_map_size);
626
627 if (!((i == (nr_frags -1)) &&
628 (frag_map_size == frag_size))) {
629 fe_set_txd(&txd, &ring->tx_dma[j]);
630 memset(&txd, 0, sizeof(txd));
631 }
632 }
633 frag_size -= frag_map_size;
634 offset += frag_map_size;
635 k++;
636 }
637 }
638
639 /* set last segment */
640 if (k & 0x1)
641 txd.txd2 |= TX_DMA_LS1;
642 else
643 txd.txd2 |= TX_DMA_LS0;
644 fe_set_txd(&txd, &ring->tx_dma[j]);
645
646 /* store skb to cleanup */
647 tx_buf->skb = skb;
648
649 netdev_sent_queue(dev, skb->len);
650 skb_tx_timestamp(skb);
651
652 j = NEXT_TX_DESP_IDX(j);
653 wmb();
654 fe_reg_w32(j, FE_REG_TX_CTX_IDX0);
655
656 return 0;
657
658 err_dma:
659 j = idx;
660 for (i = 0; i < tx_num; i++) {
661 ptxd = &ring->tx_dma[j];
662 tx_buf = &ring->tx_buf[j];
663
664 /* unmap dma */
665 fe_txd_unmap(&dev->dev, tx_buf);
666
667 ptxd->txd2 = TX_DMA_DESP2_DEF;
668 j = NEXT_TX_DESP_IDX(j);
669 }
670 wmb();
671
672 err_out:
673 return -1;
674 }
675
676 static inline int fe_skb_padto(struct sk_buff *skb, struct fe_priv *priv) {
677 unsigned int len;
678 int ret;
679
680 ret = 0;
681 if (unlikely(skb->len < VLAN_ETH_ZLEN)) {
682 if ((priv->flags & FE_FLAG_PADDING_64B) &&
683 !(priv->flags & FE_FLAG_PADDING_BUG))
684 return ret;
685
686 if (vlan_tx_tag_present(skb))
687 len = ETH_ZLEN;
688 else if (skb->protocol == cpu_to_be16(ETH_P_8021Q))
689 len = VLAN_ETH_ZLEN;
690 else if(!(priv->flags & FE_FLAG_PADDING_64B))
691 len = ETH_ZLEN;
692 else
693 return ret;
694
695 if (skb->len < len) {
696 if ((ret = skb_pad(skb, len - skb->len)) < 0)
697 return ret;
698 skb->len = len;
699 skb_set_tail_pointer(skb, len);
700 }
701 }
702
703 return ret;
704 }
705
706 static inline u32 fe_empty_txd(struct fe_tx_ring *ring, u32 tx_fill_idx)
707 {
708 return (u32)(ring->tx_ring_size - ((tx_fill_idx - ring->tx_free_idx) &
709 (ring->tx_ring_size - 1)));
710 }
711
712 static inline int fe_cal_txd_req(struct sk_buff *skb)
713 {
714 int i, nfrags;
715 struct skb_frag_struct *frag;
716
717 nfrags = 1;
718 if (skb_is_gso(skb)) {
719 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
720 frag = &skb_shinfo(skb)->frags[i];
721 nfrags += DIV_ROUND_UP(frag->size, TX_DMA_BUF_LEN);
722 }
723 } else {
724 nfrags += skb_shinfo(skb)->nr_frags;
725 }
726
727 return DIV_ROUND_UP(nfrags, 2);
728 }
729
730 static int fe_start_xmit(struct sk_buff *skb, struct net_device *dev)
731 {
732 struct fe_priv *priv = netdev_priv(dev);
733 struct fe_tx_ring *ring = &priv->tx_ring;
734 struct net_device_stats *stats = &dev->stats;
735 u32 tx;
736 int tx_num;
737 int len = skb->len;
738
739 if (fe_skb_padto(skb, priv)) {
740 netif_warn(priv, tx_err, dev, "tx padding failed!\n");
741 return NETDEV_TX_OK;
742 }
743
744 tx_num = fe_cal_txd_req(skb);
745 tx = fe_reg_r32(FE_REG_TX_CTX_IDX0);
746 if (unlikely(fe_empty_txd(ring, tx) <= tx_num))
747 {
748 netif_stop_queue(dev);
749 netif_err(priv, tx_queued,dev,
750 "Tx Ring full when queue awake!\n");
751 return NETDEV_TX_BUSY;
752 }
753
754 if (fe_tx_map_dma(skb, dev, tx, tx_num, ring) < 0) {
755 stats->tx_dropped++;
756 } else {
757 stats->tx_packets++;
758 stats->tx_bytes += len;
759 }
760
761 return NETDEV_TX_OK;
762 }
763
764 static inline void fe_rx_vlan(struct sk_buff *skb)
765 {
766 struct ethhdr *ehdr;
767 u16 vlanid;
768
769 if (!__vlan_get_tag(skb, &vlanid)) {
770 /* pop the vlan tag */
771 ehdr = (struct ethhdr *)skb->data;
772 memmove(skb->data + VLAN_HLEN, ehdr, ETH_ALEN * 2);
773 skb_pull(skb, VLAN_HLEN);
774 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlanid);
775 }
776 }
777
778 static int fe_poll_rx(struct napi_struct *napi, int budget,
779 struct fe_priv *priv, u32 rx_intr)
780 {
781 struct net_device *netdev = priv->netdev;
782 struct net_device_stats *stats = &netdev->stats;
783 struct fe_soc_data *soc = priv->soc;
784 u32 checksum_bit;
785 int idx = fe_reg_r32(FE_REG_RX_CALC_IDX0);
786 struct sk_buff *skb;
787 u8 *data, *new_data;
788 struct fe_rx_dma *rxd, trxd;
789 int done = 0, pad;
790 bool rx_vlan = netdev->features & NETIF_F_HW_VLAN_CTAG_RX;
791
792 if (netdev->features & NETIF_F_RXCSUM)
793 checksum_bit = soc->checksum_bit;
794 else
795 checksum_bit = 0;
796
797 if (priv->flags & FE_FLAG_RX_2B_OFFSET)
798 pad = 0;
799 else
800 pad = NET_IP_ALIGN;
801
802 while (done < budget) {
803 unsigned int pktlen;
804 dma_addr_t dma_addr;
805 idx = NEXT_RX_DESP_IDX(idx);
806 rxd = &priv->rx_dma[idx];
807 data = priv->rx_data[idx];
808
809 fe_get_rxd(&trxd, rxd);
810 if (!(trxd.rxd2 & RX_DMA_DONE))
811 break;
812
813 /* alloc new buffer */
814 new_data = netdev_alloc_frag(priv->frag_size);
815 if (unlikely(!new_data)) {
816 stats->rx_dropped++;
817 goto release_desc;
818 }
819 dma_addr = dma_map_single(&netdev->dev,
820 new_data + NET_SKB_PAD + pad,
821 priv->rx_buf_size,
822 DMA_FROM_DEVICE);
823 if (unlikely(dma_mapping_error(&netdev->dev, dma_addr))) {
824 put_page(virt_to_head_page(new_data));
825 goto release_desc;
826 }
827
828 /* receive data */
829 skb = build_skb(data, priv->frag_size);
830 if (unlikely(!skb)) {
831 put_page(virt_to_head_page(new_data));
832 goto release_desc;
833 }
834 skb_reserve(skb, NET_SKB_PAD + NET_IP_ALIGN);
835
836 dma_unmap_single(&netdev->dev, trxd.rxd1,
837 priv->rx_buf_size, DMA_FROM_DEVICE);
838 pktlen = RX_DMA_PLEN0(trxd.rxd2);
839 skb->dev = netdev;
840 skb_put(skb, pktlen);
841 if (trxd.rxd4 & checksum_bit) {
842 skb->ip_summed = CHECKSUM_UNNECESSARY;
843 } else {
844 skb_checksum_none_assert(skb);
845 }
846 if (rx_vlan)
847 fe_rx_vlan(skb);
848 skb->protocol = eth_type_trans(skb, netdev);
849
850 stats->rx_packets++;
851 stats->rx_bytes += pktlen;
852
853 napi_gro_receive(napi, skb);
854
855 priv->rx_data[idx] = new_data;
856 rxd->rxd1 = (unsigned int) dma_addr;
857
858 release_desc:
859 if (priv->flags & FE_FLAG_RX_SG_DMA)
860 rxd->rxd2 = RX_DMA_PLEN0(priv->rx_buf_size);
861 else
862 rxd->rxd2 = RX_DMA_LSO;
863
864 wmb();
865 fe_reg_w32(idx, FE_REG_RX_CALC_IDX0);
866 done++;
867 }
868
869 if (done < budget)
870 fe_reg_w32(rx_intr, FE_REG_FE_INT_STATUS);
871
872 return done;
873 }
874
875 static int fe_poll_tx(struct fe_priv *priv, int budget, u32 tx_intr,
876 int *tx_again)
877 {
878 struct net_device *netdev = priv->netdev;
879 struct device *dev = &netdev->dev;
880 unsigned int bytes_compl = 0;
881 struct sk_buff *skb;
882 struct fe_tx_buf *tx_buf;
883 int done = 0;
884 u32 idx, hwidx;
885 struct fe_tx_ring *ring = &priv->tx_ring;
886
887 idx = ring->tx_free_idx;
888 hwidx = fe_reg_r32(FE_REG_TX_DTX_IDX0);
889
890 while ((idx != hwidx) && budget) {
891 tx_buf = &ring->tx_buf[idx];
892 skb = tx_buf->skb;
893
894 if (!skb)
895 break;
896
897 if (skb != (struct sk_buff *) DMA_DUMMY_DESC) {
898 bytes_compl += skb->len;
899 done++;
900 budget--;
901 }
902 fe_txd_unmap(dev, tx_buf);
903 idx = NEXT_TX_DESP_IDX(idx);
904 }
905 ring->tx_free_idx = idx;
906
907 if (idx == hwidx) {
908 /* read hw index again make sure no new tx packet */
909 hwidx = fe_reg_r32(FE_REG_TX_DTX_IDX0);
910 if (idx == hwidx)
911 fe_reg_w32(tx_intr, FE_REG_FE_INT_STATUS);
912 else
913 *tx_again = 1;
914 } else
915 *tx_again = 1;
916
917 if (done) {
918 netdev_completed_queue(netdev, done, bytes_compl);
919 if (unlikely(netif_queue_stopped(netdev) &&
920 netif_carrier_ok(netdev))) {
921 netif_wake_queue(netdev);
922 }
923 }
924
925 return done;
926 }
927
928 static int fe_poll(struct napi_struct *napi, int budget)
929 {
930 struct fe_priv *priv = container_of(napi, struct fe_priv, rx_napi);
931 struct fe_hw_stats *hwstat = priv->hw_stats;
932 int tx_done, rx_done, tx_again;
933 u32 status, fe_status, status_reg, mask;
934 u32 tx_intr, rx_intr, status_intr;
935
936 fe_status = status = fe_reg_r32(FE_REG_FE_INT_STATUS);
937 tx_intr = priv->soc->tx_int;
938 rx_intr = priv->soc->rx_int;
939 status_intr = priv->soc->status_int;
940 tx_done = rx_done = tx_again = 0;
941
942 if (fe_reg_table[FE_REG_FE_INT_STATUS2]) {
943 fe_status = fe_reg_r32(FE_REG_FE_INT_STATUS2);
944 status_reg = FE_REG_FE_INT_STATUS2;
945 } else
946 status_reg = FE_REG_FE_INT_STATUS;
947
948 if (status & tx_intr)
949 tx_done = fe_poll_tx(priv, budget, tx_intr, &tx_again);
950
951 if (status & rx_intr)
952 rx_done = fe_poll_rx(napi, budget, priv, rx_intr);
953
954 if (unlikely(fe_status & status_intr)) {
955 if (hwstat && spin_trylock(&hwstat->stats_lock)) {
956 fe_stats_update(priv);
957 spin_unlock(&hwstat->stats_lock);
958 }
959 fe_reg_w32(status_intr, status_reg);
960 }
961
962 if (unlikely(netif_msg_intr(priv))) {
963 mask = fe_reg_r32(FE_REG_FE_INT_ENABLE);
964 netdev_info(priv->netdev,
965 "done tx %d, rx %d, intr 0x%08x/0x%x\n",
966 tx_done, rx_done, status, mask);
967 }
968
969 if (!tx_again && (rx_done < budget)) {
970 status = fe_reg_r32(FE_REG_FE_INT_STATUS);
971 if (status & (tx_intr | rx_intr ))
972 goto poll_again;
973
974 napi_complete(napi);
975 fe_int_enable(tx_intr | rx_intr);
976 }
977
978 poll_again:
979 return rx_done;
980 }
981
982 static void fe_tx_timeout(struct net_device *dev)
983 {
984 struct fe_priv *priv = netdev_priv(dev);
985 struct fe_tx_ring *ring = &priv->tx_ring;
986
987 priv->netdev->stats.tx_errors++;
988 netif_err(priv, tx_err, dev,
989 "transmit timed out\n");
990 netif_info(priv, drv, dev, "dma_cfg:%08x\n",
991 fe_reg_r32(FE_REG_PDMA_GLO_CFG));
992 netif_info(priv, drv, dev, "tx_ring=%d, " \
993 "base=%08x, max=%u, ctx=%u, dtx=%u, fdx=%d\n", 0,
994 fe_reg_r32(FE_REG_TX_BASE_PTR0),
995 fe_reg_r32(FE_REG_TX_MAX_CNT0),
996 fe_reg_r32(FE_REG_TX_CTX_IDX0),
997 fe_reg_r32(FE_REG_TX_DTX_IDX0),
998 ring->tx_free_idx
999 );
1000 netif_info(priv, drv, dev, "rx_ring=%d, " \
1001 "base=%08x, max=%u, calc=%u, drx=%u\n", 0,
1002 fe_reg_r32(FE_REG_RX_BASE_PTR0),
1003 fe_reg_r32(FE_REG_RX_MAX_CNT0),
1004 fe_reg_r32(FE_REG_RX_CALC_IDX0),
1005 fe_reg_r32(FE_REG_RX_DRX_IDX0)
1006 );
1007
1008 if (!test_and_set_bit(FE_FLAG_RESET_PENDING, priv->pending_flags))
1009 schedule_work(&priv->pending_work);
1010 }
1011
1012 static irqreturn_t fe_handle_irq(int irq, void *dev)
1013 {
1014 struct fe_priv *priv = netdev_priv(dev);
1015 u32 status, int_mask;
1016
1017 status = fe_reg_r32(FE_REG_FE_INT_STATUS);
1018
1019 if (unlikely(!status))
1020 return IRQ_NONE;
1021
1022 int_mask = (priv->soc->rx_int | priv->soc->tx_int);
1023 if (likely(status & int_mask)) {
1024 if (likely(napi_schedule_prep(&priv->rx_napi))) {
1025 fe_int_disable(int_mask);
1026 __napi_schedule(&priv->rx_napi);
1027 }
1028 } else {
1029 fe_reg_w32(status, FE_REG_FE_INT_STATUS);
1030 }
1031
1032 return IRQ_HANDLED;
1033 }
1034
1035 #ifdef CONFIG_NET_POLL_CONTROLLER
1036 static void fe_poll_controller(struct net_device *dev)
1037 {
1038 struct fe_priv *priv = netdev_priv(dev);
1039 u32 int_mask = priv->soc->tx_int | priv->soc->rx_int;
1040
1041 fe_int_disable(int_mask);
1042 fe_handle_irq(dev->irq, dev);
1043 fe_int_enable(int_mask);
1044 }
1045 #endif
1046
1047 int fe_set_clock_cycle(struct fe_priv *priv)
1048 {
1049 unsigned long sysclk = priv->sysclk;
1050
1051 if (!sysclk) {
1052 return -EINVAL;
1053 }
1054
1055 sysclk /= FE_US_CYC_CNT_DIVISOR;
1056 sysclk <<= FE_US_CYC_CNT_SHIFT;
1057
1058 fe_w32((fe_r32(FE_FE_GLO_CFG) &
1059 ~(FE_US_CYC_CNT_MASK << FE_US_CYC_CNT_SHIFT)) |
1060 sysclk,
1061 FE_FE_GLO_CFG);
1062 return 0;
1063 }
1064
1065 void fe_fwd_config(struct fe_priv *priv)
1066 {
1067 u32 fwd_cfg;
1068
1069 fwd_cfg = fe_r32(FE_GDMA1_FWD_CFG);
1070
1071 /* disable jumbo frame */
1072 if (priv->flags & FE_FLAG_JUMBO_FRAME)
1073 fwd_cfg &= ~FE_GDM1_JMB_EN;
1074
1075 /* set unicast/multicast/broadcast frame to cpu */
1076 fwd_cfg &= ~0xffff;
1077
1078 fe_w32(fwd_cfg, FE_GDMA1_FWD_CFG);
1079 }
1080
1081 static void fe_rxcsum_config(bool enable)
1082 {
1083 if (enable)
1084 fe_w32(fe_r32(FE_GDMA1_FWD_CFG) | (FE_GDM1_ICS_EN |
1085 FE_GDM1_TCS_EN | FE_GDM1_UCS_EN),
1086 FE_GDMA1_FWD_CFG);
1087 else
1088 fe_w32(fe_r32(FE_GDMA1_FWD_CFG) & ~(FE_GDM1_ICS_EN |
1089 FE_GDM1_TCS_EN | FE_GDM1_UCS_EN),
1090 FE_GDMA1_FWD_CFG);
1091 }
1092
1093 static void fe_txcsum_config(bool enable)
1094 {
1095 if (enable)
1096 fe_w32(fe_r32(FE_CDMA_CSG_CFG) | (FE_ICS_GEN_EN |
1097 FE_TCS_GEN_EN | FE_UCS_GEN_EN),
1098 FE_CDMA_CSG_CFG);
1099 else
1100 fe_w32(fe_r32(FE_CDMA_CSG_CFG) & ~(FE_ICS_GEN_EN |
1101 FE_TCS_GEN_EN | FE_UCS_GEN_EN),
1102 FE_CDMA_CSG_CFG);
1103 }
1104
1105 void fe_csum_config(struct fe_priv *priv)
1106 {
1107 struct net_device *dev = priv_netdev(priv);
1108
1109 fe_txcsum_config((dev->features & NETIF_F_IP_CSUM));
1110 fe_rxcsum_config((dev->features & NETIF_F_RXCSUM));
1111 }
1112
1113 static int fe_hw_init(struct net_device *dev)
1114 {
1115 struct fe_priv *priv = netdev_priv(dev);
1116 int i, err;
1117
1118 err = devm_request_irq(priv->device, dev->irq, fe_handle_irq, 0,
1119 dev_name(priv->device), dev);
1120 if (err)
1121 return err;
1122
1123 if (priv->soc->set_mac)
1124 priv->soc->set_mac(priv, dev->dev_addr);
1125 else
1126 fe_hw_set_macaddr(priv, dev->dev_addr);
1127
1128 /* disable delay interrupt */
1129 fe_reg_w32(0, FE_REG_DLY_INT_CFG);
1130
1131 fe_int_disable(priv->soc->tx_int | priv->soc->rx_int);
1132
1133 /* frame engine will push VLAN tag regarding to VIDX feild in Tx desc. */
1134 if (fe_reg_table[FE_REG_FE_DMA_VID_BASE])
1135 for (i = 0; i < 16; i += 2)
1136 fe_w32(((i + 1) << 16) + i,
1137 fe_reg_table[FE_REG_FE_DMA_VID_BASE] +
1138 (i * 2));
1139
1140 BUG_ON(!priv->soc->fwd_config);
1141 if (priv->soc->fwd_config(priv))
1142 netdev_err(dev, "unable to get clock\n");
1143
1144 if (fe_reg_table[FE_REG_FE_RST_GL]) {
1145 fe_reg_w32(1, FE_REG_FE_RST_GL);
1146 fe_reg_w32(0, FE_REG_FE_RST_GL);
1147 }
1148
1149 return 0;
1150 }
1151
1152 static int fe_open(struct net_device *dev)
1153 {
1154 struct fe_priv *priv = netdev_priv(dev);
1155 unsigned long flags;
1156 u32 val;
1157 int err;
1158
1159 err = fe_init_dma(priv);
1160 if (err)
1161 goto err_out;
1162
1163 spin_lock_irqsave(&priv->page_lock, flags);
1164
1165 val = FE_TX_WB_DDONE | FE_RX_DMA_EN | FE_TX_DMA_EN;
1166 if (priv->flags & FE_FLAG_RX_2B_OFFSET)
1167 val |= FE_RX_2B_OFFSET;
1168 val |= priv->soc->pdma_glo_cfg;
1169 fe_reg_w32(val, FE_REG_PDMA_GLO_CFG);
1170
1171 spin_unlock_irqrestore(&priv->page_lock, flags);
1172
1173 if (priv->phy)
1174 priv->phy->start(priv);
1175
1176 if (priv->soc->has_carrier && priv->soc->has_carrier(priv))
1177 netif_carrier_on(dev);
1178
1179 napi_enable(&priv->rx_napi);
1180 fe_int_enable(priv->soc->tx_int | priv->soc->rx_int);
1181 netif_start_queue(dev);
1182
1183 return 0;
1184
1185 err_out:
1186 fe_free_dma(priv);
1187 return err;
1188 }
1189
1190 static int fe_stop(struct net_device *dev)
1191 {
1192 struct fe_priv *priv = netdev_priv(dev);
1193 unsigned long flags;
1194 int i;
1195
1196 netif_tx_disable(dev);
1197 fe_int_disable(priv->soc->tx_int | priv->soc->rx_int);
1198 napi_disable(&priv->rx_napi);
1199
1200 if (priv->phy)
1201 priv->phy->stop(priv);
1202
1203 spin_lock_irqsave(&priv->page_lock, flags);
1204
1205 fe_reg_w32(fe_reg_r32(FE_REG_PDMA_GLO_CFG) &
1206 ~(FE_TX_WB_DDONE | FE_RX_DMA_EN | FE_TX_DMA_EN),
1207 FE_REG_PDMA_GLO_CFG);
1208 spin_unlock_irqrestore(&priv->page_lock, flags);
1209
1210 /* wait dma stop */
1211 for (i = 0; i < 10; i++) {
1212 if (fe_reg_r32(FE_REG_PDMA_GLO_CFG) &
1213 (FE_TX_DMA_BUSY | FE_RX_DMA_BUSY)) {
1214 msleep(10);
1215 continue;
1216 }
1217 break;
1218 }
1219
1220 fe_free_dma(priv);
1221
1222 return 0;
1223 }
1224
1225 static int __init fe_init(struct net_device *dev)
1226 {
1227 struct fe_priv *priv = netdev_priv(dev);
1228 struct device_node *port;
1229 int err;
1230
1231 BUG_ON(!priv->soc->reset_fe);
1232 priv->soc->reset_fe();
1233
1234 if (priv->soc->switch_init)
1235 priv->soc->switch_init(priv);
1236
1237 of_get_mac_address_mtd(priv->device->of_node, dev->dev_addr);
1238 /*If the mac address is invalid, use random mac address */
1239 if (!is_valid_ether_addr(dev->dev_addr)) {
1240 random_ether_addr(dev->dev_addr);
1241 dev_err(priv->device, "generated random MAC address %pM\n",
1242 dev->dev_addr);
1243 }
1244
1245 err = fe_mdio_init(priv);
1246 if (err)
1247 return err;
1248
1249 if (priv->soc->port_init)
1250 for_each_child_of_node(priv->device->of_node, port)
1251 if (of_device_is_compatible(port, "ralink,eth-port") && of_device_is_available(port))
1252 priv->soc->port_init(priv, port);
1253
1254 if (priv->phy) {
1255 err = priv->phy->connect(priv);
1256 if (err)
1257 goto err_phy_disconnect;
1258 }
1259
1260 err = fe_hw_init(dev);
1261 if (err)
1262 goto err_phy_disconnect;
1263
1264 if (priv->soc->switch_config)
1265 priv->soc->switch_config(priv);
1266
1267 return 0;
1268
1269 err_phy_disconnect:
1270 if (priv->phy)
1271 priv->phy->disconnect(priv);
1272 fe_mdio_cleanup(priv);
1273
1274 return err;
1275 }
1276
1277 static void fe_uninit(struct net_device *dev)
1278 {
1279 struct fe_priv *priv = netdev_priv(dev);
1280
1281 if (priv->phy)
1282 priv->phy->disconnect(priv);
1283 fe_mdio_cleanup(priv);
1284
1285 fe_reg_w32(0, FE_REG_FE_INT_ENABLE);
1286 free_irq(dev->irq, dev);
1287 }
1288
1289 static int fe_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1290 {
1291 struct fe_priv *priv = netdev_priv(dev);
1292
1293 if (!priv->phy_dev)
1294 return -ENODEV;
1295
1296 switch (cmd) {
1297 case SIOCETHTOOL:
1298 return phy_ethtool_ioctl(priv->phy_dev,
1299 (void *) ifr->ifr_data);
1300 case SIOCGMIIPHY:
1301 case SIOCGMIIREG:
1302 case SIOCSMIIREG:
1303 return phy_mii_ioctl(priv->phy_dev, ifr, cmd);
1304 default:
1305 break;
1306 }
1307
1308 return -EOPNOTSUPP;
1309 }
1310
1311 static int fe_change_mtu(struct net_device *dev, int new_mtu)
1312 {
1313 struct fe_priv *priv = netdev_priv(dev);
1314 int frag_size, old_mtu;
1315 u32 fwd_cfg;
1316
1317 if (!(priv->flags & FE_FLAG_JUMBO_FRAME))
1318 return eth_change_mtu(dev, new_mtu);
1319
1320 frag_size = fe_max_frag_size(new_mtu);
1321 if (new_mtu < 68 || frag_size > PAGE_SIZE)
1322 return -EINVAL;
1323
1324 old_mtu = dev->mtu;
1325 dev->mtu = new_mtu;
1326
1327 /* return early if the buffer sizes will not change */
1328 if (old_mtu <= ETH_DATA_LEN && new_mtu <= ETH_DATA_LEN)
1329 return 0;
1330 if (old_mtu > ETH_DATA_LEN && new_mtu > ETH_DATA_LEN)
1331 return 0;
1332
1333 if (new_mtu <= ETH_DATA_LEN)
1334 priv->frag_size = fe_max_frag_size(ETH_DATA_LEN);
1335 else
1336 priv->frag_size = PAGE_SIZE;
1337 priv->rx_buf_size = fe_max_buf_size(priv->frag_size);
1338
1339 if (!netif_running(dev))
1340 return 0;
1341
1342 fe_stop(dev);
1343 fwd_cfg = fe_r32(FE_GDMA1_FWD_CFG);
1344 if (new_mtu <= ETH_DATA_LEN)
1345 fwd_cfg &= ~FE_GDM1_JMB_EN;
1346 else {
1347 fwd_cfg &= ~(FE_GDM1_JMB_LEN_MASK << FE_GDM1_JMB_LEN_SHIFT);
1348 fwd_cfg |= (DIV_ROUND_UP(frag_size, 1024) <<
1349 FE_GDM1_JMB_LEN_SHIFT) | FE_GDM1_JMB_EN;
1350 }
1351 fe_w32(fwd_cfg, FE_GDMA1_FWD_CFG);
1352
1353 return fe_open(dev);
1354 }
1355
1356 static const struct net_device_ops fe_netdev_ops = {
1357 .ndo_init = fe_init,
1358 .ndo_uninit = fe_uninit,
1359 .ndo_open = fe_open,
1360 .ndo_stop = fe_stop,
1361 .ndo_start_xmit = fe_start_xmit,
1362 .ndo_set_mac_address = fe_set_mac_address,
1363 .ndo_validate_addr = eth_validate_addr,
1364 .ndo_do_ioctl = fe_do_ioctl,
1365 .ndo_change_mtu = fe_change_mtu,
1366 .ndo_tx_timeout = fe_tx_timeout,
1367 .ndo_get_stats64 = fe_get_stats64,
1368 .ndo_vlan_rx_add_vid = fe_vlan_rx_add_vid,
1369 .ndo_vlan_rx_kill_vid = fe_vlan_rx_kill_vid,
1370 #ifdef CONFIG_NET_POLL_CONTROLLER
1371 .ndo_poll_controller = fe_poll_controller,
1372 #endif
1373 };
1374
1375 static void fe_reset_pending(struct fe_priv *priv)
1376 {
1377 struct net_device *dev = priv->netdev;
1378 int err;
1379
1380 rtnl_lock();
1381 fe_stop(dev);
1382
1383 err = fe_open(dev);
1384 if (err)
1385 goto error;
1386 rtnl_unlock();
1387
1388 return;
1389 error:
1390 netif_alert(priv, ifup, dev,
1391 "Driver up/down cycle failed, closing device.\n");
1392 dev_close(dev);
1393 rtnl_unlock();
1394 }
1395
1396 static const struct fe_work_t fe_work[] = {
1397 {FE_FLAG_RESET_PENDING, fe_reset_pending},
1398 };
1399
1400 static void fe_pending_work(struct work_struct *work)
1401 {
1402 struct fe_priv *priv = container_of(work, struct fe_priv, pending_work);
1403 int i;
1404 bool pending;
1405
1406 for (i = 0; i < ARRAY_SIZE(fe_work); i++) {
1407 pending = test_and_clear_bit(fe_work[i].bitnr,
1408 priv->pending_flags);
1409 if (pending)
1410 fe_work[i].action(priv);
1411 }
1412 }
1413
1414 static int fe_probe(struct platform_device *pdev)
1415 {
1416 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1417 const struct of_device_id *match;
1418 struct fe_soc_data *soc;
1419 struct net_device *netdev;
1420 struct fe_priv *priv;
1421 struct clk *sysclk;
1422 int err, napi_weight;
1423
1424 device_reset(&pdev->dev);
1425
1426 match = of_match_device(of_fe_match, &pdev->dev);
1427 soc = (struct fe_soc_data *) match->data;
1428
1429 if (soc->reg_table)
1430 fe_reg_table = soc->reg_table;
1431 else
1432 soc->reg_table = fe_reg_table;
1433
1434 fe_base = devm_ioremap_resource(&pdev->dev, res);
1435 if (!fe_base) {
1436 err = -EADDRNOTAVAIL;
1437 goto err_out;
1438 }
1439
1440 netdev = alloc_etherdev(sizeof(*priv));
1441 if (!netdev) {
1442 dev_err(&pdev->dev, "alloc_etherdev failed\n");
1443 err = -ENOMEM;
1444 goto err_iounmap;
1445 }
1446
1447 SET_NETDEV_DEV(netdev, &pdev->dev);
1448 netdev->netdev_ops = &fe_netdev_ops;
1449 netdev->base_addr = (unsigned long) fe_base;
1450
1451 netdev->irq = platform_get_irq(pdev, 0);
1452 if (netdev->irq < 0) {
1453 dev_err(&pdev->dev, "no IRQ resource found\n");
1454 err = -ENXIO;
1455 goto err_free_dev;
1456 }
1457
1458 if (soc->init_data)
1459 soc->init_data(soc, netdev);
1460 /* fake NETIF_F_HW_VLAN_CTAG_RX for good GRO performance */
1461 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX;
1462 netdev->vlan_features = netdev->hw_features &
1463 ~(NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX);
1464 netdev->features |= netdev->hw_features;
1465
1466 /* fake rx vlan filter func. to support tx vlan offload func */
1467 if (fe_reg_table[FE_REG_FE_DMA_VID_BASE])
1468 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
1469
1470 priv = netdev_priv(netdev);
1471 spin_lock_init(&priv->page_lock);
1472 if (fe_reg_table[FE_REG_FE_COUNTER_BASE]) {
1473 priv->hw_stats = kzalloc(sizeof(*priv->hw_stats), GFP_KERNEL);
1474 if (!priv->hw_stats) {
1475 err = -ENOMEM;
1476 goto err_free_dev;
1477 }
1478 spin_lock_init(&priv->hw_stats->stats_lock);
1479 }
1480
1481 sysclk = devm_clk_get(&pdev->dev, NULL);
1482 if (!IS_ERR(sysclk))
1483 priv->sysclk = clk_get_rate(sysclk);
1484
1485 priv->netdev = netdev;
1486 priv->device = &pdev->dev;
1487 priv->soc = soc;
1488 priv->msg_enable = netif_msg_init(fe_msg_level, FE_DEFAULT_MSG_ENABLE);
1489 priv->frag_size = fe_max_frag_size(ETH_DATA_LEN);
1490 priv->rx_buf_size = fe_max_buf_size(priv->frag_size);
1491 priv->tx_ring.tx_ring_size = priv->rx_ring_size = NUM_DMA_DESC;
1492 INIT_WORK(&priv->pending_work, fe_pending_work);
1493
1494 napi_weight = 32;
1495 if (priv->flags & FE_FLAG_NAPI_WEIGHT) {
1496 napi_weight *= 4;
1497 priv->tx_ring.tx_ring_size *= 4;
1498 priv->rx_ring_size *= 4;
1499 }
1500 netif_napi_add(netdev, &priv->rx_napi, fe_poll, napi_weight);
1501 fe_set_ethtool_ops(netdev);
1502
1503 err = register_netdev(netdev);
1504 if (err) {
1505 dev_err(&pdev->dev, "error bringing up device\n");
1506 goto err_free_dev;
1507 }
1508
1509 platform_set_drvdata(pdev, netdev);
1510
1511 netif_info(priv, probe, netdev, "ralink at 0x%08lx, irq %d\n",
1512 netdev->base_addr, netdev->irq);
1513
1514 return 0;
1515
1516 err_free_dev:
1517 free_netdev(netdev);
1518 err_iounmap:
1519 devm_iounmap(&pdev->dev, fe_base);
1520 err_out:
1521 return err;
1522 }
1523
1524 static int fe_remove(struct platform_device *pdev)
1525 {
1526 struct net_device *dev = platform_get_drvdata(pdev);
1527 struct fe_priv *priv = netdev_priv(dev);
1528
1529 netif_napi_del(&priv->rx_napi);
1530 if (priv->hw_stats)
1531 kfree(priv->hw_stats);
1532
1533 cancel_work_sync(&priv->pending_work);
1534
1535 unregister_netdev(dev);
1536 free_netdev(dev);
1537 platform_set_drvdata(pdev, NULL);
1538
1539 return 0;
1540 }
1541
1542 static struct platform_driver fe_driver = {
1543 .probe = fe_probe,
1544 .remove = fe_remove,
1545 .driver = {
1546 .name = "ralink_soc_eth",
1547 .owner = THIS_MODULE,
1548 .of_match_table = of_fe_match,
1549 },
1550 };
1551
1552 static int __init init_rtfe(void)
1553 {
1554 int ret;
1555
1556 ret = rtesw_init();
1557 if (ret)
1558 return ret;
1559
1560 ret = platform_driver_register(&fe_driver);
1561 if (ret)
1562 rtesw_exit();
1563
1564 return ret;
1565 }
1566
1567 static void __exit exit_rtfe(void)
1568 {
1569 platform_driver_unregister(&fe_driver);
1570 rtesw_exit();
1571 }
1572
1573 module_init(init_rtfe);
1574 module_exit(exit_rtfe);
1575
1576 MODULE_LICENSE("GPL");
1577 MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
1578 MODULE_DESCRIPTION("Ethernet driver for Ralink SoC");
1579 MODULE_VERSION(FE_DRV_VERSION);
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