projects / openwrt / openwrt.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
ramips: Fix setting of rx buffer length
[openwrt/openwrt.git] / target / linux / ramips / files / drivers / net / ethernet / ralink / ralink_soc_eth.c
1 /*
2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License as published by
4 * the Free Software Foundation; version 2 of the License
5 *
6 * This program is distributed in the hope that it will be useful,
7 * but WITHOUT ANY WARRANTY; without even the implied warranty of
8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9 * GNU General Public License for more details.
10 *
11 * You should have received a copy of the GNU General Public License
12 * along with this program; if not, write to the Free Software
13 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
14 *
15 * Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
16 */
17
18 #include <linux/module.h>
19 #include <linux/kernel.h>
20 #include <linux/types.h>
21 #include <linux/dma-mapping.h>
22 #include <linux/init.h>
23 #include <linux/skbuff.h>
24 #include <linux/etherdevice.h>
25 #include <linux/ethtool.h>
26 #include <linux/platform_device.h>
27 #include <linux/of_device.h>
28 #include <linux/clk.h>
29 #include <linux/of_net.h>
30 #include <linux/of_mdio.h>
31 #include <linux/if_vlan.h>
32 #include <linux/reset.h>
33 #include <linux/tcp.h>
34 #include <linux/io.h>
35
36 #include <asm/mach-ralink/ralink_regs.h>
37
38 #include "ralink_soc_eth.h"
39 #include "esw_rt3052.h"
40 #include "mdio.h"
41 #include "ralink_ethtool.h"
42
43 #define MAX_RX_LENGTH 1536
44 #define FE_RX_HLEN (NET_SKB_PAD + VLAN_ETH_HLEN + VLAN_HLEN + \
45 + NET_IP_ALIGN + ETH_FCS_LEN)
46 #define DMA_DUMMY_DESC 0xffffffff
47 #define FE_DEFAULT_MSG_ENABLE \
48 (NETIF_MSG_DRV | \
49 NETIF_MSG_PROBE | \
50 NETIF_MSG_LINK | \
51 NETIF_MSG_TIMER | \
52 NETIF_MSG_IFDOWN | \
53 NETIF_MSG_IFUP | \
54 NETIF_MSG_RX_ERR | \
55 NETIF_MSG_TX_ERR)
56
57 #define TX_DMA_DESP2_DEF (TX_DMA_LS0 | TX_DMA_DONE)
58 #define TX_DMA_DESP4_DEF (TX_DMA_QN(3) | TX_DMA_PN(1))
59 #define NEXT_TX_DESP_IDX(X) (((X) + 1) & (ring->tx_ring_size - 1))
60 #define NEXT_RX_DESP_IDX(X) (((X) + 1) & (ring->rx_ring_size - 1))
61
62 #define SYSC_REG_RSTCTRL 0x34
63
64 static int fe_msg_level = -1;
65 module_param_named(msg_level, fe_msg_level, int, 0);
66 MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)");
67
68 static const u16 fe_reg_table_default[FE_REG_COUNT] = {
69 [FE_REG_PDMA_GLO_CFG] = FE_PDMA_GLO_CFG,
70 [FE_REG_PDMA_RST_CFG] = FE_PDMA_RST_CFG,
71 [FE_REG_DLY_INT_CFG] = FE_DLY_INT_CFG,
72 [FE_REG_TX_BASE_PTR0] = FE_TX_BASE_PTR0,
73 [FE_REG_TX_MAX_CNT0] = FE_TX_MAX_CNT0,
74 [FE_REG_TX_CTX_IDX0] = FE_TX_CTX_IDX0,
75 [FE_REG_TX_DTX_IDX0] = FE_TX_DTX_IDX0,
76 [FE_REG_RX_BASE_PTR0] = FE_RX_BASE_PTR0,
77 [FE_REG_RX_MAX_CNT0] = FE_RX_MAX_CNT0,
78 [FE_REG_RX_CALC_IDX0] = FE_RX_CALC_IDX0,
79 [FE_REG_RX_DRX_IDX0] = FE_RX_DRX_IDX0,
80 [FE_REG_FE_INT_ENABLE] = FE_FE_INT_ENABLE,
81 [FE_REG_FE_INT_STATUS] = FE_FE_INT_STATUS,
82 [FE_REG_FE_DMA_VID_BASE] = FE_DMA_VID0,
83 [FE_REG_FE_COUNTER_BASE] = FE_GDMA1_TX_GBCNT,
84 [FE_REG_FE_RST_GL] = FE_FE_RST_GL,
85 };
86
87 static const u16 *fe_reg_table = fe_reg_table_default;
88
89 struct fe_work_t {
90 int bitnr;
91 void (*action)(struct fe_priv *);
92 };
93
94 static void __iomem *fe_base = 0;
95
96 void fe_w32(u32 val, unsigned reg)
97 {
98 __raw_writel(val, fe_base + reg);
99 }
100
101 u32 fe_r32(unsigned reg)
102 {
103 return __raw_readl(fe_base + reg);
104 }
105
106 void fe_reg_w32(u32 val, enum fe_reg reg)
107 {
108 fe_w32(val, fe_reg_table[reg]);
109 }
110
111 u32 fe_reg_r32(enum fe_reg reg)
112 {
113 return fe_r32(fe_reg_table[reg]);
114 }
115
116 void fe_reset(u32 reset_bits)
117 {
118 u32 t;
119
120 t = rt_sysc_r32(SYSC_REG_RSTCTRL);
121 t |= reset_bits;
122 rt_sysc_w32(t , SYSC_REG_RSTCTRL);
123 udelay(10);
124
125 t &= ~reset_bits;
126 rt_sysc_w32(t, SYSC_REG_RSTCTRL);
127 udelay(10);
128 }
129
130 static inline void fe_int_disable(u32 mask)
131 {
132 fe_reg_w32(fe_reg_r32(FE_REG_FE_INT_ENABLE) & ~mask,
133 FE_REG_FE_INT_ENABLE);
134 /* flush write */
135 fe_reg_r32(FE_REG_FE_INT_ENABLE);
136 }
137
138 static inline void fe_int_enable(u32 mask)
139 {
140 fe_reg_w32(fe_reg_r32(FE_REG_FE_INT_ENABLE) | mask,
141 FE_REG_FE_INT_ENABLE);
142 /* flush write */
143 fe_reg_r32(FE_REG_FE_INT_ENABLE);
144 }
145
146 static inline void fe_hw_set_macaddr(struct fe_priv *priv, unsigned char *mac)
147 {
148 unsigned long flags;
149
150 spin_lock_irqsave(&priv->page_lock, flags);
151 fe_w32((mac[0] << 8) | mac[1], FE_GDMA1_MAC_ADRH);
152 fe_w32((mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5],
153 FE_GDMA1_MAC_ADRL);
154 spin_unlock_irqrestore(&priv->page_lock, flags);
155 }
156
157 static int fe_set_mac_address(struct net_device *dev, void *p)
158 {
159 int ret = eth_mac_addr(dev, p);
160
161 if (!ret) {
162 struct fe_priv *priv = netdev_priv(dev);
163
164 if (priv->soc->set_mac)
165 priv->soc->set_mac(priv, dev->dev_addr);
166 else
167 fe_hw_set_macaddr(priv, p);
168 }
169
170 return ret;
171 }
172
173 static inline int fe_max_frag_size(int mtu)
174 {
175 return SKB_DATA_ALIGN(FE_RX_HLEN + mtu) +
176 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
177 }
178
179 static inline int fe_max_buf_size(int frag_size)
180 {
181 return frag_size - NET_SKB_PAD - NET_IP_ALIGN -
182 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
183 }
184
185 static inline void fe_get_rxd(struct fe_rx_dma *rxd, struct fe_rx_dma *dma_rxd)
186 {
187 rxd->rxd1 = dma_rxd->rxd1;
188 rxd->rxd2 = dma_rxd->rxd2;
189 rxd->rxd3 = dma_rxd->rxd3;
190 rxd->rxd4 = dma_rxd->rxd4;
191 }
192
193 static inline void fe_set_txd(struct fe_tx_dma *txd, struct fe_tx_dma *dma_txd)
194 {
195 dma_txd->txd1 = txd->txd1;
196 dma_txd->txd3 = txd->txd3;
197 dma_txd->txd4 = txd->txd4;
198 /* clean dma done flag last */
199 dma_txd->txd2 = txd->txd2;
200 }
201
202 static void fe_clean_rx(struct fe_priv *priv)
203 {
204 int i;
205 struct fe_rx_ring *ring = &priv->rx_ring;
206
207 if (ring->rx_data) {
208 for (i = 0; i < ring->rx_ring_size; i++)
209 if (ring->rx_data[i]) {
210 if (ring->rx_dma && ring->rx_dma[i].rxd1)
211 dma_unmap_single(&priv->netdev->dev,
212 ring->rx_dma[i].rxd1,
213 ring->rx_buf_size,
214 DMA_FROM_DEVICE);
215 put_page(virt_to_head_page(ring->rx_data[i]));
216 }
217
218 kfree(ring->rx_data);
219 ring->rx_data = NULL;
220 }
221
222 if (ring->rx_dma) {
223 dma_free_coherent(&priv->netdev->dev,
224 ring->rx_ring_size * sizeof(*ring->rx_dma),
225 ring->rx_dma,
226 ring->rx_phys);
227 ring->rx_dma = NULL;
228 }
229 }
230
231 static int fe_alloc_rx(struct fe_priv *priv)
232 {
233 struct net_device *netdev = priv->netdev;
234 struct fe_rx_ring *ring = &priv->rx_ring;
235 int i, pad;
236
237 ring->rx_data = kcalloc(ring->rx_ring_size, sizeof(*ring->rx_data),
238 GFP_KERNEL);
239 if (!ring->rx_data)
240 goto no_rx_mem;
241
242 for (i = 0; i < ring->rx_ring_size; i++) {
243 ring->rx_data[i] = netdev_alloc_frag(ring->frag_size);
244 if (!ring->rx_data[i])
245 goto no_rx_mem;
246 }
247
248 ring->rx_dma = dma_alloc_coherent(&netdev->dev,
249 ring->rx_ring_size * sizeof(*ring->rx_dma),
250 &ring->rx_phys,
251 GFP_ATOMIC | __GFP_ZERO);
252 if (!ring->rx_dma)
253 goto no_rx_mem;
254
255 if (priv->flags & FE_FLAG_RX_2B_OFFSET)
256 pad = 0;
257 else
258 pad = NET_IP_ALIGN;
259 for (i = 0; i < ring->rx_ring_size; i++) {
260 dma_addr_t dma_addr = dma_map_single(&netdev->dev,
261 ring->rx_data[i] + NET_SKB_PAD + pad,
262 ring->rx_buf_size,
263 DMA_FROM_DEVICE);
264 if (unlikely(dma_mapping_error(&netdev->dev, dma_addr)))
265 goto no_rx_mem;
266 ring->rx_dma[i].rxd1 = (unsigned int) dma_addr;
267
268 if (priv->flags & FE_FLAG_RX_SG_DMA)
269 ring->rx_dma[i].rxd2 = RX_DMA_PLEN0(ring->rx_buf_size);
270 else
271 ring->rx_dma[i].rxd2 = RX_DMA_LSO;
272 }
273 ring->rx_calc_idx = ring->rx_ring_size - 1;
274 wmb();
275
276 fe_reg_w32(ring->rx_phys, FE_REG_RX_BASE_PTR0);
277 fe_reg_w32(ring->rx_ring_size, FE_REG_RX_MAX_CNT0);
278 fe_reg_w32(ring->rx_calc_idx, FE_REG_RX_CALC_IDX0);
279 fe_reg_w32(FE_PST_DRX_IDX0, FE_REG_PDMA_RST_CFG);
280
281 return 0;
282
283 no_rx_mem:
284 return -ENOMEM;
285 }
286
287 static void fe_txd_unmap(struct device *dev, struct fe_tx_buf *tx_buf)
288 {
289 if (tx_buf->flags & FE_TX_FLAGS_SINGLE0) {
290 dma_unmap_single(dev,
291 dma_unmap_addr(tx_buf, dma_addr0),
292 dma_unmap_len(tx_buf, dma_len0),
293 DMA_TO_DEVICE);
294 } else if (tx_buf->flags & FE_TX_FLAGS_PAGE0) {
295 dma_unmap_page(dev,
296 dma_unmap_addr(tx_buf, dma_addr0),
297 dma_unmap_len(tx_buf, dma_len0),
298 DMA_TO_DEVICE);
299 }
300 if (tx_buf->flags & FE_TX_FLAGS_PAGE1)
301 dma_unmap_page(dev,
302 dma_unmap_addr(tx_buf, dma_addr1),
303 dma_unmap_len(tx_buf, dma_len1),
304 DMA_TO_DEVICE);
305
306 tx_buf->flags = 0;
307 if (tx_buf->skb && (tx_buf->skb != (struct sk_buff *) DMA_DUMMY_DESC)) {
308 dev_kfree_skb_any(tx_buf->skb);
309 }
310 tx_buf->skb = NULL;
311 }
312
313 static void fe_clean_tx(struct fe_priv *priv)
314 {
315 int i;
316 struct device *dev = &priv->netdev->dev;
317 struct fe_tx_ring *ring = &priv->tx_ring;
318
319 if (ring->tx_buf) {
320 for (i = 0; i < ring->tx_ring_size; i++)
321 fe_txd_unmap(dev, &ring->tx_buf[i]);
322 kfree(ring->tx_buf);
323 ring->tx_buf = NULL;
324 }
325
326 if (ring->tx_dma) {
327 dma_free_coherent(dev,
328 ring->tx_ring_size * sizeof(*ring->tx_dma),
329 ring->tx_dma,
330 ring->tx_phys);
331 ring->tx_dma = NULL;
332 }
333
334 netdev_reset_queue(priv->netdev);
335 }
336
337 static int fe_alloc_tx(struct fe_priv *priv)
338 {
339 int i;
340 struct fe_tx_ring *ring = &priv->tx_ring;
341
342 ring->tx_free_idx = 0;
343 ring->tx_next_idx = 0;
344 ring->tx_thresh = max((unsigned long)ring->tx_ring_size >> 2, MAX_SKB_FRAGS);
345
346 ring->tx_buf = kcalloc(ring->tx_ring_size, sizeof(*ring->tx_buf),
347 GFP_KERNEL);
348 if (!ring->tx_buf)
349 goto no_tx_mem;
350
351 ring->tx_dma = dma_alloc_coherent(&priv->netdev->dev,
352 ring->tx_ring_size * sizeof(*ring->tx_dma),
353 &ring->tx_phys,
354 GFP_ATOMIC | __GFP_ZERO);
355 if (!ring->tx_dma)
356 goto no_tx_mem;
357
358 for (i = 0; i < ring->tx_ring_size; i++) {
359 if (priv->soc->tx_dma) {
360 priv->soc->tx_dma(&ring->tx_dma[i]);
361 }
362 ring->tx_dma[i].txd2 = TX_DMA_DESP2_DEF;
363 }
364 wmb();
365
366 fe_reg_w32(ring->tx_phys, FE_REG_TX_BASE_PTR0);
367 fe_reg_w32(ring->tx_ring_size, FE_REG_TX_MAX_CNT0);
368 fe_reg_w32(0, FE_REG_TX_CTX_IDX0);
369 fe_reg_w32(FE_PST_DTX_IDX0, FE_REG_PDMA_RST_CFG);
370
371 return 0;
372
373 no_tx_mem:
374 return -ENOMEM;
375 }
376
377 static int fe_init_dma(struct fe_priv *priv)
378 {
379 int err;
380
381 err = fe_alloc_tx(priv);
382 if (err)
383 return err;
384
385 err = fe_alloc_rx(priv);
386 if (err)
387 return err;
388
389 return 0;
390 }
391
392 static void fe_free_dma(struct fe_priv *priv)
393 {
394 fe_clean_tx(priv);
395 fe_clean_rx(priv);
396 }
397
398 void fe_stats_update(struct fe_priv *priv)
399 {
400 struct fe_hw_stats *hwstats = priv->hw_stats;
401 unsigned int base = fe_reg_table[FE_REG_FE_COUNTER_BASE];
402 u64 stats;
403
404 u64_stats_update_begin(&hwstats->syncp);
405
406 if (IS_ENABLED(CONFIG_SOC_MT7621)) {
407 hwstats->rx_bytes += fe_r32(base);
408 stats = fe_r32(base + 0x04);
409 if (stats)
410 hwstats->rx_bytes += (stats << 32);
411 hwstats->rx_packets += fe_r32(base + 0x08);
412 hwstats->rx_overflow += fe_r32(base + 0x10);
413 hwstats->rx_fcs_errors += fe_r32(base + 0x14);
414 hwstats->rx_short_errors += fe_r32(base + 0x18);
415 hwstats->rx_long_errors += fe_r32(base + 0x1c);
416 hwstats->rx_checksum_errors += fe_r32(base + 0x20);
417 hwstats->rx_flow_control_packets += fe_r32(base + 0x24);
418 hwstats->tx_skip += fe_r32(base + 0x28);
419 hwstats->tx_collisions += fe_r32(base + 0x2c);
420 hwstats->tx_bytes += fe_r32(base + 0x30);
421 stats = fe_r32(base + 0x34);
422 if (stats)
423 hwstats->tx_bytes += (stats << 32);
424 hwstats->tx_packets += fe_r32(base + 0x38);
425 } else {
426 hwstats->tx_bytes += fe_r32(base);
427 hwstats->tx_packets += fe_r32(base + 0x04);
428 hwstats->tx_skip += fe_r32(base + 0x08);
429 hwstats->tx_collisions += fe_r32(base + 0x0c);
430 hwstats->rx_bytes += fe_r32(base + 0x20);
431 hwstats->rx_packets += fe_r32(base + 0x24);
432 hwstats->rx_overflow += fe_r32(base + 0x28);
433 hwstats->rx_fcs_errors += fe_r32(base + 0x2c);
434 hwstats->rx_short_errors += fe_r32(base + 0x30);
435 hwstats->rx_long_errors += fe_r32(base + 0x34);
436 hwstats->rx_checksum_errors += fe_r32(base + 0x38);
437 hwstats->rx_flow_control_packets += fe_r32(base + 0x3c);
438 }
439
440 u64_stats_update_end(&hwstats->syncp);
441 }
442
443 static struct rtnl_link_stats64 *fe_get_stats64(struct net_device *dev,
444 struct rtnl_link_stats64 *storage)
445 {
446 struct fe_priv *priv = netdev_priv(dev);
447 struct fe_hw_stats *hwstats = priv->hw_stats;
448 unsigned int base = fe_reg_table[FE_REG_FE_COUNTER_BASE];
449 unsigned int start;
450
451 if (!base) {
452 netdev_stats_to_stats64(storage, &dev->stats);
453 return storage;
454 }
455
456 if (netif_running(dev) && netif_device_present(dev)) {
457 if (spin_trylock(&hwstats->stats_lock)) {
458 fe_stats_update(priv);
459 spin_unlock(&hwstats->stats_lock);
460 }
461 }
462
463 do {
464 start = u64_stats_fetch_begin_irq(&hwstats->syncp);
465 storage->rx_packets = hwstats->rx_packets;
466 storage->tx_packets = hwstats->tx_packets;
467 storage->rx_bytes = hwstats->rx_bytes;
468 storage->tx_bytes = hwstats->tx_bytes;
469 storage->collisions = hwstats->tx_collisions;
470 storage->rx_length_errors = hwstats->rx_short_errors +
471 hwstats->rx_long_errors;
472 storage->rx_over_errors = hwstats->rx_overflow;
473 storage->rx_crc_errors = hwstats->rx_fcs_errors;
474 storage->rx_errors = hwstats->rx_checksum_errors;
475 storage->tx_aborted_errors = hwstats->tx_skip;
476 } while (u64_stats_fetch_retry_irq(&hwstats->syncp, start));
477
478 storage->tx_errors = priv->netdev->stats.tx_errors;
479 storage->rx_dropped = priv->netdev->stats.rx_dropped;
480 storage->tx_dropped = priv->netdev->stats.tx_dropped;
481
482 return storage;
483 }
484
485 static int fe_vlan_rx_add_vid(struct net_device *dev,
486 __be16 proto, u16 vid)
487 {
488 struct fe_priv *priv = netdev_priv(dev);
489 u32 idx = (vid & 0xf);
490 u32 vlan_cfg;
491
492 if (!((fe_reg_table[FE_REG_FE_DMA_VID_BASE]) &&
493 (dev->features & NETIF_F_HW_VLAN_CTAG_TX)))
494 return 0;
495
496 if (test_bit(idx, &priv->vlan_map)) {
497 netdev_warn(dev, "disable tx vlan offload\n");
498 dev->wanted_features &= ~NETIF_F_HW_VLAN_CTAG_TX;
499 netdev_update_features(dev);
500 } else {
501 vlan_cfg = fe_r32(fe_reg_table[FE_REG_FE_DMA_VID_BASE] +
502 ((idx >> 1) << 2));
503 if (idx & 0x1) {
504 vlan_cfg &= 0xffff;
505 vlan_cfg |= (vid << 16);
506 } else {
507 vlan_cfg &= 0xffff0000;
508 vlan_cfg |= vid;
509 }
510 fe_w32(vlan_cfg, fe_reg_table[FE_REG_FE_DMA_VID_BASE] +
511 ((idx >> 1) << 2));
512 set_bit(idx, &priv->vlan_map);
513 }
514
515 return 0;
516 }
517
518 static int fe_vlan_rx_kill_vid(struct net_device *dev,
519 __be16 proto, u16 vid)
520 {
521 struct fe_priv *priv = netdev_priv(dev);
522 u32 idx = (vid & 0xf);
523
524 if (!((fe_reg_table[FE_REG_FE_DMA_VID_BASE]) &&
525 (dev->features & NETIF_F_HW_VLAN_CTAG_TX)))
526 return 0;
527
528 clear_bit(idx, &priv->vlan_map);
529
530 return 0;
531 }
532
533 static inline u32 fe_empty_txd(struct fe_tx_ring *ring)
534 {
535 barrier();
536 return (u32)(ring->tx_ring_size -
537 ((ring->tx_next_idx - ring->tx_free_idx) &
538 (ring->tx_ring_size - 1)));
539 }
540
541 static int fe_tx_map_dma(struct sk_buff *skb, struct net_device *dev,
542 int tx_num, struct fe_tx_ring *ring)
543 {
544 struct fe_priv *priv = netdev_priv(dev);
545 struct skb_frag_struct *frag;
546 struct fe_tx_dma txd, *ptxd;
547 struct fe_tx_buf *tx_buf;
548 dma_addr_t mapped_addr;
549 unsigned int nr_frags;
550 u32 def_txd4;
551 int i, j, k, frag_size, frag_map_size, offset;
552
553 tx_buf = &ring->tx_buf[ring->tx_next_idx];
554 memset(tx_buf, 0, sizeof(*tx_buf));
555 memset(&txd, 0, sizeof(txd));
556 nr_frags = skb_shinfo(skb)->nr_frags;
557
558 /* init tx descriptor */
559 if (priv->soc->tx_dma)
560 priv->soc->tx_dma(&txd);
561 else
562 txd.txd4 = TX_DMA_DESP4_DEF;
563 def_txd4 = txd.txd4;
564
565 /* TX Checksum offload */
566 if (skb->ip_summed == CHECKSUM_PARTIAL)
567 txd.txd4 |= TX_DMA_CHKSUM;
568
569 /* VLAN header offload */
570 if (vlan_tx_tag_present(skb)) {
571 if (IS_ENABLED(CONFIG_SOC_MT7621))
572 txd.txd4 |= TX_DMA_INS_VLAN_MT7621 | vlan_tx_tag_get(skb);
573 else
574 txd.txd4 |= TX_DMA_INS_VLAN |
575 ((vlan_tx_tag_get(skb) >> VLAN_PRIO_SHIFT) << 4) |
576 (vlan_tx_tag_get(skb) & 0xF);
577 }
578
579 /* TSO: fill MSS info in tcp checksum field */
580 if (skb_is_gso(skb)) {
581 if (skb_cow_head(skb, 0)) {
582 netif_warn(priv, tx_err, dev,
583 "GSO expand head fail.\n");
584 goto err_out;
585 }
586 if (skb_shinfo(skb)->gso_type &
587 (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) {
588 txd.txd4 |= TX_DMA_TSO;
589 tcp_hdr(skb)->check = htons(skb_shinfo(skb)->gso_size);
590 }
591 }
592
593 mapped_addr = dma_map_single(&dev->dev, skb->data,
594 skb_headlen(skb), DMA_TO_DEVICE);
595 if (unlikely(dma_mapping_error(&dev->dev, mapped_addr)))
596 goto err_out;
597 txd.txd1 = mapped_addr;
598 txd.txd2 = TX_DMA_PLEN0(skb_headlen(skb));
599
600 tx_buf->flags |= FE_TX_FLAGS_SINGLE0;
601 dma_unmap_addr_set(tx_buf, dma_addr0, mapped_addr);
602 dma_unmap_len_set(tx_buf, dma_len0, skb_headlen(skb));
603
604 /* TX SG offload */
605 j = ring->tx_next_idx;
606 k = 0;
607 for (i = 0; i < nr_frags; i++) {
608 offset = 0;
609 frag = &skb_shinfo(skb)->frags[i];
610 frag_size = skb_frag_size(frag);
611
612 while (frag_size > 0) {
613 frag_map_size = min(frag_size, TX_DMA_BUF_LEN);
614 mapped_addr = skb_frag_dma_map(&dev->dev, frag, offset,
615 frag_map_size, DMA_TO_DEVICE);
616 if (unlikely(dma_mapping_error(&dev->dev, mapped_addr)))
617 goto err_dma;
618
619 if (k & 0x1) {
620 j = NEXT_TX_DESP_IDX(j);
621 txd.txd1 = mapped_addr;
622 txd.txd2 = TX_DMA_PLEN0(frag_map_size);
623 txd.txd4 = def_txd4;
624
625 tx_buf = &ring->tx_buf[j];
626 memset(tx_buf, 0, sizeof(*tx_buf));
627
628 tx_buf->flags |= FE_TX_FLAGS_PAGE0;
629 dma_unmap_addr_set(tx_buf, dma_addr0, mapped_addr);
630 dma_unmap_len_set(tx_buf, dma_len0, frag_map_size);
631 } else {
632 txd.txd3 = mapped_addr;
633 txd.txd2 |= TX_DMA_PLEN1(frag_map_size);
634
635 tx_buf->skb = (struct sk_buff *) DMA_DUMMY_DESC;
636 tx_buf->flags |= FE_TX_FLAGS_PAGE1;
637 dma_unmap_addr_set(tx_buf, dma_addr1, mapped_addr);
638 dma_unmap_len_set(tx_buf, dma_len1, frag_map_size);
639
640 if (!((i == (nr_frags -1)) &&
641 (frag_map_size == frag_size))) {
642 fe_set_txd(&txd, &ring->tx_dma[j]);
643 memset(&txd, 0, sizeof(txd));
644 }
645 }
646 frag_size -= frag_map_size;
647 offset += frag_map_size;
648 k++;
649 }
650 }
651
652 /* set last segment */
653 if (k & 0x1)
654 txd.txd2 |= TX_DMA_LS1;
655 else
656 txd.txd2 |= TX_DMA_LS0;
657 fe_set_txd(&txd, &ring->tx_dma[j]);
658
659 /* store skb to cleanup */
660 tx_buf->skb = skb;
661
662 netdev_sent_queue(dev, skb->len);
663 skb_tx_timestamp(skb);
664
665 ring->tx_next_idx = NEXT_TX_DESP_IDX(j);
666 wmb();
667 if (unlikely(fe_empty_txd(ring) <= ring->tx_thresh)) {
668 netif_stop_queue(dev);
669 smp_mb();
670 if (unlikely(fe_empty_txd(ring) > ring->tx_thresh))
671 netif_wake_queue(dev);
672 }
673
674 if (netif_xmit_stopped(netdev_get_tx_queue(dev, 0)) || !skb->xmit_more)
675 fe_reg_w32(ring->tx_next_idx, FE_REG_TX_CTX_IDX0);
676
677 return 0;
678
679 err_dma:
680 j = ring->tx_next_idx;
681 for (i = 0; i < tx_num; i++) {
682 ptxd = &ring->tx_dma[j];
683 tx_buf = &ring->tx_buf[j];
684
685 /* unmap dma */
686 fe_txd_unmap(&dev->dev, tx_buf);
687
688 ptxd->txd2 = TX_DMA_DESP2_DEF;
689 j = NEXT_TX_DESP_IDX(j);
690 }
691 wmb();
692
693 err_out:
694 return -1;
695 }
696
697 static inline int fe_skb_padto(struct sk_buff *skb, struct fe_priv *priv) {
698 unsigned int len;
699 int ret;
700
701 ret = 0;
702 if (unlikely(skb->len < VLAN_ETH_ZLEN)) {
703 if ((priv->flags & FE_FLAG_PADDING_64B) &&
704 !(priv->flags & FE_FLAG_PADDING_BUG))
705 return ret;
706
707 if (vlan_tx_tag_present(skb))
708 len = ETH_ZLEN;
709 else if (skb->protocol == cpu_to_be16(ETH_P_8021Q))
710 len = VLAN_ETH_ZLEN;
711 else if(!(priv->flags & FE_FLAG_PADDING_64B))
712 len = ETH_ZLEN;
713 else
714 return ret;
715
716 if (skb->len < len) {
717 if ((ret = skb_pad(skb, len - skb->len)) < 0)
718 return ret;
719 skb->len = len;
720 skb_set_tail_pointer(skb, len);
721 }
722 }
723
724 return ret;
725 }
726
727 static inline int fe_cal_txd_req(struct sk_buff *skb)
728 {
729 int i, nfrags;
730 struct skb_frag_struct *frag;
731
732 nfrags = 1;
733 if (skb_is_gso(skb)) {
734 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
735 frag = &skb_shinfo(skb)->frags[i];
736 nfrags += DIV_ROUND_UP(frag->size, TX_DMA_BUF_LEN);
737 }
738 } else {
739 nfrags += skb_shinfo(skb)->nr_frags;
740 }
741
742 return DIV_ROUND_UP(nfrags, 2);
743 }
744
745 static int fe_start_xmit(struct sk_buff *skb, struct net_device *dev)
746 {
747 struct fe_priv *priv = netdev_priv(dev);
748 struct fe_tx_ring *ring = &priv->tx_ring;
749 struct net_device_stats *stats = &dev->stats;
750 int tx_num;
751 int len = skb->len;
752
753 if (fe_skb_padto(skb, priv)) {
754 netif_warn(priv, tx_err, dev, "tx padding failed!\n");
755 return NETDEV_TX_OK;
756 }
757
758 tx_num = fe_cal_txd_req(skb);
759 if (unlikely(fe_empty_txd(ring) <= tx_num))
760 {
761 netif_stop_queue(dev);
762 netif_err(priv, tx_queued,dev,
763 "Tx Ring full when queue awake!\n");
764 return NETDEV_TX_BUSY;
765 }
766
767 if (fe_tx_map_dma(skb, dev, tx_num, ring) < 0) {
768 stats->tx_dropped++;
769 } else {
770 stats->tx_packets++;
771 stats->tx_bytes += len;
772 }
773
774 return NETDEV_TX_OK;
775 }
776
777 static inline void fe_rx_vlan(struct sk_buff *skb)
778 {
779 struct ethhdr *ehdr;
780 u16 vlanid;
781
782 if (!__vlan_get_tag(skb, &vlanid)) {
783 /* pop the vlan tag */
784 ehdr = (struct ethhdr *)skb->data;
785 memmove(skb->data + VLAN_HLEN, ehdr, ETH_ALEN * 2);
786 skb_pull(skb, VLAN_HLEN);
787 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlanid);
788 }
789 }
790
791 static int fe_poll_rx(struct napi_struct *napi, int budget,
792 struct fe_priv *priv, u32 rx_intr)
793 {
794 struct net_device *netdev = priv->netdev;
795 struct net_device_stats *stats = &netdev->stats;
796 struct fe_soc_data *soc = priv->soc;
797 struct fe_rx_ring *ring = &priv->rx_ring;
798 int idx = ring->rx_calc_idx;
799 u32 checksum_bit;
800 struct sk_buff *skb;
801 u8 *data, *new_data;
802 struct fe_rx_dma *rxd, trxd;
803 int done = 0, pad;
804 bool rx_vlan = netdev->features & NETIF_F_HW_VLAN_CTAG_RX;
805
806 if (netdev->features & NETIF_F_RXCSUM)
807 checksum_bit = soc->checksum_bit;
808 else
809 checksum_bit = 0;
810
811 if (priv->flags & FE_FLAG_RX_2B_OFFSET)
812 pad = 0;
813 else
814 pad = NET_IP_ALIGN;
815
816 while (done < budget) {
817 unsigned int pktlen;
818 dma_addr_t dma_addr;
819 idx = NEXT_RX_DESP_IDX(idx);
820 rxd = &ring->rx_dma[idx];
821 data = ring->rx_data[idx];
822
823 fe_get_rxd(&trxd, rxd);
824 if (!(trxd.rxd2 & RX_DMA_DONE))
825 break;
826
827 /* alloc new buffer */
828 new_data = netdev_alloc_frag(ring->frag_size);
829 if (unlikely(!new_data)) {
830 stats->rx_dropped++;
831 goto release_desc;
832 }
833 dma_addr = dma_map_single(&netdev->dev,
834 new_data + NET_SKB_PAD + pad,
835 ring->rx_buf_size,
836 DMA_FROM_DEVICE);
837 if (unlikely(dma_mapping_error(&netdev->dev, dma_addr))) {
838 put_page(virt_to_head_page(new_data));
839 goto release_desc;
840 }
841
842 /* receive data */
843 skb = build_skb(data, ring->frag_size);
844 if (unlikely(!skb)) {
845 put_page(virt_to_head_page(new_data));
846 goto release_desc;
847 }
848 skb_reserve(skb, NET_SKB_PAD + NET_IP_ALIGN);
849
850 dma_unmap_single(&netdev->dev, trxd.rxd1,
851 ring->rx_buf_size, DMA_FROM_DEVICE);
852 pktlen = RX_DMA_GET_PLEN0(trxd.rxd2);
853 skb->dev = netdev;
854 skb_put(skb, pktlen);
855 if (trxd.rxd4 & checksum_bit) {
856 skb->ip_summed = CHECKSUM_UNNECESSARY;
857 } else {
858 skb_checksum_none_assert(skb);
859 }
860 if (rx_vlan)
861 fe_rx_vlan(skb);
862 skb->protocol = eth_type_trans(skb, netdev);
863
864 stats->rx_packets++;
865 stats->rx_bytes += pktlen;
866
867 napi_gro_receive(napi, skb);
868
869 ring->rx_data[idx] = new_data;
870 rxd->rxd1 = (unsigned int) dma_addr;
871
872 release_desc:
873 if (priv->flags & FE_FLAG_RX_SG_DMA)
874 rxd->rxd2 = RX_DMA_PLEN0(ring->rx_buf_size);
875 else
876 rxd->rxd2 = RX_DMA_LSO;
877
878 ring->rx_calc_idx = idx;
879 wmb();
880 fe_reg_w32(ring->rx_calc_idx, FE_REG_RX_CALC_IDX0);
881 done++;
882 }
883
884 if (done < budget)
885 fe_reg_w32(rx_intr, FE_REG_FE_INT_STATUS);
886
887 return done;
888 }
889
890 static int fe_poll_tx(struct fe_priv *priv, int budget, u32 tx_intr,
891 int *tx_again)
892 {
893 struct net_device *netdev = priv->netdev;
894 struct device *dev = &netdev->dev;
895 unsigned int bytes_compl = 0;
896 struct sk_buff *skb;
897 struct fe_tx_buf *tx_buf;
898 int done = 0;
899 u32 idx, hwidx;
900 struct fe_tx_ring *ring = &priv->tx_ring;
901
902 idx = ring->tx_free_idx;
903 hwidx = fe_reg_r32(FE_REG_TX_DTX_IDX0);
904
905 while ((idx != hwidx) && budget) {
906 tx_buf = &ring->tx_buf[idx];
907 skb = tx_buf->skb;
908
909 if (!skb)
910 break;
911
912 if (skb != (struct sk_buff *) DMA_DUMMY_DESC) {
913 bytes_compl += skb->len;
914 done++;
915 budget--;
916 }
917 fe_txd_unmap(dev, tx_buf);
918 idx = NEXT_TX_DESP_IDX(idx);
919 }
920 ring->tx_free_idx = idx;
921
922 if (idx == hwidx) {
923 /* read hw index again make sure no new tx packet */
924 hwidx = fe_reg_r32(FE_REG_TX_DTX_IDX0);
925 if (idx == hwidx)
926 fe_reg_w32(tx_intr, FE_REG_FE_INT_STATUS);
927 else
928 *tx_again = 1;
929 } else
930 *tx_again = 1;
931
932 if (done) {
933 netdev_completed_queue(netdev, done, bytes_compl);
934 smp_mb();
935 if (unlikely(netif_queue_stopped(netdev) &&
936 (fe_empty_txd(ring) > ring->tx_thresh)))
937 netif_wake_queue(netdev);
938 }
939
940 return done;
941 }
942
943 static int fe_poll(struct napi_struct *napi, int budget)
944 {
945 struct fe_priv *priv = container_of(napi, struct fe_priv, rx_napi);
946 struct fe_hw_stats *hwstat = priv->hw_stats;
947 int tx_done, rx_done, tx_again;
948 u32 status, fe_status, status_reg, mask;
949 u32 tx_intr, rx_intr, status_intr;
950
951 fe_status = status = fe_reg_r32(FE_REG_FE_INT_STATUS);
952 tx_intr = priv->soc->tx_int;
953 rx_intr = priv->soc->rx_int;
954 status_intr = priv->soc->status_int;
955 tx_done = rx_done = tx_again = 0;
956
957 if (fe_reg_table[FE_REG_FE_INT_STATUS2]) {
958 fe_status = fe_reg_r32(FE_REG_FE_INT_STATUS2);
959 status_reg = FE_REG_FE_INT_STATUS2;
960 } else
961 status_reg = FE_REG_FE_INT_STATUS;
962
963 if (status & tx_intr)
964 tx_done = fe_poll_tx(priv, budget, tx_intr, &tx_again);
965
966 if (status & rx_intr)
967 rx_done = fe_poll_rx(napi, budget, priv, rx_intr);
968
969 if (unlikely(fe_status & status_intr)) {
970 if (hwstat && spin_trylock(&hwstat->stats_lock)) {
971 fe_stats_update(priv);
972 spin_unlock(&hwstat->stats_lock);
973 }
974 fe_reg_w32(status_intr, status_reg);
975 }
976
977 if (unlikely(netif_msg_intr(priv))) {
978 mask = fe_reg_r32(FE_REG_FE_INT_ENABLE);
979 netdev_info(priv->netdev,
980 "done tx %d, rx %d, intr 0x%08x/0x%x\n",
981 tx_done, rx_done, status, mask);
982 }
983
984 if (!tx_again && (rx_done < budget)) {
985 status = fe_reg_r32(FE_REG_FE_INT_STATUS);
986 if (status & (tx_intr | rx_intr ))
987 goto poll_again;
988
989 napi_complete(napi);
990 fe_int_enable(tx_intr | rx_intr);
991 }
992
993 poll_again:
994 return rx_done;
995 }
996
997 static void fe_tx_timeout(struct net_device *dev)
998 {
999 struct fe_priv *priv = netdev_priv(dev);
1000 struct fe_tx_ring *ring = &priv->tx_ring;
1001
1002 priv->netdev->stats.tx_errors++;
1003 netif_err(priv, tx_err, dev,
1004 "transmit timed out\n");
1005 netif_info(priv, drv, dev, "dma_cfg:%08x\n",
1006 fe_reg_r32(FE_REG_PDMA_GLO_CFG));
1007 netif_info(priv, drv, dev, "tx_ring=%d, " \
1008 "base=%08x, max=%u, ctx=%u, dtx=%u, fdx=%hu, next=%hu\n", 0,
1009 fe_reg_r32(FE_REG_TX_BASE_PTR0),
1010 fe_reg_r32(FE_REG_TX_MAX_CNT0),
1011 fe_reg_r32(FE_REG_TX_CTX_IDX0),
1012 fe_reg_r32(FE_REG_TX_DTX_IDX0),
1013 ring->tx_free_idx,
1014 ring->tx_next_idx
1015 );
1016 netif_info(priv, drv, dev, "rx_ring=%d, " \
1017 "base=%08x, max=%u, calc=%u, drx=%u\n", 0,
1018 fe_reg_r32(FE_REG_RX_BASE_PTR0),
1019 fe_reg_r32(FE_REG_RX_MAX_CNT0),
1020 fe_reg_r32(FE_REG_RX_CALC_IDX0),
1021 fe_reg_r32(FE_REG_RX_DRX_IDX0)
1022 );
1023
1024 if (!test_and_set_bit(FE_FLAG_RESET_PENDING, priv->pending_flags))
1025 schedule_work(&priv->pending_work);
1026 }
1027
1028 static irqreturn_t fe_handle_irq(int irq, void *dev)
1029 {
1030 struct fe_priv *priv = netdev_priv(dev);
1031 u32 status, int_mask;
1032
1033 status = fe_reg_r32(FE_REG_FE_INT_STATUS);
1034
1035 if (unlikely(!status))
1036 return IRQ_NONE;
1037
1038 int_mask = (priv->soc->rx_int | priv->soc->tx_int);
1039 if (likely(status & int_mask)) {
1040 if (likely(napi_schedule_prep(&priv->rx_napi))) {
1041 fe_int_disable(int_mask);
1042 __napi_schedule(&priv->rx_napi);
1043 }
1044 } else {
1045 fe_reg_w32(status, FE_REG_FE_INT_STATUS);
1046 }
1047
1048 return IRQ_HANDLED;
1049 }
1050
1051 #ifdef CONFIG_NET_POLL_CONTROLLER
1052 static void fe_poll_controller(struct net_device *dev)
1053 {
1054 struct fe_priv *priv = netdev_priv(dev);
1055 u32 int_mask = priv->soc->tx_int | priv->soc->rx_int;
1056
1057 fe_int_disable(int_mask);
1058 fe_handle_irq(dev->irq, dev);
1059 fe_int_enable(int_mask);
1060 }
1061 #endif
1062
1063 int fe_set_clock_cycle(struct fe_priv *priv)
1064 {
1065 unsigned long sysclk = priv->sysclk;
1066
1067 if (!sysclk) {
1068 return -EINVAL;
1069 }
1070
1071 sysclk /= FE_US_CYC_CNT_DIVISOR;
1072 sysclk <<= FE_US_CYC_CNT_SHIFT;
1073
1074 fe_w32((fe_r32(FE_FE_GLO_CFG) &
1075 ~(FE_US_CYC_CNT_MASK << FE_US_CYC_CNT_SHIFT)) |
1076 sysclk,
1077 FE_FE_GLO_CFG);
1078 return 0;
1079 }
1080
1081 void fe_fwd_config(struct fe_priv *priv)
1082 {
1083 u32 fwd_cfg;
1084
1085 fwd_cfg = fe_r32(FE_GDMA1_FWD_CFG);
1086
1087 /* disable jumbo frame */
1088 if (priv->flags & FE_FLAG_JUMBO_FRAME)
1089 fwd_cfg &= ~FE_GDM1_JMB_EN;
1090
1091 /* set unicast/multicast/broadcast frame to cpu */
1092 fwd_cfg &= ~0xffff;
1093
1094 fe_w32(fwd_cfg, FE_GDMA1_FWD_CFG);
1095 }
1096
1097 static void fe_rxcsum_config(bool enable)
1098 {
1099 if (enable)
1100 fe_w32(fe_r32(FE_GDMA1_FWD_CFG) | (FE_GDM1_ICS_EN |
1101 FE_GDM1_TCS_EN | FE_GDM1_UCS_EN),
1102 FE_GDMA1_FWD_CFG);
1103 else
1104 fe_w32(fe_r32(FE_GDMA1_FWD_CFG) & ~(FE_GDM1_ICS_EN |
1105 FE_GDM1_TCS_EN | FE_GDM1_UCS_EN),
1106 FE_GDMA1_FWD_CFG);
1107 }
1108
1109 static void fe_txcsum_config(bool enable)
1110 {
1111 if (enable)
1112 fe_w32(fe_r32(FE_CDMA_CSG_CFG) | (FE_ICS_GEN_EN |
1113 FE_TCS_GEN_EN | FE_UCS_GEN_EN),
1114 FE_CDMA_CSG_CFG);
1115 else
1116 fe_w32(fe_r32(FE_CDMA_CSG_CFG) & ~(FE_ICS_GEN_EN |
1117 FE_TCS_GEN_EN | FE_UCS_GEN_EN),
1118 FE_CDMA_CSG_CFG);
1119 }
1120
1121 void fe_csum_config(struct fe_priv *priv)
1122 {
1123 struct net_device *dev = priv_netdev(priv);
1124
1125 fe_txcsum_config((dev->features & NETIF_F_IP_CSUM));
1126 fe_rxcsum_config((dev->features & NETIF_F_RXCSUM));
1127 }
1128
1129 static int fe_hw_init(struct net_device *dev)
1130 {
1131 struct fe_priv *priv = netdev_priv(dev);
1132 int i, err;
1133
1134 err = devm_request_irq(priv->device, dev->irq, fe_handle_irq, 0,
1135 dev_name(priv->device), dev);
1136 if (err)
1137 return err;
1138
1139 if (priv->soc->set_mac)
1140 priv->soc->set_mac(priv, dev->dev_addr);
1141 else
1142 fe_hw_set_macaddr(priv, dev->dev_addr);
1143
1144 /* disable delay interrupt */
1145 fe_reg_w32(0, FE_REG_DLY_INT_CFG);
1146
1147 fe_int_disable(priv->soc->tx_int | priv->soc->rx_int);
1148
1149 /* frame engine will push VLAN tag regarding to VIDX feild in Tx desc. */
1150 if (fe_reg_table[FE_REG_FE_DMA_VID_BASE])
1151 for (i = 0; i < 16; i += 2)
1152 fe_w32(((i + 1) << 16) + i,
1153 fe_reg_table[FE_REG_FE_DMA_VID_BASE] +
1154 (i * 2));
1155
1156 BUG_ON(!priv->soc->fwd_config);
1157 if (priv->soc->fwd_config(priv))
1158 netdev_err(dev, "unable to get clock\n");
1159
1160 if (fe_reg_table[FE_REG_FE_RST_GL]) {
1161 fe_reg_w32(1, FE_REG_FE_RST_GL);
1162 fe_reg_w32(0, FE_REG_FE_RST_GL);
1163 }
1164
1165 return 0;
1166 }
1167
1168 static int fe_open(struct net_device *dev)
1169 {
1170 struct fe_priv *priv = netdev_priv(dev);
1171 unsigned long flags;
1172 u32 val;
1173 int err;
1174
1175 err = fe_init_dma(priv);
1176 if (err)
1177 goto err_out;
1178
1179 spin_lock_irqsave(&priv->page_lock, flags);
1180
1181 val = FE_TX_WB_DDONE | FE_RX_DMA_EN | FE_TX_DMA_EN;
1182 if (priv->flags & FE_FLAG_RX_2B_OFFSET)
1183 val |= FE_RX_2B_OFFSET;
1184 val |= priv->soc->pdma_glo_cfg;
1185 fe_reg_w32(val, FE_REG_PDMA_GLO_CFG);
1186
1187 spin_unlock_irqrestore(&priv->page_lock, flags);
1188
1189 if (priv->phy)
1190 priv->phy->start(priv);
1191
1192 if (priv->soc->has_carrier && priv->soc->has_carrier(priv))
1193 netif_carrier_on(dev);
1194
1195 napi_enable(&priv->rx_napi);
1196 fe_int_enable(priv->soc->tx_int | priv->soc->rx_int);
1197 netif_start_queue(dev);
1198
1199 return 0;
1200
1201 err_out:
1202 fe_free_dma(priv);
1203 return err;
1204 }
1205
1206 static int fe_stop(struct net_device *dev)
1207 {
1208 struct fe_priv *priv = netdev_priv(dev);
1209 unsigned long flags;
1210 int i;
1211
1212 netif_tx_disable(dev);
1213 fe_int_disable(priv->soc->tx_int | priv->soc->rx_int);
1214 napi_disable(&priv->rx_napi);
1215
1216 if (priv->phy)
1217 priv->phy->stop(priv);
1218
1219 spin_lock_irqsave(&priv->page_lock, flags);
1220
1221 fe_reg_w32(fe_reg_r32(FE_REG_PDMA_GLO_CFG) &
1222 ~(FE_TX_WB_DDONE | FE_RX_DMA_EN | FE_TX_DMA_EN),
1223 FE_REG_PDMA_GLO_CFG);
1224 spin_unlock_irqrestore(&priv->page_lock, flags);
1225
1226 /* wait dma stop */
1227 for (i = 0; i < 10; i++) {
1228 if (fe_reg_r32(FE_REG_PDMA_GLO_CFG) &
1229 (FE_TX_DMA_BUSY | FE_RX_DMA_BUSY)) {
1230 msleep(10);
1231 continue;
1232 }
1233 break;
1234 }
1235
1236 fe_free_dma(priv);
1237
1238 return 0;
1239 }
1240
1241 static int __init fe_init(struct net_device *dev)
1242 {
1243 struct fe_priv *priv = netdev_priv(dev);
1244 struct device_node *port;
1245 int err;
1246
1247 BUG_ON(!priv->soc->reset_fe);
1248 priv->soc->reset_fe();
1249
1250 if (priv->soc->switch_init)
1251 priv->soc->switch_init(priv);
1252
1253 of_get_mac_address_mtd(priv->device->of_node, dev->dev_addr);
1254 /*If the mac address is invalid, use random mac address */
1255 if (!is_valid_ether_addr(dev->dev_addr)) {
1256 random_ether_addr(dev->dev_addr);
1257 dev_err(priv->device, "generated random MAC address %pM\n",
1258 dev->dev_addr);
1259 }
1260
1261 err = fe_mdio_init(priv);
1262 if (err)
1263 return err;
1264
1265 if (priv->soc->port_init)
1266 for_each_child_of_node(priv->device->of_node, port)
1267 if (of_device_is_compatible(port, "ralink,eth-port") && of_device_is_available(port))
1268 priv->soc->port_init(priv, port);
1269
1270 if (priv->phy) {
1271 err = priv->phy->connect(priv);
1272 if (err)
1273 goto err_phy_disconnect;
1274 }
1275
1276 err = fe_hw_init(dev);
1277 if (err)
1278 goto err_phy_disconnect;
1279
1280 if (priv->soc->switch_config)
1281 priv->soc->switch_config(priv);
1282
1283 return 0;
1284
1285 err_phy_disconnect:
1286 if (priv->phy)
1287 priv->phy->disconnect(priv);
1288 fe_mdio_cleanup(priv);
1289
1290 return err;
1291 }
1292
1293 static void fe_uninit(struct net_device *dev)
1294 {
1295 struct fe_priv *priv = netdev_priv(dev);
1296
1297 if (priv->phy)
1298 priv->phy->disconnect(priv);
1299 fe_mdio_cleanup(priv);
1300
1301 fe_reg_w32(0, FE_REG_FE_INT_ENABLE);
1302 free_irq(dev->irq, dev);
1303 }
1304
1305 static int fe_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1306 {
1307 struct fe_priv *priv = netdev_priv(dev);
1308
1309 if (!priv->phy_dev)
1310 return -ENODEV;
1311
1312 switch (cmd) {
1313 case SIOCETHTOOL:
1314 return phy_ethtool_ioctl(priv->phy_dev,
1315 (void *) ifr->ifr_data);
1316 case SIOCGMIIPHY:
1317 case SIOCGMIIREG:
1318 case SIOCSMIIREG:
1319 return phy_mii_ioctl(priv->phy_dev, ifr, cmd);
1320 default:
1321 break;
1322 }
1323
1324 return -EOPNOTSUPP;
1325 }
1326
1327 static int fe_change_mtu(struct net_device *dev, int new_mtu)
1328 {
1329 struct fe_priv *priv = netdev_priv(dev);
1330 int frag_size, old_mtu;
1331 u32 fwd_cfg;
1332
1333 if (!(priv->flags & FE_FLAG_JUMBO_FRAME))
1334 return eth_change_mtu(dev, new_mtu);
1335
1336 frag_size = fe_max_frag_size(new_mtu);
1337 if (new_mtu < 68 || frag_size > PAGE_SIZE)
1338 return -EINVAL;
1339
1340 old_mtu = dev->mtu;
1341 dev->mtu = new_mtu;
1342
1343 /* return early if the buffer sizes will not change */
1344 if (old_mtu <= ETH_DATA_LEN && new_mtu <= ETH_DATA_LEN)
1345 return 0;
1346 if (old_mtu > ETH_DATA_LEN && new_mtu > ETH_DATA_LEN)
1347 return 0;
1348
1349 if (new_mtu <= ETH_DATA_LEN)
1350 priv->rx_ring.frag_size = fe_max_frag_size(ETH_DATA_LEN);
1351 else
1352 priv->rx_ring.frag_size = PAGE_SIZE;
1353 priv->rx_ring.rx_buf_size = fe_max_buf_size(priv->rx_ring.frag_size);
1354
1355 if (!netif_running(dev))
1356 return 0;
1357
1358 fe_stop(dev);
1359 fwd_cfg = fe_r32(FE_GDMA1_FWD_CFG);
1360 if (new_mtu <= ETH_DATA_LEN)
1361 fwd_cfg &= ~FE_GDM1_JMB_EN;
1362 else {
1363 fwd_cfg &= ~(FE_GDM1_JMB_LEN_MASK << FE_GDM1_JMB_LEN_SHIFT);
1364 fwd_cfg |= (DIV_ROUND_UP(frag_size, 1024) <<
1365 FE_GDM1_JMB_LEN_SHIFT) | FE_GDM1_JMB_EN;
1366 }
1367 fe_w32(fwd_cfg, FE_GDMA1_FWD_CFG);
1368
1369 return fe_open(dev);
1370 }
1371
1372 static const struct net_device_ops fe_netdev_ops = {
1373 .ndo_init = fe_init,
1374 .ndo_uninit = fe_uninit,
1375 .ndo_open = fe_open,
1376 .ndo_stop = fe_stop,
1377 .ndo_start_xmit = fe_start_xmit,
1378 .ndo_set_mac_address = fe_set_mac_address,
1379 .ndo_validate_addr = eth_validate_addr,
1380 .ndo_do_ioctl = fe_do_ioctl,
1381 .ndo_change_mtu = fe_change_mtu,
1382 .ndo_tx_timeout = fe_tx_timeout,
1383 .ndo_get_stats64 = fe_get_stats64,
1384 .ndo_vlan_rx_add_vid = fe_vlan_rx_add_vid,
1385 .ndo_vlan_rx_kill_vid = fe_vlan_rx_kill_vid,
1386 #ifdef CONFIG_NET_POLL_CONTROLLER
1387 .ndo_poll_controller = fe_poll_controller,
1388 #endif
1389 };
1390
1391 static void fe_reset_pending(struct fe_priv *priv)
1392 {
1393 struct net_device *dev = priv->netdev;
1394 int err;
1395
1396 rtnl_lock();
1397 fe_stop(dev);
1398
1399 err = fe_open(dev);
1400 if (err)
1401 goto error;
1402 rtnl_unlock();
1403
1404 return;
1405 error:
1406 netif_alert(priv, ifup, dev,
1407 "Driver up/down cycle failed, closing device.\n");
1408 dev_close(dev);
1409 rtnl_unlock();
1410 }
1411
1412 static const struct fe_work_t fe_work[] = {
1413 {FE_FLAG_RESET_PENDING, fe_reset_pending},
1414 };
1415
1416 static void fe_pending_work(struct work_struct *work)
1417 {
1418 struct fe_priv *priv = container_of(work, struct fe_priv, pending_work);
1419 int i;
1420 bool pending;
1421
1422 for (i = 0; i < ARRAY_SIZE(fe_work); i++) {
1423 pending = test_and_clear_bit(fe_work[i].bitnr,
1424 priv->pending_flags);
1425 if (pending)
1426 fe_work[i].action(priv);
1427 }
1428 }
1429
1430 static int fe_probe(struct platform_device *pdev)
1431 {
1432 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1433 const struct of_device_id *match;
1434 struct fe_soc_data *soc;
1435 struct net_device *netdev;
1436 struct fe_priv *priv;
1437 struct clk *sysclk;
1438 int err, napi_weight;
1439
1440 device_reset(&pdev->dev);
1441
1442 match = of_match_device(of_fe_match, &pdev->dev);
1443 soc = (struct fe_soc_data *) match->data;
1444
1445 if (soc->reg_table)
1446 fe_reg_table = soc->reg_table;
1447 else
1448 soc->reg_table = fe_reg_table;
1449
1450 fe_base = devm_ioremap_resource(&pdev->dev, res);
1451 if (!fe_base) {
1452 err = -EADDRNOTAVAIL;
1453 goto err_out;
1454 }
1455
1456 netdev = alloc_etherdev(sizeof(*priv));
1457 if (!netdev) {
1458 dev_err(&pdev->dev, "alloc_etherdev failed\n");
1459 err = -ENOMEM;
1460 goto err_iounmap;
1461 }
1462
1463 SET_NETDEV_DEV(netdev, &pdev->dev);
1464 netdev->netdev_ops = &fe_netdev_ops;
1465 netdev->base_addr = (unsigned long) fe_base;
1466
1467 netdev->irq = platform_get_irq(pdev, 0);
1468 if (netdev->irq < 0) {
1469 dev_err(&pdev->dev, "no IRQ resource found\n");
1470 err = -ENXIO;
1471 goto err_free_dev;
1472 }
1473
1474 if (soc->init_data)
1475 soc->init_data(soc, netdev);
1476 /* fake NETIF_F_HW_VLAN_CTAG_RX for good GRO performance */
1477 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX;
1478 netdev->vlan_features = netdev->hw_features &
1479 ~(NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX);
1480 netdev->features |= netdev->hw_features;
1481
1482 /* fake rx vlan filter func. to support tx vlan offload func */
1483 if (fe_reg_table[FE_REG_FE_DMA_VID_BASE])
1484 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
1485
1486 priv = netdev_priv(netdev);
1487 spin_lock_init(&priv->page_lock);
1488 if (fe_reg_table[FE_REG_FE_COUNTER_BASE]) {
1489 priv->hw_stats = kzalloc(sizeof(*priv->hw_stats), GFP_KERNEL);
1490 if (!priv->hw_stats) {
1491 err = -ENOMEM;
1492 goto err_free_dev;
1493 }
1494 spin_lock_init(&priv->hw_stats->stats_lock);
1495 }
1496
1497 sysclk = devm_clk_get(&pdev->dev, NULL);
1498 if (!IS_ERR(sysclk))
1499 priv->sysclk = clk_get_rate(sysclk);
1500
1501 priv->netdev = netdev;
1502 priv->device = &pdev->dev;
1503 priv->soc = soc;
1504 priv->msg_enable = netif_msg_init(fe_msg_level, FE_DEFAULT_MSG_ENABLE);
1505 priv->rx_ring.frag_size = fe_max_frag_size(ETH_DATA_LEN);
1506 priv->rx_ring.rx_buf_size = fe_max_buf_size(priv->rx_ring.frag_size);
1507 priv->tx_ring.tx_ring_size = priv->rx_ring.rx_ring_size = NUM_DMA_DESC;
1508 INIT_WORK(&priv->pending_work, fe_pending_work);
1509
1510 napi_weight = 32;
1511 if (priv->flags & FE_FLAG_NAPI_WEIGHT) {
1512 napi_weight *= 4;
1513 priv->tx_ring.tx_ring_size *= 4;
1514 priv->rx_ring.rx_ring_size *= 4;
1515 }
1516 netif_napi_add(netdev, &priv->rx_napi, fe_poll, napi_weight);
1517 fe_set_ethtool_ops(netdev);
1518
1519 err = register_netdev(netdev);
1520 if (err) {
1521 dev_err(&pdev->dev, "error bringing up device\n");
1522 goto err_free_dev;
1523 }
1524
1525 platform_set_drvdata(pdev, netdev);
1526
1527 netif_info(priv, probe, netdev, "ralink at 0x%08lx, irq %d\n",
1528 netdev->base_addr, netdev->irq);
1529
1530 return 0;
1531
1532 err_free_dev:
1533 free_netdev(netdev);
1534 err_iounmap:
1535 devm_iounmap(&pdev->dev, fe_base);
1536 err_out:
1537 return err;
1538 }
1539
1540 static int fe_remove(struct platform_device *pdev)
1541 {
1542 struct net_device *dev = platform_get_drvdata(pdev);
1543 struct fe_priv *priv = netdev_priv(dev);
1544
1545 netif_napi_del(&priv->rx_napi);
1546 if (priv->hw_stats)
1547 kfree(priv->hw_stats);
1548
1549 cancel_work_sync(&priv->pending_work);
1550
1551 unregister_netdev(dev);
1552 free_netdev(dev);
1553 platform_set_drvdata(pdev, NULL);
1554
1555 return 0;
1556 }
1557
1558 static struct platform_driver fe_driver = {
1559 .probe = fe_probe,
1560 .remove = fe_remove,
1561 .driver = {
1562 .name = "ralink_soc_eth",
1563 .owner = THIS_MODULE,
1564 .of_match_table = of_fe_match,
1565 },
1566 };
1567
1568 static int __init init_rtfe(void)
1569 {
1570 int ret;
1571
1572 ret = rtesw_init();
1573 if (ret)
1574 return ret;
1575
1576 ret = platform_driver_register(&fe_driver);
1577 if (ret)
1578 rtesw_exit();
1579
1580 return ret;
1581 }
1582
1583 static void __exit exit_rtfe(void)
1584 {
1585 platform_driver_unregister(&fe_driver);
1586 rtesw_exit();
1587 }
1588
1589 module_init(init_rtfe);
1590 module_exit(exit_rtfe);
1591
1592 MODULE_LICENSE("GPL");
1593 MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
1594 MODULE_DESCRIPTION("Ethernet driver for Ralink SoC");
1595 MODULE_VERSION(FE_DRV_VERSION);
OpenWrt Source Repository