target/linux/ramips/files/drivers/net/ethernet/ralink/soc_mt7620.c

   1 /*   This program is free software; you can redistribute it and/or modify
   2  *   it under the terms of the GNU General Public License as published by
   3  *   the Free Software Foundation; version 2 of the License
   4  *
   5  *   This program is distributed in the hope that it will be useful,
   6  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
   7  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   8  *   GNU General Public License for more details.
   9  *
  10  *   Copyright (C) 2009-2015 John Crispin <blogic@openwrt.org>
  11  *   Copyright (C) 2009-2015 Felix Fietkau <nbd@nbd.name>
  12  *   Copyright (C) 2013-2015 Michael Lee <igvtee@gmail.com>
  13  */
  14
  15 #include <linux/module.h>
  16 #include <linux/platform_device.h>
  17 #include <linux/if_vlan.h>
  18 #include <linux/of_net.h>
  19
  20 #include <asm/mach-ralink/ralink_regs.h>
  21
  22 #include <mt7620.h>
  23 #include "mtk_eth_soc.h"
  24 #include "gsw_mt7620.h"
  25 #include "mt7530.h"
  26 #include "mdio.h"
  27
  28 #define MT7620A_CDMA_CSG_CFG    0x400
  29 #define MT7620_DMA_VID          (MT7620A_CDMA_CSG_CFG | 0x30)
  30 #define MT7620_L4_VALID         BIT(23)
  31
  32 #define MT7620_TX_DMA_UDF       BIT(15)
  33 #define TX_DMA_FP_BMAP          ((0xff) << 19)
  34
  35 #define CDMA_ICS_EN             BIT(2)
  36 #define CDMA_UCS_EN             BIT(1)
  37 #define CDMA_TCS_EN             BIT(0)
  38
  39 #define GDMA_ICS_EN             BIT(22)
  40 #define GDMA_TCS_EN             BIT(21)
  41 #define GDMA_UCS_EN             BIT(20)
  42
  43 /* frame engine counters */
  44 #define MT7620_REG_MIB_OFFSET   0x1000
  45 #define MT7620_PPE_AC_BCNT0     (MT7620_REG_MIB_OFFSET + 0x00)
  46 #define MT7620_GDM1_TX_GBCNT    (MT7620_REG_MIB_OFFSET + 0x300)
  47 #define MT7620_GDM2_TX_GBCNT    (MT7620_GDM1_TX_GBCNT + 0x40)
  48
  49 #define GSW_REG_GDMA1_MAC_ADRL  0x508
  50 #define GSW_REG_GDMA1_MAC_ADRH  0x50C
  51
  52 #define MT7621_FE_RST_GL        (FE_FE_OFFSET + 0x04)
  53 #define MT7620_FE_INT_STATUS2   (FE_FE_OFFSET + 0x08)
  54
  55 /* FE_INT_STATUS reg on mt7620 define CNT_GDM1_AF at BIT(29)
  56  * but after test it should be BIT(13).
  57  */
  58 #define MT7620_FE_GDM1_AF       BIT(13)
  59
  60 static const u16 mt7620_reg_table[FE_REG_COUNT] = {
  61         [FE_REG_PDMA_GLO_CFG] = RT5350_PDMA_GLO_CFG,
  62         [FE_REG_PDMA_RST_CFG] = RT5350_PDMA_RST_CFG,
  63         [FE_REG_DLY_INT_CFG] = RT5350_DLY_INT_CFG,
  64         [FE_REG_TX_BASE_PTR0] = RT5350_TX_BASE_PTR0,
  65         [FE_REG_TX_MAX_CNT0] = RT5350_TX_MAX_CNT0,
  66         [FE_REG_TX_CTX_IDX0] = RT5350_TX_CTX_IDX0,
  67         [FE_REG_TX_DTX_IDX0] = RT5350_TX_DTX_IDX0,
  68         [FE_REG_RX_BASE_PTR0] = RT5350_RX_BASE_PTR0,
  69         [FE_REG_RX_MAX_CNT0] = RT5350_RX_MAX_CNT0,
  70         [FE_REG_RX_CALC_IDX0] = RT5350_RX_CALC_IDX0,
  71         [FE_REG_RX_DRX_IDX0] = RT5350_RX_DRX_IDX0,
  72         [FE_REG_FE_INT_ENABLE] = RT5350_FE_INT_ENABLE,
  73         [FE_REG_FE_INT_STATUS] = RT5350_FE_INT_STATUS,
  74         [FE_REG_FE_DMA_VID_BASE] = MT7620_DMA_VID,
  75         [FE_REG_FE_COUNTER_BASE] = MT7620_GDM1_TX_GBCNT,
  76         [FE_REG_FE_RST_GL] = MT7621_FE_RST_GL,
  77         [FE_REG_FE_INT_STATUS2] = MT7620_FE_INT_STATUS2,
  78 };
  79
  80 static int mt7620_gsw_config(struct fe_priv *priv)
  81 {
  82         struct mt7620_gsw *gsw = (struct mt7620_gsw *) priv->soc->swpriv;
  83         u32 val;
  84
  85         /* is the mt7530 internal or external */
  86         if (priv->mii_bus && mdiobus_get_phy(priv->mii_bus, 0x1f)) {
  87                 mt7530_probe(priv->dev, gsw->base, NULL, 0);
  88                 mt7530_probe(priv->dev, NULL, priv->mii_bus, 1);
  89
  90                 /* magic values from original SDK */
  91                 val = mt7530_mdio_r32(gsw, 0x7830);
  92                 val &= ~BIT(0);
  93                 val |= BIT(1);
  94                 mt7530_mdio_w32(gsw, 0x7830, val);
  95
  96                 val = mt7530_mdio_r32(gsw, 0x7a40);
  97                 val &= ~BIT(30);
  98                 mt7530_mdio_w32(gsw, 0x7a40, val);
  99
 100                 mt7530_mdio_w32(gsw, 0x7a78, 0x855);
 101
 102                 pr_info("mt7530: mdio central align\n");
 103         } else {
 104                 mt7530_probe(priv->dev, gsw->base, NULL, 1);
 105         }
 106
 107         return 0;
 108 }
 109
 110 static void mt7620_set_mac(struct fe_priv *priv, unsigned char *mac)
 111 {
 112         struct mt7620_gsw *gsw = (struct mt7620_gsw *)priv->soc->swpriv;
 113         unsigned long flags;
 114
 115         spin_lock_irqsave(&priv->page_lock, flags);
 116         mtk_switch_w32(gsw, (mac[0] << 8) | mac[1], GSW_REG_SMACCR1);
 117         mtk_switch_w32(gsw, (mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5],
 118                 GSW_REG_SMACCR0);
 119         spin_unlock_irqrestore(&priv->page_lock, flags);
 120 }
 121
 122 static void mt7620_auto_poll(struct mt7620_gsw *gsw, int port)
 123 {
 124         int phy;
 125         int lsb = -1, msb = 0;
 126
 127         for_each_set_bit(phy, &gsw->autopoll, 32) {
 128                 if (lsb < 0)
 129                         lsb = phy;
 130                 msb = phy;
 131         }
 132
 133         if (lsb == msb && port ==  4)
 134                 msb++;
 135         else if (lsb == msb && port ==  5)
 136                 lsb--;
 137
 138         mtk_switch_w32(gsw, PHY_AN_EN | PHY_PRE_EN | PMY_MDC_CONF(5) |
 139                 (msb << 8) | lsb, ESW_PHY_POLLING);
 140 }
 141
 142 static void mt7620_port_init(struct fe_priv *priv, struct device_node *np)
 143 {
 144         struct mt7620_gsw *gsw = (struct mt7620_gsw *)priv->soc->swpriv;
 145         const __be32 *_id = of_get_property(np, "reg", NULL);
 146         const __be32 *phy_addr;
 147 #if LINUX_VERSION_CODE < KERNEL_VERSION(5, 10, 0)
 148         int phy_mode;
 149 #else
 150         phy_interface_t phy_mode = PHY_INTERFACE_MODE_NA;
 151 #endif
 152         int size, id;
 153         int shift = 12;
 154         u32 val, mask = 0;
 155         u32 val_delay = 0;
 156         u32 mask_delay = GSW_REG_GPCx_TXDELAY | GSW_REG_GPCx_RXDELAY;
 157         int min = (gsw->port4_ephy) ? (5) : (4);
 158
 159         if (!_id || (be32_to_cpu(*_id) < min) || (be32_to_cpu(*_id) > 5)) {
 160                 if (_id)
 161                         pr_err("%s: invalid port id %d\n", np->name,
 162                                be32_to_cpu(*_id));
 163                 else
 164                         pr_err("%s: invalid port id\n", np->name);
 165                 return;
 166         }
 167
 168         id = be32_to_cpu(*_id);
 169
 170         if (id == 4)
 171                 shift = 14;
 172
 173         priv->phy->phy_fixed[id] = of_get_property(np, "mediatek,fixed-link",
 174                                                    &size);
 175         if (priv->phy->phy_fixed[id] &&
 176             (size != (4 * sizeof(*priv->phy->phy_fixed[id])))) {
 177                 pr_err("%s: invalid fixed link property\n", np->name);
 178                 priv->phy->phy_fixed[id] = NULL;
 179         }
 180
 181 #if LINUX_VERSION_CODE < KERNEL_VERSION(5, 10, 0)
 182         phy_mode = of_get_phy_mode(np);
 183 #else
 184         of_get_phy_mode(np, &phy_mode);
 185 #endif
 186         switch (phy_mode) {
 187         case PHY_INTERFACE_MODE_RGMII:
 188                 mask = 0;
 189                 /* Do not touch rx/tx delay in this state to avoid problems with
 190                  * backward compability.
 191                  */
 192                 mask_delay = 0;
 193                 break;
 194         case PHY_INTERFACE_MODE_RGMII_ID:
 195                 mask = 0;
 196                 val_delay |= GSW_REG_GPCx_TXDELAY;
 197                 val_delay &= ~GSW_REG_GPCx_RXDELAY;
 198                 break;
 199         case PHY_INTERFACE_MODE_RGMII_RXID:
 200                 mask = 0;
 201                 val_delay &= ~GSW_REG_GPCx_TXDELAY;
 202                 val_delay &= ~GSW_REG_GPCx_RXDELAY;
 203                 break;
 204         case PHY_INTERFACE_MODE_RGMII_TXID:
 205                 mask = 0;
 206                 val_delay |= GSW_REG_GPCx_TXDELAY;
 207                 val_delay |= GSW_REG_GPCx_RXDELAY;
 208                 break;
 209         case PHY_INTERFACE_MODE_MII:
 210                 mask = 1;
 211                 break;
 212         case PHY_INTERFACE_MODE_RMII:
 213                 mask = 2;
 214                 break;
 215         default:
 216                 dev_err(priv->dev, "port %d - invalid phy mode\n", id);
 217                 return;
 218         }
 219
 220         val = rt_sysc_r32(SYSC_REG_CFG1);
 221         val &= ~(3 << shift);
 222         val |= mask << shift;
 223         rt_sysc_w32(val, SYSC_REG_CFG1);
 224
 225         if (id == 4) {
 226                 val = mtk_switch_r32(gsw, GSW_REG_GPC2);
 227                 val &= ~(mask_delay);
 228                 val |= val_delay & mask_delay;
 229                 mtk_switch_w32(gsw, val, GSW_REG_GPC2);
 230         }
 231         else if (id == 5) {
 232                 val = mtk_switch_r32(gsw, GSW_REG_GPC1);
 233                 val &= ~(mask_delay);
 234                 val |= val_delay & mask_delay;
 235                 mtk_switch_w32(gsw, val, GSW_REG_GPC1);
 236         }
 237
 238         if (priv->phy->phy_fixed[id]) {
 239                 const __be32 *link = priv->phy->phy_fixed[id];
 240                 int tx_fc, rx_fc;
 241                 u32 val = 0;
 242
 243                 priv->phy->speed[id] = be32_to_cpup(link++);
 244                 tx_fc = be32_to_cpup(link++);
 245                 rx_fc = be32_to_cpup(link++);
 246                 priv->phy->duplex[id] = be32_to_cpup(link++);
 247                 priv->link[id] = 1;
 248
 249                 switch (priv->phy->speed[id]) {
 250                 case SPEED_10:
 251                         val = 0;
 252                         break;
 253                 case SPEED_100:
 254                         val = 1;
 255                         break;
 256                 case SPEED_1000:
 257                         val = 2;
 258                         break;
 259                 default:
 260                         dev_err(priv->dev, "port %d - invalid link speed: %d\n",
 261                                 id, priv->phy->speed[id]);
 262                         priv->phy->phy_fixed[id] = 0;
 263                         return;
 264                 }
 265                 val = PMCR_SPEED(val);
 266                 val |= PMCR_LINK | PMCR_BACKPRES | PMCR_BACKOFF | PMCR_RX_EN |
 267                         PMCR_TX_EN | PMCR_FORCE | PMCR_MAC_MODE | PMCR_IPG;
 268                 if (tx_fc)
 269                         val |= PMCR_TX_FC;
 270                 if (rx_fc)
 271                         val |= PMCR_RX_FC;
 272                 if (priv->phy->duplex[id])
 273                         val |= PMCR_DUPLEX;
 274                 mtk_switch_w32(gsw, val, GSW_REG_PORT_PMCR(id));
 275                 dev_info(priv->dev, "port %d - using fixed link parameters\n", id);
 276                 return;
 277         }
 278
 279         priv->phy->phy_node[id] = of_parse_phandle(np, "phy-handle", 0);
 280         if (!priv->phy->phy_node[id]) {
 281                 dev_err(priv->dev, "port %d - missing phy handle\n", id);
 282                 return;
 283         }
 284
 285         phy_addr = of_get_property(priv->phy->phy_node[id], "reg", NULL);
 286         if (phy_addr && mdiobus_get_phy(priv->mii_bus, be32_to_cpup(phy_addr))) {
 287                 u32 val = PMCR_BACKPRES | PMCR_BACKOFF | PMCR_RX_EN |
 288                         PMCR_TX_EN |  PMCR_MAC_MODE | PMCR_IPG;
 289
 290                 mtk_switch_w32(gsw, val, GSW_REG_PORT_PMCR(id));
 291                 fe_connect_phy_node(priv, priv->phy->phy_node[id], id);
 292                 gsw->autopoll |= BIT(be32_to_cpup(phy_addr));
 293                 mt7620_auto_poll(gsw,id);
 294         }
 295 }
 296
 297 static void mt7620_fe_reset(struct fe_priv *priv)
 298 {
 299         fe_reset(MT7620A_RESET_FE | MT7620A_RESET_ESW);
 300 }
 301
 302 static void mt7620_rxcsum_config(bool enable)
 303 {
 304         if (enable)
 305                 fe_w32(fe_r32(MT7620A_GDMA1_FWD_CFG) | (GDMA_ICS_EN |
 306                                         GDMA_TCS_EN | GDMA_UCS_EN),
 307                                 MT7620A_GDMA1_FWD_CFG);
 308         else
 309                 fe_w32(fe_r32(MT7620A_GDMA1_FWD_CFG) & ~(GDMA_ICS_EN |
 310                                         GDMA_TCS_EN | GDMA_UCS_EN),
 311                                 MT7620A_GDMA1_FWD_CFG);
 312 }
 313
 314 static void mt7620_txcsum_config(bool enable)
 315 {
 316         if (enable)
 317                 fe_w32(fe_r32(MT7620A_CDMA_CSG_CFG) | (CDMA_ICS_EN |
 318                                         CDMA_UCS_EN | CDMA_TCS_EN),
 319                                 MT7620A_CDMA_CSG_CFG);
 320         else
 321                 fe_w32(fe_r32(MT7620A_CDMA_CSG_CFG) & ~(CDMA_ICS_EN |
 322                                         CDMA_UCS_EN | CDMA_TCS_EN),
 323                                 MT7620A_CDMA_CSG_CFG);
 324 }
 325
 326 static int mt7620_fwd_config(struct fe_priv *priv)
 327 {
 328         struct net_device *dev = priv_netdev(priv);
 329
 330         fe_w32(fe_r32(MT7620A_GDMA1_FWD_CFG) & ~7, MT7620A_GDMA1_FWD_CFG);
 331
 332         mt7620_txcsum_config((dev->features & NETIF_F_IP_CSUM));
 333         mt7620_rxcsum_config((dev->features & NETIF_F_RXCSUM));
 334
 335         return 0;
 336 }
 337
 338 static void mt7620_tx_dma(struct fe_tx_dma *txd)
 339 {
 340 }
 341
 342 static void mt7620_init_data(struct fe_soc_data *data,
 343                              struct net_device *netdev)
 344 {
 345         struct fe_priv *priv = netdev_priv(netdev);
 346
 347         priv->flags = FE_FLAG_PADDING_64B | FE_FLAG_RX_2B_OFFSET |
 348                 FE_FLAG_RX_SG_DMA | FE_FLAG_HAS_SWITCH;
 349
 350         netdev->hw_features = NETIF_F_IP_CSUM | NETIF_F_RXCSUM |
 351                 NETIF_F_HW_VLAN_CTAG_TX;
 352         if (mt7620_get_eco() >= 5)
 353                 netdev->hw_features |= NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6 |
 354                         NETIF_F_IPV6_CSUM;
 355 }
 356
 357 static struct fe_soc_data mt7620_data = {
 358         .init_data = mt7620_init_data,
 359         .reset_fe = mt7620_fe_reset,
 360         .set_mac = mt7620_set_mac,
 361         .fwd_config = mt7620_fwd_config,
 362         .tx_dma = mt7620_tx_dma,
 363         .switch_init = mtk_gsw_init,
 364         .switch_config = mt7620_gsw_config,
 365         .port_init = mt7620_port_init,
 366         .reg_table = mt7620_reg_table,
 367         .pdma_glo_cfg = FE_PDMA_SIZE_16DWORDS,
 368         .rx_int = RT5350_RX_DONE_INT,
 369         .tx_int = RT5350_TX_DONE_INT,
 370         .status_int = MT7620_FE_GDM1_AF,
 371         .checksum_bit = MT7620_L4_VALID,
 372         .has_carrier = mt7620_has_carrier,
 373         .mdio_read = mt7620_mdio_read,
 374         .mdio_write = mt7620_mdio_write,
 375         .mdio_adjust_link = mt7620_mdio_link_adjust,
 376 };
 377
 378 const struct of_device_id of_fe_match[] = {
 379         { .compatible = "mediatek,mt7620-eth", .data = &mt7620_data },
 380         {},
 381 };
 382
 383 MODULE_DEVICE_TABLE(of, of_fe_match);