2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License as published by
4 * the Free Software Foundation; version 2 of the License
6 * This program is distributed in the hope that it will be useful,
7 * but WITHOUT ANY WARRANTY; without even the implied warranty of
8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9 * GNU General Public License for more details.
11 * You should have received a copy of the GNU General Public License
12 * along with this program; if not, write to the Free Software
13 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
15 * Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
18 #include <linux/module.h>
19 #include <linux/platform_device.h>
20 #include <linux/if_vlan.h>
22 #include <asm/mach-ralink/ralink_regs.h>
25 #include "ralink_soc_eth.h"
26 #include "gsw_mt7620a.h"
28 #define MT7620A_CDMA_CSG_CFG 0x400
29 #define MT7620_DMA_VID (MT7620A_CDMA_CSG_CFG | 0x30)
30 #define MT7621_DMA_VID 0xa8
31 #define MT7620A_RESET_FE BIT(21)
32 #define MT7621_RESET_FE BIT(6)
33 #define MT7620A_RESET_ESW BIT(23)
34 #define MT7620_L4_VALID BIT(23)
35 #define MT7621_L4_VALID BIT(24)
37 #define MT7620_TX_DMA_UDF BIT(15)
38 #define MT7621_TX_DMA_UDF BIT(19)
39 #define TX_DMA_FP_BMAP ((0xff) << 19)
41 #define CDMA_ICS_EN BIT(2)
42 #define CDMA_UCS_EN BIT(1)
43 #define CDMA_TCS_EN BIT(0)
45 #define GDMA_ICS_EN BIT(22)
46 #define GDMA_TCS_EN BIT(21)
47 #define GDMA_UCS_EN BIT(20)
49 /* frame engine counters */
50 #define MT7620_REG_MIB_OFFSET 0x1000
51 #define MT7620_PPE_AC_BCNT0 (MT7620_REG_MIB_OFFSET + 0x00)
52 #define MT7620_GDM1_TX_GBCNT (MT7620_REG_MIB_OFFSET + 0x300)
53 #define MT7620_GDM2_TX_GBCNT (MT7620_GDM1_TX_GBCNT + 0x40)
55 #define MT7621_REG_MIB_OFFSET 0x2000
56 #define MT7621_PPE_AC_BCNT0 (MT7621_REG_MIB_OFFSET + 0x00)
57 #define MT7621_GDM1_TX_GBCNT (MT7621_REG_MIB_OFFSET + 0x400)
58 #define MT7621_GDM2_TX_GBCNT (MT7621_GDM1_TX_GBCNT + 0x40)
60 #define GSW_REG_GDMA1_MAC_ADRL 0x508
61 #define GSW_REG_GDMA1_MAC_ADRH 0x50C
63 #define MT7621_FE_RST_GL (FE_FE_OFFSET + 0x04)
65 static const u32 mt7620_reg_table
[FE_REG_COUNT
] = {
66 [FE_REG_PDMA_GLO_CFG
] = RT5350_PDMA_GLO_CFG
,
67 [FE_REG_PDMA_RST_CFG
] = RT5350_PDMA_RST_CFG
,
68 [FE_REG_DLY_INT_CFG
] = RT5350_DLY_INT_CFG
,
69 [FE_REG_TX_BASE_PTR0
] = RT5350_TX_BASE_PTR0
,
70 [FE_REG_TX_MAX_CNT0
] = RT5350_TX_MAX_CNT0
,
71 [FE_REG_TX_CTX_IDX0
] = RT5350_TX_CTX_IDX0
,
72 [FE_REG_TX_DTX_IDX0
] = RT5350_TX_DTX_IDX0
,
73 [FE_REG_RX_BASE_PTR0
] = RT5350_RX_BASE_PTR0
,
74 [FE_REG_RX_MAX_CNT0
] = RT5350_RX_MAX_CNT0
,
75 [FE_REG_RX_CALC_IDX0
] = RT5350_RX_CALC_IDX0
,
76 [FE_REG_RX_DRX_IDX0
] = RT5350_RX_DRX_IDX0
,
77 [FE_REG_FE_INT_ENABLE
] = RT5350_FE_INT_ENABLE
,
78 [FE_REG_FE_INT_STATUS
] = RT5350_FE_INT_STATUS
,
79 [FE_REG_FE_DMA_VID_BASE
] = MT7620_DMA_VID
,
80 [FE_REG_FE_COUNTER_BASE
] = MT7620_GDM1_TX_GBCNT
,
81 [FE_REG_FE_RST_GL
] = MT7621_FE_RST_GL
,
84 static const u32 mt7621_reg_table
[FE_REG_COUNT
] = {
85 [FE_REG_PDMA_GLO_CFG
] = RT5350_PDMA_GLO_CFG
,
86 [FE_REG_PDMA_RST_CFG
] = RT5350_PDMA_RST_CFG
,
87 [FE_REG_DLY_INT_CFG
] = RT5350_DLY_INT_CFG
,
88 [FE_REG_TX_BASE_PTR0
] = RT5350_TX_BASE_PTR0
,
89 [FE_REG_TX_MAX_CNT0
] = RT5350_TX_MAX_CNT0
,
90 [FE_REG_TX_CTX_IDX0
] = RT5350_TX_CTX_IDX0
,
91 [FE_REG_TX_DTX_IDX0
] = RT5350_TX_DTX_IDX0
,
92 [FE_REG_RX_BASE_PTR0
] = RT5350_RX_BASE_PTR0
,
93 [FE_REG_RX_MAX_CNT0
] = RT5350_RX_MAX_CNT0
,
94 [FE_REG_RX_CALC_IDX0
] = RT5350_RX_CALC_IDX0
,
95 [FE_REG_RX_DRX_IDX0
] = RT5350_RX_DRX_IDX0
,
96 [FE_REG_FE_INT_ENABLE
] = RT5350_FE_INT_ENABLE
,
97 [FE_REG_FE_INT_STATUS
] = RT5350_FE_INT_STATUS
,
98 [FE_REG_FE_DMA_VID_BASE
] = MT7621_DMA_VID
,
99 [FE_REG_FE_COUNTER_BASE
] = MT7621_GDM1_TX_GBCNT
,
100 [FE_REG_FE_RST_GL
] = MT7621_FE_RST_GL
,
103 static void mt7620_fe_reset(void)
105 fe_reset(MT7620A_RESET_FE
| MT7620A_RESET_ESW
);
108 static void mt7621_fe_reset(void)
110 fe_reset(MT7621_RESET_FE
);
113 static void mt7620_rxcsum_config(bool enable
)
116 fe_w32(fe_r32(MT7620A_GDMA1_FWD_CFG
) | (GDMA_ICS_EN
|
117 GDMA_TCS_EN
| GDMA_UCS_EN
),
118 MT7620A_GDMA1_FWD_CFG
);
120 fe_w32(fe_r32(MT7620A_GDMA1_FWD_CFG
) & ~(GDMA_ICS_EN
|
121 GDMA_TCS_EN
| GDMA_UCS_EN
),
122 MT7620A_GDMA1_FWD_CFG
);
125 static void mt7620_txcsum_config(bool enable
)
128 fe_w32(fe_r32(MT7620A_CDMA_CSG_CFG
) | (CDMA_ICS_EN
|
129 CDMA_UCS_EN
| CDMA_TCS_EN
),
130 MT7620A_CDMA_CSG_CFG
);
132 fe_w32(fe_r32(MT7620A_CDMA_CSG_CFG
) & ~(CDMA_ICS_EN
|
133 CDMA_UCS_EN
| CDMA_TCS_EN
),
134 MT7620A_CDMA_CSG_CFG
);
137 static int mt7620_fwd_config(struct fe_priv
*priv
)
139 struct net_device
*dev
= priv_netdev(priv
);
141 fe_w32(fe_r32(MT7620A_GDMA1_FWD_CFG
) & ~7, MT7620A_GDMA1_FWD_CFG
);
143 mt7620_txcsum_config((dev
->features
& NETIF_F_IP_CSUM
));
144 mt7620_rxcsum_config((dev
->features
& NETIF_F_RXCSUM
));
149 static int mt7621_fwd_config(struct fe_priv
*priv
)
151 struct net_device
*dev
= priv_netdev(priv
);
153 fe_w32(fe_r32(MT7620A_GDMA1_FWD_CFG
) & ~0xffff, MT7620A_GDMA1_FWD_CFG
);
155 mt7620_txcsum_config((dev
->features
& NETIF_F_IP_CSUM
));
156 mt7620_rxcsum_config((dev
->features
& NETIF_F_RXCSUM
));
161 static void mt7620_tx_dma(struct fe_tx_dma
*txd
)
166 static void mt7621_tx_dma(struct fe_tx_dma
*txd
)
171 static void mt7620_init_data(struct fe_soc_data
*data
,
172 struct net_device
*netdev
)
174 struct fe_priv
*priv
= netdev_priv(netdev
);
176 priv
->flags
= FE_FLAG_PADDING_64B
| FE_FLAG_RX_2B_OFFSET
|
178 netdev
->hw_features
= NETIF_F_IP_CSUM
| NETIF_F_RXCSUM
|
179 NETIF_F_HW_VLAN_CTAG_TX
;
181 if (mt7620_get_eco() >= 5 || IS_ENABLED(CONFIG_SOC_MT7621
))
182 netdev
->hw_features
|= NETIF_F_SG
| NETIF_F_TSO
| NETIF_F_TSO6
|
186 static void mt7621_init_data(struct fe_soc_data
*data
,
187 struct net_device
*netdev
)
189 struct fe_priv
*priv
= netdev_priv(netdev
);
191 priv
->flags
= FE_FLAG_PADDING_64B
| FE_FLAG_RX_2B_OFFSET
|
193 netdev
->hw_features
= NETIF_F_HW_VLAN_CTAG_TX
;
196 static void mt7621_set_mac(struct fe_priv
*priv
, unsigned char *mac
)
200 spin_lock_irqsave(&priv
->page_lock
, flags
);
201 fe_w32((mac
[0] << 8) | mac
[1], GSW_REG_GDMA1_MAC_ADRH
);
202 fe_w32((mac
[2] << 24) | (mac
[3] << 16) | (mac
[4] << 8) | mac
[5],
203 GSW_REG_GDMA1_MAC_ADRL
);
204 spin_unlock_irqrestore(&priv
->page_lock
, flags
);
207 static struct fe_soc_data mt7620_data
= {
208 .mac
= { 0x00, 0x11, 0x22, 0x33, 0x44, 0x55 },
209 .init_data
= mt7620_init_data
,
210 .reset_fe
= mt7620_fe_reset
,
211 .set_mac
= mt7620_set_mac
,
212 .fwd_config
= mt7620_fwd_config
,
213 .tx_dma
= mt7620_tx_dma
,
214 .switch_init
= mt7620_gsw_probe
,
215 .switch_config
= mt7620_gsw_config
,
216 .port_init
= mt7620_port_init
,
217 .reg_table
= mt7620_reg_table
,
218 .pdma_glo_cfg
= FE_PDMA_SIZE_16DWORDS
,
219 .rx_int
= RT5350_RX_DONE_INT
,
220 .tx_int
= RT5350_TX_DONE_INT
,
221 .checksum_bit
= MT7620_L4_VALID
,
222 .tx_udf_bit
= MT7620_TX_DMA_UDF
,
223 .has_carrier
= mt7620a_has_carrier
,
224 .mdio_read
= mt7620_mdio_read
,
225 .mdio_write
= mt7620_mdio_write
,
226 .mdio_adjust_link
= mt7620_mdio_link_adjust
,
229 static struct fe_soc_data mt7621_data
= {
230 .mac
= { 0x00, 0x11, 0x22, 0x33, 0x44, 0x55 },
231 .init_data
= mt7621_init_data
,
232 .reset_fe
= mt7621_fe_reset
,
233 .set_mac
= mt7621_set_mac
,
234 .fwd_config
= mt7621_fwd_config
,
235 .tx_dma
= mt7621_tx_dma
,
236 .switch_init
= mt7620_gsw_probe
,
237 .switch_config
= mt7621_gsw_config
,
238 .reg_table
= mt7621_reg_table
,
239 .pdma_glo_cfg
= FE_PDMA_SIZE_16DWORDS
,
240 .rx_int
= RT5350_RX_DONE_INT
,
241 .tx_int
= RT5350_TX_DONE_INT
,
242 .checksum_bit
= MT7621_L4_VALID
,
243 .tx_udf_bit
= MT7621_TX_DMA_UDF
,
244 .has_carrier
= mt7620a_has_carrier
,
245 .mdio_read
= mt7620_mdio_read
,
246 .mdio_write
= mt7620_mdio_write
,
247 .mdio_adjust_link
= mt7620_mdio_link_adjust
,
250 const struct of_device_id of_fe_match
[] = {
251 { .compatible
= "ralink,mt7620a-eth", .data
= &mt7620_data
},
252 { .compatible
= "ralink,mt7621-eth", .data
= &mt7621_data
},
256 MODULE_DEVICE_TABLE(of
, of_fe_match
);