1 /* This program is free software; you can redistribute it and/or modify
2 * it under the terms of the GNU General Public License as published by
3 * the Free Software Foundation; version 2 of the License
5 * This program is distributed in the hope that it will be useful,
6 * but WITHOUT ANY WARRANTY; without even the implied warranty of
7 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
8 * GNU General Public License for more details.
10 * Copyright (C) 2009-2015 John Crispin <blogic@openwrt.org>
11 * Copyright (C) 2009-2015 Felix Fietkau <nbd@nbd.name>
12 * Copyright (C) 2013-2015 Michael Lee <igvtee@gmail.com>
15 #include <linux/module.h>
16 #include <linux/kernel.h>
17 #include <linux/types.h>
18 #include <linux/dma-mapping.h>
19 #include <linux/init.h>
20 #include <linux/skbuff.h>
21 #include <linux/etherdevice.h>
22 #include <linux/ethtool.h>
23 #include <linux/platform_device.h>
24 #include <linux/of_device.h>
25 #include <linux/clk.h>
26 #include <linux/of_net.h>
27 #include <linux/of_mdio.h>
28 #include <linux/if_vlan.h>
29 #include <linux/reset.h>
30 #include <linux/tcp.h>
32 #include <linux/bug.h>
33 #include <linux/netfilter.h>
34 #include <net/netfilter/nf_flow_table.h>
36 #include <asm/mach-ralink/ralink_regs.h>
38 #include "mtk_eth_soc.h"
42 #define MAX_RX_LENGTH 1536
43 #define FE_RX_ETH_HLEN (VLAN_ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN)
44 #define FE_RX_HLEN (NET_SKB_PAD + FE_RX_ETH_HLEN + NET_IP_ALIGN)
45 #define DMA_DUMMY_DESC 0xffffffff
46 #define FE_DEFAULT_MSG_ENABLE \
56 #define TX_DMA_DESP2_DEF (TX_DMA_LS0 | TX_DMA_DONE)
57 #define TX_DMA_DESP4_DEF (TX_DMA_QN(3) | TX_DMA_PN(1))
58 #define NEXT_TX_DESP_IDX(X) (((X) + 1) & (ring->tx_ring_size - 1))
59 #define NEXT_RX_DESP_IDX(X) (((X) + 1) & (ring->rx_ring_size - 1))
61 #define SYSC_REG_RSTCTRL 0x34
63 static int fe_msg_level
= -1;
64 module_param_named(msg_level
, fe_msg_level
, int, 0);
65 MODULE_PARM_DESC(msg_level
, "Message level (-1=defaults,0=none,...,16=all)");
67 static const u16 fe_reg_table_default
[FE_REG_COUNT
] = {
68 [FE_REG_PDMA_GLO_CFG
] = FE_PDMA_GLO_CFG
,
69 [FE_REG_PDMA_RST_CFG
] = FE_PDMA_RST_CFG
,
70 [FE_REG_DLY_INT_CFG
] = FE_DLY_INT_CFG
,
71 [FE_REG_TX_BASE_PTR0
] = FE_TX_BASE_PTR0
,
72 [FE_REG_TX_MAX_CNT0
] = FE_TX_MAX_CNT0
,
73 [FE_REG_TX_CTX_IDX0
] = FE_TX_CTX_IDX0
,
74 [FE_REG_TX_DTX_IDX0
] = FE_TX_DTX_IDX0
,
75 [FE_REG_RX_BASE_PTR0
] = FE_RX_BASE_PTR0
,
76 [FE_REG_RX_MAX_CNT0
] = FE_RX_MAX_CNT0
,
77 [FE_REG_RX_CALC_IDX0
] = FE_RX_CALC_IDX0
,
78 [FE_REG_RX_DRX_IDX0
] = FE_RX_DRX_IDX0
,
79 [FE_REG_FE_INT_ENABLE
] = FE_FE_INT_ENABLE
,
80 [FE_REG_FE_INT_STATUS
] = FE_FE_INT_STATUS
,
81 [FE_REG_FE_DMA_VID_BASE
] = FE_DMA_VID0
,
82 [FE_REG_FE_COUNTER_BASE
] = FE_GDMA1_TX_GBCNT
,
83 [FE_REG_FE_RST_GL
] = FE_FE_RST_GL
,
86 static const u16
*fe_reg_table
= fe_reg_table_default
;
90 void (*action
)(struct fe_priv
*);
93 static void __iomem
*fe_base
;
95 void fe_w32(u32 val
, unsigned reg
)
97 __raw_writel(val
, fe_base
+ reg
);
100 u32
fe_r32(unsigned reg
)
102 return __raw_readl(fe_base
+ reg
);
105 void fe_reg_w32(u32 val
, enum fe_reg reg
)
107 fe_w32(val
, fe_reg_table
[reg
]);
110 u32
fe_reg_r32(enum fe_reg reg
)
112 return fe_r32(fe_reg_table
[reg
]);
115 void fe_m32(struct fe_priv
*eth
, u32 clear
, u32 set
, unsigned reg
)
119 spin_lock(ð
->page_lock
);
120 val
= __raw_readl(fe_base
+ reg
);
123 __raw_writel(val
, fe_base
+ reg
);
124 spin_unlock(ð
->page_lock
);
127 void fe_reset(u32 reset_bits
)
131 t
= rt_sysc_r32(SYSC_REG_RSTCTRL
);
133 rt_sysc_w32(t
, SYSC_REG_RSTCTRL
);
134 usleep_range(10, 20);
137 rt_sysc_w32(t
, SYSC_REG_RSTCTRL
);
138 usleep_range(10, 20);
141 static inline void fe_int_disable(u32 mask
)
143 fe_reg_w32(fe_reg_r32(FE_REG_FE_INT_ENABLE
) & ~mask
,
144 FE_REG_FE_INT_ENABLE
);
146 fe_reg_r32(FE_REG_FE_INT_ENABLE
);
149 static inline void fe_int_enable(u32 mask
)
151 fe_reg_w32(fe_reg_r32(FE_REG_FE_INT_ENABLE
) | mask
,
152 FE_REG_FE_INT_ENABLE
);
154 fe_reg_r32(FE_REG_FE_INT_ENABLE
);
157 static inline void fe_hw_set_macaddr(struct fe_priv
*priv
, unsigned char *mac
)
161 spin_lock_irqsave(&priv
->page_lock
, flags
);
162 fe_w32((mac
[0] << 8) | mac
[1], FE_GDMA1_MAC_ADRH
);
163 fe_w32((mac
[2] << 24) | (mac
[3] << 16) | (mac
[4] << 8) | mac
[5],
165 spin_unlock_irqrestore(&priv
->page_lock
, flags
);
168 static int fe_set_mac_address(struct net_device
*dev
, void *p
)
170 int ret
= eth_mac_addr(dev
, p
);
173 struct fe_priv
*priv
= netdev_priv(dev
);
175 if (priv
->soc
->set_mac
)
176 priv
->soc
->set_mac(priv
, dev
->dev_addr
);
178 fe_hw_set_macaddr(priv
, p
);
184 static inline int fe_max_frag_size(int mtu
)
186 /* make sure buf_size will be at least MAX_RX_LENGTH */
187 if (mtu
+ FE_RX_ETH_HLEN
< MAX_RX_LENGTH
)
188 mtu
= MAX_RX_LENGTH
- FE_RX_ETH_HLEN
;
190 return SKB_DATA_ALIGN(FE_RX_HLEN
+ mtu
) +
191 SKB_DATA_ALIGN(sizeof(struct skb_shared_info
));
194 static inline int fe_max_buf_size(int frag_size
)
196 int buf_size
= frag_size
- NET_SKB_PAD
- NET_IP_ALIGN
-
197 SKB_DATA_ALIGN(sizeof(struct skb_shared_info
));
199 BUG_ON(buf_size
< MAX_RX_LENGTH
);
203 static inline void fe_get_rxd(struct fe_rx_dma
*rxd
, struct fe_rx_dma
*dma_rxd
)
205 rxd
->rxd1
= dma_rxd
->rxd1
;
206 rxd
->rxd2
= dma_rxd
->rxd2
;
207 rxd
->rxd3
= dma_rxd
->rxd3
;
208 rxd
->rxd4
= dma_rxd
->rxd4
;
211 static inline void fe_set_txd(struct fe_tx_dma
*txd
, struct fe_tx_dma
*dma_txd
)
213 dma_txd
->txd1
= txd
->txd1
;
214 dma_txd
->txd3
= txd
->txd3
;
215 dma_txd
->txd4
= txd
->txd4
;
216 /* clean dma done flag last */
217 dma_txd
->txd2
= txd
->txd2
;
220 static void fe_clean_rx(struct fe_priv
*priv
)
223 struct fe_rx_ring
*ring
= &priv
->rx_ring
;
226 for (i
= 0; i
< ring
->rx_ring_size
; i
++)
227 if (ring
->rx_data
[i
]) {
228 if (ring
->rx_dma
&& ring
->rx_dma
[i
].rxd1
)
229 dma_unmap_single(&priv
->netdev
->dev
,
230 ring
->rx_dma
[i
].rxd1
,
233 put_page(virt_to_head_page(ring
->rx_data
[i
]));
236 kfree(ring
->rx_data
);
237 ring
->rx_data
= NULL
;
241 dma_free_coherent(&priv
->netdev
->dev
,
242 ring
->rx_ring_size
* sizeof(*ring
->rx_dma
),
249 static int fe_alloc_rx(struct fe_priv
*priv
)
251 struct net_device
*netdev
= priv
->netdev
;
252 struct fe_rx_ring
*ring
= &priv
->rx_ring
;
255 ring
->rx_data
= kcalloc(ring
->rx_ring_size
, sizeof(*ring
->rx_data
),
260 for (i
= 0; i
< ring
->rx_ring_size
; i
++) {
261 ring
->rx_data
[i
] = netdev_alloc_frag(ring
->frag_size
);
262 if (!ring
->rx_data
[i
])
266 ring
->rx_dma
= dma_alloc_coherent(&netdev
->dev
,
267 ring
->rx_ring_size
* sizeof(*ring
->rx_dma
),
269 GFP_ATOMIC
| __GFP_ZERO
);
273 if (priv
->flags
& FE_FLAG_RX_2B_OFFSET
)
277 for (i
= 0; i
< ring
->rx_ring_size
; i
++) {
278 dma_addr_t dma_addr
= dma_map_single(&netdev
->dev
,
279 ring
->rx_data
[i
] + NET_SKB_PAD
+ pad
,
282 if (unlikely(dma_mapping_error(&netdev
->dev
, dma_addr
)))
284 ring
->rx_dma
[i
].rxd1
= (unsigned int)dma_addr
;
286 if (priv
->flags
& FE_FLAG_RX_SG_DMA
)
287 ring
->rx_dma
[i
].rxd2
= RX_DMA_PLEN0(ring
->rx_buf_size
);
289 ring
->rx_dma
[i
].rxd2
= RX_DMA_LSO
;
291 ring
->rx_calc_idx
= ring
->rx_ring_size
- 1;
292 /* make sure that all changes to the dma ring are flushed before we
297 fe_reg_w32(ring
->rx_phys
, FE_REG_RX_BASE_PTR0
);
298 fe_reg_w32(ring
->rx_ring_size
, FE_REG_RX_MAX_CNT0
);
299 fe_reg_w32(ring
->rx_calc_idx
, FE_REG_RX_CALC_IDX0
);
300 fe_reg_w32(FE_PST_DRX_IDX0
, FE_REG_PDMA_RST_CFG
);
308 static void fe_txd_unmap(struct device
*dev
, struct fe_tx_buf
*tx_buf
)
310 if (tx_buf
->flags
& FE_TX_FLAGS_SINGLE0
) {
311 dma_unmap_single(dev
,
312 dma_unmap_addr(tx_buf
, dma_addr0
),
313 dma_unmap_len(tx_buf
, dma_len0
),
315 } else if (tx_buf
->flags
& FE_TX_FLAGS_PAGE0
) {
317 dma_unmap_addr(tx_buf
, dma_addr0
),
318 dma_unmap_len(tx_buf
, dma_len0
),
321 if (tx_buf
->flags
& FE_TX_FLAGS_PAGE1
)
323 dma_unmap_addr(tx_buf
, dma_addr1
),
324 dma_unmap_len(tx_buf
, dma_len1
),
328 if (tx_buf
->skb
&& (tx_buf
->skb
!= (struct sk_buff
*)DMA_DUMMY_DESC
))
329 dev_kfree_skb_any(tx_buf
->skb
);
333 static void fe_clean_tx(struct fe_priv
*priv
)
336 struct device
*dev
= &priv
->netdev
->dev
;
337 struct fe_tx_ring
*ring
= &priv
->tx_ring
;
340 for (i
= 0; i
< ring
->tx_ring_size
; i
++)
341 fe_txd_unmap(dev
, &ring
->tx_buf
[i
]);
347 dma_free_coherent(dev
,
348 ring
->tx_ring_size
* sizeof(*ring
->tx_dma
),
354 netdev_reset_queue(priv
->netdev
);
357 static int fe_alloc_tx(struct fe_priv
*priv
)
360 struct fe_tx_ring
*ring
= &priv
->tx_ring
;
362 ring
->tx_free_idx
= 0;
363 ring
->tx_next_idx
= 0;
364 ring
->tx_thresh
= max((unsigned long)ring
->tx_ring_size
>> 2,
367 ring
->tx_buf
= kcalloc(ring
->tx_ring_size
, sizeof(*ring
->tx_buf
),
372 ring
->tx_dma
= dma_alloc_coherent(&priv
->netdev
->dev
,
373 ring
->tx_ring_size
* sizeof(*ring
->tx_dma
),
375 GFP_ATOMIC
| __GFP_ZERO
);
379 for (i
= 0; i
< ring
->tx_ring_size
; i
++) {
380 if (priv
->soc
->tx_dma
)
381 priv
->soc
->tx_dma(&ring
->tx_dma
[i
]);
382 ring
->tx_dma
[i
].txd2
= TX_DMA_DESP2_DEF
;
384 /* make sure that all changes to the dma ring are flushed before we
389 fe_reg_w32(ring
->tx_phys
, FE_REG_TX_BASE_PTR0
);
390 fe_reg_w32(ring
->tx_ring_size
, FE_REG_TX_MAX_CNT0
);
391 fe_reg_w32(0, FE_REG_TX_CTX_IDX0
);
392 fe_reg_w32(FE_PST_DTX_IDX0
, FE_REG_PDMA_RST_CFG
);
400 static int fe_init_dma(struct fe_priv
*priv
)
404 err
= fe_alloc_tx(priv
);
408 err
= fe_alloc_rx(priv
);
415 static void fe_free_dma(struct fe_priv
*priv
)
421 void fe_stats_update(struct fe_priv
*priv
)
423 struct fe_hw_stats
*hwstats
= priv
->hw_stats
;
424 unsigned int base
= fe_reg_table
[FE_REG_FE_COUNTER_BASE
];
427 u64_stats_update_begin(&hwstats
->syncp
);
429 if (IS_ENABLED(CONFIG_SOC_MT7621
)) {
430 hwstats
->rx_bytes
+= fe_r32(base
);
431 stats
= fe_r32(base
+ 0x04);
433 hwstats
->rx_bytes
+= (stats
<< 32);
434 hwstats
->rx_packets
+= fe_r32(base
+ 0x08);
435 hwstats
->rx_overflow
+= fe_r32(base
+ 0x10);
436 hwstats
->rx_fcs_errors
+= fe_r32(base
+ 0x14);
437 hwstats
->rx_short_errors
+= fe_r32(base
+ 0x18);
438 hwstats
->rx_long_errors
+= fe_r32(base
+ 0x1c);
439 hwstats
->rx_checksum_errors
+= fe_r32(base
+ 0x20);
440 hwstats
->rx_flow_control_packets
+= fe_r32(base
+ 0x24);
441 hwstats
->tx_skip
+= fe_r32(base
+ 0x28);
442 hwstats
->tx_collisions
+= fe_r32(base
+ 0x2c);
443 hwstats
->tx_bytes
+= fe_r32(base
+ 0x30);
444 stats
= fe_r32(base
+ 0x34);
446 hwstats
->tx_bytes
+= (stats
<< 32);
447 hwstats
->tx_packets
+= fe_r32(base
+ 0x38);
449 hwstats
->tx_bytes
+= fe_r32(base
);
450 hwstats
->tx_packets
+= fe_r32(base
+ 0x04);
451 hwstats
->tx_skip
+= fe_r32(base
+ 0x08);
452 hwstats
->tx_collisions
+= fe_r32(base
+ 0x0c);
453 hwstats
->rx_bytes
+= fe_r32(base
+ 0x20);
454 hwstats
->rx_packets
+= fe_r32(base
+ 0x24);
455 hwstats
->rx_overflow
+= fe_r32(base
+ 0x28);
456 hwstats
->rx_fcs_errors
+= fe_r32(base
+ 0x2c);
457 hwstats
->rx_short_errors
+= fe_r32(base
+ 0x30);
458 hwstats
->rx_long_errors
+= fe_r32(base
+ 0x34);
459 hwstats
->rx_checksum_errors
+= fe_r32(base
+ 0x38);
460 hwstats
->rx_flow_control_packets
+= fe_r32(base
+ 0x3c);
463 u64_stats_update_end(&hwstats
->syncp
);
466 static void fe_get_stats64(struct net_device
*dev
,
467 struct rtnl_link_stats64
*storage
)
469 struct fe_priv
*priv
= netdev_priv(dev
);
470 struct fe_hw_stats
*hwstats
= priv
->hw_stats
;
471 unsigned int base
= fe_reg_table
[FE_REG_FE_COUNTER_BASE
];
475 netdev_stats_to_stats64(storage
, &dev
->stats
);
479 if (netif_running(dev
) && netif_device_present(dev
)) {
480 if (spin_trylock_bh(&hwstats
->stats_lock
)) {
481 fe_stats_update(priv
);
482 spin_unlock_bh(&hwstats
->stats_lock
);
487 start
= u64_stats_fetch_begin_irq(&hwstats
->syncp
);
488 storage
->rx_packets
= hwstats
->rx_packets
;
489 storage
->tx_packets
= hwstats
->tx_packets
;
490 storage
->rx_bytes
= hwstats
->rx_bytes
;
491 storage
->tx_bytes
= hwstats
->tx_bytes
;
492 storage
->collisions
= hwstats
->tx_collisions
;
493 storage
->rx_length_errors
= hwstats
->rx_short_errors
+
494 hwstats
->rx_long_errors
;
495 storage
->rx_over_errors
= hwstats
->rx_overflow
;
496 storage
->rx_crc_errors
= hwstats
->rx_fcs_errors
;
497 storage
->rx_errors
= hwstats
->rx_checksum_errors
;
498 storage
->tx_aborted_errors
= hwstats
->tx_skip
;
499 } while (u64_stats_fetch_retry_irq(&hwstats
->syncp
, start
));
501 storage
->tx_errors
= priv
->netdev
->stats
.tx_errors
;
502 storage
->rx_dropped
= priv
->netdev
->stats
.rx_dropped
;
503 storage
->tx_dropped
= priv
->netdev
->stats
.tx_dropped
;
506 static int fe_vlan_rx_add_vid(struct net_device
*dev
,
507 __be16 proto
, u16 vid
)
509 struct fe_priv
*priv
= netdev_priv(dev
);
510 u32 idx
= (vid
& 0xf);
513 if (!((fe_reg_table
[FE_REG_FE_DMA_VID_BASE
]) &&
514 (dev
->features
& NETIF_F_HW_VLAN_CTAG_TX
)))
517 if (test_bit(idx
, &priv
->vlan_map
)) {
518 netdev_warn(dev
, "disable tx vlan offload\n");
519 dev
->wanted_features
&= ~NETIF_F_HW_VLAN_CTAG_TX
;
520 netdev_update_features(dev
);
522 vlan_cfg
= fe_r32(fe_reg_table
[FE_REG_FE_DMA_VID_BASE
] +
526 vlan_cfg
|= (vid
<< 16);
528 vlan_cfg
&= 0xffff0000;
531 fe_w32(vlan_cfg
, fe_reg_table
[FE_REG_FE_DMA_VID_BASE
] +
533 set_bit(idx
, &priv
->vlan_map
);
539 static int fe_vlan_rx_kill_vid(struct net_device
*dev
,
540 __be16 proto
, u16 vid
)
542 struct fe_priv
*priv
= netdev_priv(dev
);
543 u32 idx
= (vid
& 0xf);
545 if (!((fe_reg_table
[FE_REG_FE_DMA_VID_BASE
]) &&
546 (dev
->features
& NETIF_F_HW_VLAN_CTAG_TX
)))
549 clear_bit(idx
, &priv
->vlan_map
);
554 static inline u32
fe_empty_txd(struct fe_tx_ring
*ring
)
557 return (u32
)(ring
->tx_ring_size
-
558 ((ring
->tx_next_idx
- ring
->tx_free_idx
) &
559 (ring
->tx_ring_size
- 1)));
562 static int fe_tx_map_dma(struct sk_buff
*skb
, struct net_device
*dev
,
563 int tx_num
, struct fe_tx_ring
*ring
)
565 struct fe_priv
*priv
= netdev_priv(dev
);
566 struct skb_frag_struct
*frag
;
567 struct fe_tx_dma txd
, *ptxd
;
568 struct fe_tx_buf
*tx_buf
;
569 dma_addr_t mapped_addr
;
570 unsigned int nr_frags
;
572 int i
, j
, k
, frag_size
, frag_map_size
, offset
;
574 tx_buf
= &ring
->tx_buf
[ring
->tx_next_idx
];
575 memset(tx_buf
, 0, sizeof(*tx_buf
));
576 memset(&txd
, 0, sizeof(txd
));
577 nr_frags
= skb_shinfo(skb
)->nr_frags
;
579 /* init tx descriptor */
580 if (priv
->soc
->tx_dma
)
581 priv
->soc
->tx_dma(&txd
);
583 txd
.txd4
= TX_DMA_DESP4_DEF
;
586 /* TX Checksum offload */
587 if (skb
->ip_summed
== CHECKSUM_PARTIAL
)
588 txd
.txd4
|= TX_DMA_CHKSUM
;
590 /* VLAN header offload */
591 if (skb_vlan_tag_present(skb
)) {
592 u16 tag
= skb_vlan_tag_get(skb
);
594 if (IS_ENABLED(CONFIG_SOC_MT7621
))
595 txd
.txd4
|= TX_DMA_INS_VLAN_MT7621
| tag
;
597 txd
.txd4
|= TX_DMA_INS_VLAN
|
598 ((tag
>> VLAN_PRIO_SHIFT
) << 4) |
602 /* TSO: fill MSS info in tcp checksum field */
603 if (skb_is_gso(skb
)) {
604 if (skb_cow_head(skb
, 0)) {
605 netif_warn(priv
, tx_err
, dev
,
606 "GSO expand head fail.\n");
609 if (skb_shinfo(skb
)->gso_type
&
610 (SKB_GSO_TCPV4
| SKB_GSO_TCPV6
)) {
611 txd
.txd4
|= TX_DMA_TSO
;
612 tcp_hdr(skb
)->check
= htons(skb_shinfo(skb
)->gso_size
);
616 mapped_addr
= dma_map_single(&dev
->dev
, skb
->data
,
617 skb_headlen(skb
), DMA_TO_DEVICE
);
618 if (unlikely(dma_mapping_error(&dev
->dev
, mapped_addr
)))
620 txd
.txd1
= mapped_addr
;
621 txd
.txd2
= TX_DMA_PLEN0(skb_headlen(skb
));
623 tx_buf
->flags
|= FE_TX_FLAGS_SINGLE0
;
624 dma_unmap_addr_set(tx_buf
, dma_addr0
, mapped_addr
);
625 dma_unmap_len_set(tx_buf
, dma_len0
, skb_headlen(skb
));
628 j
= ring
->tx_next_idx
;
630 for (i
= 0; i
< nr_frags
; i
++) {
632 frag
= &skb_shinfo(skb
)->frags
[i
];
633 frag_size
= skb_frag_size(frag
);
635 while (frag_size
> 0) {
636 frag_map_size
= min(frag_size
, TX_DMA_BUF_LEN
);
637 mapped_addr
= skb_frag_dma_map(&dev
->dev
, frag
, offset
,
640 if (unlikely(dma_mapping_error(&dev
->dev
, mapped_addr
)))
644 j
= NEXT_TX_DESP_IDX(j
);
645 txd
.txd1
= mapped_addr
;
646 txd
.txd2
= TX_DMA_PLEN0(frag_map_size
);
649 tx_buf
= &ring
->tx_buf
[j
];
650 memset(tx_buf
, 0, sizeof(*tx_buf
));
652 tx_buf
->flags
|= FE_TX_FLAGS_PAGE0
;
653 dma_unmap_addr_set(tx_buf
, dma_addr0
,
655 dma_unmap_len_set(tx_buf
, dma_len0
,
658 txd
.txd3
= mapped_addr
;
659 txd
.txd2
|= TX_DMA_PLEN1(frag_map_size
);
661 tx_buf
->skb
= (struct sk_buff
*)DMA_DUMMY_DESC
;
662 tx_buf
->flags
|= FE_TX_FLAGS_PAGE1
;
663 dma_unmap_addr_set(tx_buf
, dma_addr1
,
665 dma_unmap_len_set(tx_buf
, dma_len1
,
668 if (!((i
== (nr_frags
- 1)) &&
669 (frag_map_size
== frag_size
))) {
670 fe_set_txd(&txd
, &ring
->tx_dma
[j
]);
671 memset(&txd
, 0, sizeof(txd
));
674 frag_size
-= frag_map_size
;
675 offset
+= frag_map_size
;
680 /* set last segment */
682 txd
.txd2
|= TX_DMA_LS1
;
684 txd
.txd2
|= TX_DMA_LS0
;
685 fe_set_txd(&txd
, &ring
->tx_dma
[j
]);
687 /* store skb to cleanup */
690 netdev_sent_queue(dev
, skb
->len
);
691 skb_tx_timestamp(skb
);
693 ring
->tx_next_idx
= NEXT_TX_DESP_IDX(j
);
694 /* make sure that all changes to the dma ring are flushed before we
698 if (unlikely(fe_empty_txd(ring
) <= ring
->tx_thresh
)) {
699 netif_stop_queue(dev
);
701 if (unlikely(fe_empty_txd(ring
) > ring
->tx_thresh
))
702 netif_wake_queue(dev
);
705 if (netif_xmit_stopped(netdev_get_tx_queue(dev
, 0)) || !skb
->xmit_more
)
706 fe_reg_w32(ring
->tx_next_idx
, FE_REG_TX_CTX_IDX0
);
711 j
= ring
->tx_next_idx
;
712 for (i
= 0; i
< tx_num
; i
++) {
713 ptxd
= &ring
->tx_dma
[j
];
714 tx_buf
= &ring
->tx_buf
[j
];
717 fe_txd_unmap(&dev
->dev
, tx_buf
);
719 ptxd
->txd2
= TX_DMA_DESP2_DEF
;
720 j
= NEXT_TX_DESP_IDX(j
);
722 /* make sure that all changes to the dma ring are flushed before we
731 static inline int fe_skb_padto(struct sk_buff
*skb
, struct fe_priv
*priv
)
737 if (unlikely(skb
->len
< VLAN_ETH_ZLEN
)) {
738 if ((priv
->flags
& FE_FLAG_PADDING_64B
) &&
739 !(priv
->flags
& FE_FLAG_PADDING_BUG
))
742 if (skb_vlan_tag_present(skb
))
744 else if (skb
->protocol
== cpu_to_be16(ETH_P_8021Q
))
746 else if (!(priv
->flags
& FE_FLAG_PADDING_64B
))
751 if (skb
->len
< len
) {
752 ret
= skb_pad(skb
, len
- skb
->len
);
756 skb_set_tail_pointer(skb
, len
);
763 static inline int fe_cal_txd_req(struct sk_buff
*skb
)
766 struct skb_frag_struct
*frag
;
769 if (skb_is_gso(skb
)) {
770 for (i
= 0; i
< skb_shinfo(skb
)->nr_frags
; i
++) {
771 frag
= &skb_shinfo(skb
)->frags
[i
];
772 nfrags
+= DIV_ROUND_UP(frag
->size
, TX_DMA_BUF_LEN
);
775 nfrags
+= skb_shinfo(skb
)->nr_frags
;
778 return DIV_ROUND_UP(nfrags
, 2);
781 static int fe_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
783 struct fe_priv
*priv
= netdev_priv(dev
);
784 struct fe_tx_ring
*ring
= &priv
->tx_ring
;
785 struct net_device_stats
*stats
= &dev
->stats
;
789 if (fe_skb_padto(skb
, priv
)) {
790 netif_warn(priv
, tx_err
, dev
, "tx padding failed!\n");
794 tx_num
= fe_cal_txd_req(skb
);
795 if (unlikely(fe_empty_txd(ring
) <= tx_num
)) {
796 netif_stop_queue(dev
);
797 netif_err(priv
, tx_queued
, dev
,
798 "Tx Ring full when queue awake!\n");
799 return NETDEV_TX_BUSY
;
802 if (fe_tx_map_dma(skb
, dev
, tx_num
, ring
) < 0) {
806 stats
->tx_bytes
+= len
;
812 static int fe_poll_rx(struct napi_struct
*napi
, int budget
,
813 struct fe_priv
*priv
, u32 rx_intr
)
815 struct net_device
*netdev
= priv
->netdev
;
816 struct net_device_stats
*stats
= &netdev
->stats
;
817 struct fe_soc_data
*soc
= priv
->soc
;
818 struct fe_rx_ring
*ring
= &priv
->rx_ring
;
819 int idx
= ring
->rx_calc_idx
;
823 struct fe_rx_dma
*rxd
, trxd
;
826 if (netdev
->features
& NETIF_F_RXCSUM
)
827 checksum_bit
= soc
->checksum_bit
;
831 if (priv
->flags
& FE_FLAG_RX_2B_OFFSET
)
836 while (done
< budget
) {
840 idx
= NEXT_RX_DESP_IDX(idx
);
841 rxd
= &ring
->rx_dma
[idx
];
842 data
= ring
->rx_data
[idx
];
844 fe_get_rxd(&trxd
, rxd
);
845 if (!(trxd
.rxd2
& RX_DMA_DONE
))
848 /* alloc new buffer */
849 new_data
= netdev_alloc_frag(ring
->frag_size
);
850 if (unlikely(!new_data
)) {
854 dma_addr
= dma_map_single(&netdev
->dev
,
855 new_data
+ NET_SKB_PAD
+ pad
,
858 if (unlikely(dma_mapping_error(&netdev
->dev
, dma_addr
))) {
859 put_page(virt_to_head_page(new_data
));
864 skb
= build_skb(data
, ring
->frag_size
);
865 if (unlikely(!skb
)) {
866 put_page(virt_to_head_page(new_data
));
869 skb_reserve(skb
, NET_SKB_PAD
+ NET_IP_ALIGN
);
871 dma_unmap_single(&netdev
->dev
, trxd
.rxd1
,
872 ring
->rx_buf_size
, DMA_FROM_DEVICE
);
873 pktlen
= RX_DMA_GET_PLEN0(trxd
.rxd2
);
875 skb_put(skb
, pktlen
);
876 if (trxd
.rxd4
& checksum_bit
)
877 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
879 skb_checksum_none_assert(skb
);
880 skb
->protocol
= eth_type_trans(skb
, netdev
);
882 #ifdef CONFIG_NET_MEDIATEK_OFFLOAD
883 if (mtk_offload_check_rx(priv
, skb
, trxd
.rxd4
) == 0) {
886 stats
->rx_bytes
+= pktlen
;
888 napi_gro_receive(napi
, skb
);
889 #ifdef CONFIG_NET_MEDIATEK_OFFLOAD
894 ring
->rx_data
[idx
] = new_data
;
895 rxd
->rxd1
= (unsigned int)dma_addr
;
898 if (priv
->flags
& FE_FLAG_RX_SG_DMA
)
899 rxd
->rxd2
= RX_DMA_PLEN0(ring
->rx_buf_size
);
901 rxd
->rxd2
= RX_DMA_LSO
;
903 ring
->rx_calc_idx
= idx
;
904 /* make sure that all changes to the dma ring are flushed before
908 fe_reg_w32(ring
->rx_calc_idx
, FE_REG_RX_CALC_IDX0
);
913 fe_reg_w32(rx_intr
, FE_REG_FE_INT_STATUS
);
918 static int fe_poll_tx(struct fe_priv
*priv
, int budget
, u32 tx_intr
,
921 struct net_device
*netdev
= priv
->netdev
;
922 struct device
*dev
= &netdev
->dev
;
923 unsigned int bytes_compl
= 0;
925 struct fe_tx_buf
*tx_buf
;
928 struct fe_tx_ring
*ring
= &priv
->tx_ring
;
930 idx
= ring
->tx_free_idx
;
931 hwidx
= fe_reg_r32(FE_REG_TX_DTX_IDX0
);
933 while ((idx
!= hwidx
) && budget
) {
934 tx_buf
= &ring
->tx_buf
[idx
];
940 if (skb
!= (struct sk_buff
*)DMA_DUMMY_DESC
) {
941 bytes_compl
+= skb
->len
;
945 fe_txd_unmap(dev
, tx_buf
);
946 idx
= NEXT_TX_DESP_IDX(idx
);
948 ring
->tx_free_idx
= idx
;
951 /* read hw index again make sure no new tx packet */
952 hwidx
= fe_reg_r32(FE_REG_TX_DTX_IDX0
);
954 fe_reg_w32(tx_intr
, FE_REG_FE_INT_STATUS
);
962 netdev_completed_queue(netdev
, done
, bytes_compl
);
964 if (unlikely(netif_queue_stopped(netdev
) &&
965 (fe_empty_txd(ring
) > ring
->tx_thresh
)))
966 netif_wake_queue(netdev
);
972 static int fe_poll(struct napi_struct
*napi
, int budget
)
974 struct fe_priv
*priv
= container_of(napi
, struct fe_priv
, rx_napi
);
975 struct fe_hw_stats
*hwstat
= priv
->hw_stats
;
976 int tx_done
, rx_done
, tx_again
;
977 u32 status
, fe_status
, status_reg
, mask
;
978 u32 tx_intr
, rx_intr
, status_intr
;
980 status
= fe_reg_r32(FE_REG_FE_INT_STATUS
);
982 tx_intr
= priv
->soc
->tx_int
;
983 rx_intr
= priv
->soc
->rx_int
;
984 status_intr
= priv
->soc
->status_int
;
989 if (fe_reg_table
[FE_REG_FE_INT_STATUS2
]) {
990 fe_status
= fe_reg_r32(FE_REG_FE_INT_STATUS2
);
991 status_reg
= FE_REG_FE_INT_STATUS2
;
993 status_reg
= FE_REG_FE_INT_STATUS
;
996 if (status
& tx_intr
)
997 tx_done
= fe_poll_tx(priv
, budget
, tx_intr
, &tx_again
);
999 if (status
& rx_intr
)
1000 rx_done
= fe_poll_rx(napi
, budget
, priv
, rx_intr
);
1002 if (unlikely(fe_status
& status_intr
)) {
1003 if (hwstat
&& spin_trylock(&hwstat
->stats_lock
)) {
1004 fe_stats_update(priv
);
1005 spin_unlock(&hwstat
->stats_lock
);
1007 fe_reg_w32(status_intr
, status_reg
);
1010 if (unlikely(netif_msg_intr(priv
))) {
1011 mask
= fe_reg_r32(FE_REG_FE_INT_ENABLE
);
1012 netdev_info(priv
->netdev
,
1013 "done tx %d, rx %d, intr 0x%08x/0x%x\n",
1014 tx_done
, rx_done
, status
, mask
);
1017 if (!tx_again
&& (rx_done
< budget
)) {
1018 status
= fe_reg_r32(FE_REG_FE_INT_STATUS
);
1019 if (status
& (tx_intr
| rx_intr
)) {
1020 /* let napi poll again */
1025 napi_complete_done(napi
, rx_done
);
1026 fe_int_enable(tx_intr
| rx_intr
);
1035 static void fe_tx_timeout(struct net_device
*dev
)
1037 struct fe_priv
*priv
= netdev_priv(dev
);
1038 struct fe_tx_ring
*ring
= &priv
->tx_ring
;
1040 priv
->netdev
->stats
.tx_errors
++;
1041 netif_err(priv
, tx_err
, dev
,
1042 "transmit timed out\n");
1043 netif_info(priv
, drv
, dev
, "dma_cfg:%08x\n",
1044 fe_reg_r32(FE_REG_PDMA_GLO_CFG
));
1045 netif_info(priv
, drv
, dev
, "tx_ring=%d, "
1046 "base=%08x, max=%u, ctx=%u, dtx=%u, fdx=%hu, next=%hu\n",
1047 0, fe_reg_r32(FE_REG_TX_BASE_PTR0
),
1048 fe_reg_r32(FE_REG_TX_MAX_CNT0
),
1049 fe_reg_r32(FE_REG_TX_CTX_IDX0
),
1050 fe_reg_r32(FE_REG_TX_DTX_IDX0
),
1053 netif_info(priv
, drv
, dev
,
1054 "rx_ring=%d, base=%08x, max=%u, calc=%u, drx=%u\n",
1055 0, fe_reg_r32(FE_REG_RX_BASE_PTR0
),
1056 fe_reg_r32(FE_REG_RX_MAX_CNT0
),
1057 fe_reg_r32(FE_REG_RX_CALC_IDX0
),
1058 fe_reg_r32(FE_REG_RX_DRX_IDX0
));
1060 if (!test_and_set_bit(FE_FLAG_RESET_PENDING
, priv
->pending_flags
))
1061 schedule_work(&priv
->pending_work
);
1064 static irqreturn_t
fe_handle_irq(int irq
, void *dev
)
1066 struct fe_priv
*priv
= netdev_priv(dev
);
1067 u32 status
, int_mask
;
1069 status
= fe_reg_r32(FE_REG_FE_INT_STATUS
);
1071 if (unlikely(!status
))
1074 int_mask
= (priv
->soc
->rx_int
| priv
->soc
->tx_int
);
1075 if (likely(status
& int_mask
)) {
1076 if (likely(napi_schedule_prep(&priv
->rx_napi
))) {
1077 fe_int_disable(int_mask
);
1078 __napi_schedule(&priv
->rx_napi
);
1081 fe_reg_w32(status
, FE_REG_FE_INT_STATUS
);
1087 #ifdef CONFIG_NET_POLL_CONTROLLER
1088 static void fe_poll_controller(struct net_device
*dev
)
1090 struct fe_priv
*priv
= netdev_priv(dev
);
1091 u32 int_mask
= priv
->soc
->tx_int
| priv
->soc
->rx_int
;
1093 fe_int_disable(int_mask
);
1094 fe_handle_irq(dev
->irq
, dev
);
1095 fe_int_enable(int_mask
);
1099 int fe_set_clock_cycle(struct fe_priv
*priv
)
1101 unsigned long sysclk
= priv
->sysclk
;
1103 sysclk
/= FE_US_CYC_CNT_DIVISOR
;
1104 sysclk
<<= FE_US_CYC_CNT_SHIFT
;
1106 fe_w32((fe_r32(FE_FE_GLO_CFG
) &
1107 ~(FE_US_CYC_CNT_MASK
<< FE_US_CYC_CNT_SHIFT
)) |
1113 void fe_fwd_config(struct fe_priv
*priv
)
1117 fwd_cfg
= fe_r32(FE_GDMA1_FWD_CFG
);
1119 /* disable jumbo frame */
1120 if (priv
->flags
& FE_FLAG_JUMBO_FRAME
)
1121 fwd_cfg
&= ~FE_GDM1_JMB_EN
;
1123 /* set unicast/multicast/broadcast frame to cpu */
1126 fe_w32(fwd_cfg
, FE_GDMA1_FWD_CFG
);
1129 static void fe_rxcsum_config(bool enable
)
1132 fe_w32(fe_r32(FE_GDMA1_FWD_CFG
) | (FE_GDM1_ICS_EN
|
1133 FE_GDM1_TCS_EN
| FE_GDM1_UCS_EN
),
1136 fe_w32(fe_r32(FE_GDMA1_FWD_CFG
) & ~(FE_GDM1_ICS_EN
|
1137 FE_GDM1_TCS_EN
| FE_GDM1_UCS_EN
),
1141 static void fe_txcsum_config(bool enable
)
1144 fe_w32(fe_r32(FE_CDMA_CSG_CFG
) | (FE_ICS_GEN_EN
|
1145 FE_TCS_GEN_EN
| FE_UCS_GEN_EN
),
1148 fe_w32(fe_r32(FE_CDMA_CSG_CFG
) & ~(FE_ICS_GEN_EN
|
1149 FE_TCS_GEN_EN
| FE_UCS_GEN_EN
),
1153 void fe_csum_config(struct fe_priv
*priv
)
1155 struct net_device
*dev
= priv_netdev(priv
);
1157 fe_txcsum_config((dev
->features
& NETIF_F_IP_CSUM
));
1158 fe_rxcsum_config((dev
->features
& NETIF_F_RXCSUM
));
1161 static int fe_hw_init(struct net_device
*dev
)
1163 struct fe_priv
*priv
= netdev_priv(dev
);
1166 err
= devm_request_irq(priv
->dev
, dev
->irq
, fe_handle_irq
, 0,
1167 dev_name(priv
->dev
), dev
);
1171 if (priv
->soc
->set_mac
)
1172 priv
->soc
->set_mac(priv
, dev
->dev_addr
);
1174 fe_hw_set_macaddr(priv
, dev
->dev_addr
);
1176 /* disable delay interrupt */
1177 fe_reg_w32(0, FE_REG_DLY_INT_CFG
);
1179 fe_int_disable(priv
->soc
->tx_int
| priv
->soc
->rx_int
);
1181 /* frame engine will push VLAN tag regarding to VIDX feild in Tx desc */
1182 if (fe_reg_table
[FE_REG_FE_DMA_VID_BASE
])
1183 for (i
= 0; i
< 16; i
+= 2)
1184 fe_w32(((i
+ 1) << 16) + i
,
1185 fe_reg_table
[FE_REG_FE_DMA_VID_BASE
] +
1188 if (priv
->soc
->fwd_config(priv
))
1189 netdev_err(dev
, "unable to get clock\n");
1191 if (fe_reg_table
[FE_REG_FE_RST_GL
]) {
1192 fe_reg_w32(1, FE_REG_FE_RST_GL
);
1193 fe_reg_w32(0, FE_REG_FE_RST_GL
);
1199 static int fe_open(struct net_device
*dev
)
1201 struct fe_priv
*priv
= netdev_priv(dev
);
1202 unsigned long flags
;
1206 err
= fe_init_dma(priv
);
1212 spin_lock_irqsave(&priv
->page_lock
, flags
);
1214 val
= FE_TX_WB_DDONE
| FE_RX_DMA_EN
| FE_TX_DMA_EN
;
1215 if (priv
->flags
& FE_FLAG_RX_2B_OFFSET
)
1216 val
|= FE_RX_2B_OFFSET
;
1217 val
|= priv
->soc
->pdma_glo_cfg
;
1218 fe_reg_w32(val
, FE_REG_PDMA_GLO_CFG
);
1220 spin_unlock_irqrestore(&priv
->page_lock
, flags
);
1223 priv
->phy
->start(priv
);
1225 if (priv
->soc
->has_carrier
&& priv
->soc
->has_carrier(priv
))
1226 netif_carrier_on(dev
);
1228 napi_enable(&priv
->rx_napi
);
1229 fe_int_enable(priv
->soc
->tx_int
| priv
->soc
->rx_int
);
1230 netif_start_queue(dev
);
1231 #ifdef CONFIG_NET_MEDIATEK_OFFLOAD
1232 mtk_ppe_probe(priv
);
1238 static int fe_stop(struct net_device
*dev
)
1240 struct fe_priv
*priv
= netdev_priv(dev
);
1241 unsigned long flags
;
1244 netif_tx_disable(dev
);
1245 fe_int_disable(priv
->soc
->tx_int
| priv
->soc
->rx_int
);
1246 napi_disable(&priv
->rx_napi
);
1249 priv
->phy
->stop(priv
);
1251 spin_lock_irqsave(&priv
->page_lock
, flags
);
1253 fe_reg_w32(fe_reg_r32(FE_REG_PDMA_GLO_CFG
) &
1254 ~(FE_TX_WB_DDONE
| FE_RX_DMA_EN
| FE_TX_DMA_EN
),
1255 FE_REG_PDMA_GLO_CFG
);
1256 spin_unlock_irqrestore(&priv
->page_lock
, flags
);
1259 for (i
= 0; i
< 10; i
++) {
1260 if (fe_reg_r32(FE_REG_PDMA_GLO_CFG
) &
1261 (FE_TX_DMA_BUSY
| FE_RX_DMA_BUSY
)) {
1270 #ifdef CONFIG_NET_MEDIATEK_OFFLOAD
1271 mtk_ppe_remove(priv
);
1277 static int __init
fe_init(struct net_device
*dev
)
1279 struct fe_priv
*priv
= netdev_priv(dev
);
1280 struct device_node
*port
;
1281 const char *mac_addr
;
1284 priv
->soc
->reset_fe();
1286 if (priv
->soc
->switch_init
)
1287 if (priv
->soc
->switch_init(priv
)) {
1288 netdev_err(dev
, "failed to initialize switch core\n");
1292 mac_addr
= of_get_mac_address(priv
->dev
->of_node
);
1294 ether_addr_copy(dev
->dev_addr
, mac_addr
);
1296 /* If the mac address is invalid, use random mac address */
1297 if (!is_valid_ether_addr(dev
->dev_addr
)) {
1298 random_ether_addr(dev
->dev_addr
);
1299 dev_err(priv
->dev
, "generated random MAC address %pM\n",
1303 err
= fe_mdio_init(priv
);
1307 if (priv
->soc
->port_init
)
1308 for_each_child_of_node(priv
->dev
->of_node
, port
)
1309 if (of_device_is_compatible(port
, "mediatek,eth-port") &&
1310 of_device_is_available(port
))
1311 priv
->soc
->port_init(priv
, port
);
1314 err
= priv
->phy
->connect(priv
);
1316 goto err_phy_disconnect
;
1319 err
= fe_hw_init(dev
);
1321 goto err_phy_disconnect
;
1323 if ((priv
->flags
& FE_FLAG_HAS_SWITCH
) && priv
->soc
->switch_config
)
1324 priv
->soc
->switch_config(priv
);
1330 priv
->phy
->disconnect(priv
);
1331 fe_mdio_cleanup(priv
);
1336 static void fe_uninit(struct net_device
*dev
)
1338 struct fe_priv
*priv
= netdev_priv(dev
);
1341 priv
->phy
->disconnect(priv
);
1342 fe_mdio_cleanup(priv
);
1344 fe_reg_w32(0, FE_REG_FE_INT_ENABLE
);
1345 free_irq(dev
->irq
, dev
);
1348 static int fe_do_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
1350 struct fe_priv
*priv
= netdev_priv(dev
);
1357 return phy_ethtool_ioctl(priv
->phy_dev
,
1358 (void *) ifr
->ifr_data
);
1362 return phy_mii_ioctl(priv
->phy_dev
, ifr
, cmd
);
1370 static int fe_change_mtu(struct net_device
*dev
, int new_mtu
)
1372 struct fe_priv
*priv
= netdev_priv(dev
);
1373 int frag_size
, old_mtu
;
1379 if (!(priv
->flags
& FE_FLAG_JUMBO_FRAME
))
1382 /* return early if the buffer sizes will not change */
1383 if (old_mtu
<= ETH_DATA_LEN
&& new_mtu
<= ETH_DATA_LEN
)
1385 if (old_mtu
> ETH_DATA_LEN
&& new_mtu
> ETH_DATA_LEN
)
1388 if (new_mtu
<= ETH_DATA_LEN
)
1389 priv
->rx_ring
.frag_size
= fe_max_frag_size(ETH_DATA_LEN
);
1391 priv
->rx_ring
.frag_size
= PAGE_SIZE
;
1392 priv
->rx_ring
.rx_buf_size
= fe_max_buf_size(priv
->rx_ring
.frag_size
);
1394 if (!netif_running(dev
))
1398 if (!IS_ENABLED(CONFIG_SOC_MT7621
)) {
1399 fwd_cfg
= fe_r32(FE_GDMA1_FWD_CFG
);
1400 if (new_mtu
<= ETH_DATA_LEN
) {
1401 fwd_cfg
&= ~FE_GDM1_JMB_EN
;
1403 frag_size
= fe_max_frag_size(new_mtu
);
1404 fwd_cfg
&= ~(FE_GDM1_JMB_LEN_MASK
<< FE_GDM1_JMB_LEN_SHIFT
);
1405 fwd_cfg
|= (DIV_ROUND_UP(frag_size
, 1024) <<
1406 FE_GDM1_JMB_LEN_SHIFT
) | FE_GDM1_JMB_EN
;
1408 fe_w32(fwd_cfg
, FE_GDMA1_FWD_CFG
);
1411 return fe_open(dev
);
1414 #ifdef CONFIG_NET_MEDIATEK_OFFLOAD
1416 fe_flow_offload(enum flow_offload_type type
, struct flow_offload
*flow
,
1417 struct flow_offload_hw_path
*src
,
1418 struct flow_offload_hw_path
*dest
)
1420 struct fe_priv
*priv
;
1422 if (src
->dev
!= dest
->dev
)
1425 priv
= netdev_priv(src
->dev
);
1427 return mtk_flow_offload(priv
, type
, flow
, src
, dest
);
1431 static const struct net_device_ops fe_netdev_ops
= {
1432 .ndo_init
= fe_init
,
1433 .ndo_uninit
= fe_uninit
,
1434 .ndo_open
= fe_open
,
1435 .ndo_stop
= fe_stop
,
1436 .ndo_start_xmit
= fe_start_xmit
,
1437 .ndo_set_mac_address
= fe_set_mac_address
,
1438 .ndo_validate_addr
= eth_validate_addr
,
1439 .ndo_do_ioctl
= fe_do_ioctl
,
1440 .ndo_change_mtu
= fe_change_mtu
,
1441 .ndo_tx_timeout
= fe_tx_timeout
,
1442 .ndo_get_stats64
= fe_get_stats64
,
1443 .ndo_vlan_rx_add_vid
= fe_vlan_rx_add_vid
,
1444 .ndo_vlan_rx_kill_vid
= fe_vlan_rx_kill_vid
,
1445 #ifdef CONFIG_NET_POLL_CONTROLLER
1446 .ndo_poll_controller
= fe_poll_controller
,
1448 #ifdef CONFIG_NET_MEDIATEK_OFFLOAD
1449 .ndo_flow_offload
= fe_flow_offload
,
1453 static void fe_reset_pending(struct fe_priv
*priv
)
1455 struct net_device
*dev
= priv
->netdev
;
1463 netif_alert(priv
, ifup
, dev
,
1464 "Driver up/down cycle failed, closing device.\n");
1470 static const struct fe_work_t fe_work
[] = {
1471 {FE_FLAG_RESET_PENDING
, fe_reset_pending
},
1474 static void fe_pending_work(struct work_struct
*work
)
1476 struct fe_priv
*priv
= container_of(work
, struct fe_priv
, pending_work
);
1480 for (i
= 0; i
< ARRAY_SIZE(fe_work
); i
++) {
1481 pending
= test_and_clear_bit(fe_work
[i
].bitnr
,
1482 priv
->pending_flags
);
1484 fe_work
[i
].action(priv
);
1488 static int fe_probe(struct platform_device
*pdev
)
1490 struct resource
*res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1491 const struct of_device_id
*match
;
1492 struct fe_soc_data
*soc
;
1493 struct net_device
*netdev
;
1494 struct fe_priv
*priv
;
1496 int err
, napi_weight
;
1498 device_reset(&pdev
->dev
);
1500 match
= of_match_device(of_fe_match
, &pdev
->dev
);
1501 soc
= (struct fe_soc_data
*)match
->data
;
1504 fe_reg_table
= soc
->reg_table
;
1506 soc
->reg_table
= fe_reg_table
;
1508 fe_base
= devm_ioremap_resource(&pdev
->dev
, res
);
1509 if (IS_ERR(fe_base
)) {
1510 err
= -EADDRNOTAVAIL
;
1514 netdev
= alloc_etherdev(sizeof(*priv
));
1516 dev_err(&pdev
->dev
, "alloc_etherdev failed\n");
1521 SET_NETDEV_DEV(netdev
, &pdev
->dev
);
1522 netdev
->netdev_ops
= &fe_netdev_ops
;
1523 netdev
->base_addr
= (unsigned long)fe_base
;
1525 netdev
->irq
= platform_get_irq(pdev
, 0);
1526 if (netdev
->irq
< 0) {
1527 dev_err(&pdev
->dev
, "no IRQ resource found\n");
1533 soc
->init_data(soc
, netdev
);
1534 netdev
->vlan_features
= netdev
->hw_features
& ~NETIF_F_HW_VLAN_CTAG_TX
;
1535 netdev
->features
|= netdev
->hw_features
;
1537 if (IS_ENABLED(CONFIG_SOC_MT7621
))
1538 netdev
->max_mtu
= 2048;
1540 /* fake rx vlan filter func. to support tx vlan offload func */
1541 if (fe_reg_table
[FE_REG_FE_DMA_VID_BASE
])
1542 netdev
->features
|= NETIF_F_HW_VLAN_CTAG_FILTER
;
1544 priv
= netdev_priv(netdev
);
1545 spin_lock_init(&priv
->page_lock
);
1546 if (fe_reg_table
[FE_REG_FE_COUNTER_BASE
]) {
1547 priv
->hw_stats
= kzalloc(sizeof(*priv
->hw_stats
), GFP_KERNEL
);
1548 if (!priv
->hw_stats
) {
1552 spin_lock_init(&priv
->hw_stats
->stats_lock
);
1555 sysclk
= devm_clk_get(&pdev
->dev
, NULL
);
1556 if (!IS_ERR(sysclk
)) {
1557 priv
->sysclk
= clk_get_rate(sysclk
);
1558 } else if ((priv
->flags
& FE_FLAG_CALIBRATE_CLK
)) {
1559 dev_err(&pdev
->dev
, "this soc needs a clk for calibration\n");
1564 priv
->switch_np
= of_parse_phandle(pdev
->dev
.of_node
, "mediatek,switch", 0);
1565 if ((priv
->flags
& FE_FLAG_HAS_SWITCH
) && !priv
->switch_np
) {
1566 dev_err(&pdev
->dev
, "failed to read switch phandle\n");
1571 priv
->netdev
= netdev
;
1572 priv
->dev
= &pdev
->dev
;
1574 priv
->msg_enable
= netif_msg_init(fe_msg_level
, FE_DEFAULT_MSG_ENABLE
);
1575 priv
->rx_ring
.frag_size
= fe_max_frag_size(ETH_DATA_LEN
);
1576 priv
->rx_ring
.rx_buf_size
= fe_max_buf_size(priv
->rx_ring
.frag_size
);
1577 priv
->tx_ring
.tx_ring_size
= NUM_DMA_DESC
;
1578 priv
->rx_ring
.rx_ring_size
= NUM_DMA_DESC
;
1579 INIT_WORK(&priv
->pending_work
, fe_pending_work
);
1580 u64_stats_init(&priv
->hw_stats
->syncp
);
1583 if (priv
->flags
& FE_FLAG_NAPI_WEIGHT
) {
1585 priv
->tx_ring
.tx_ring_size
*= 4;
1586 priv
->rx_ring
.rx_ring_size
*= 4;
1588 netif_napi_add(netdev
, &priv
->rx_napi
, fe_poll
, napi_weight
);
1589 fe_set_ethtool_ops(netdev
);
1591 err
= register_netdev(netdev
);
1593 dev_err(&pdev
->dev
, "error bringing up device\n");
1597 platform_set_drvdata(pdev
, netdev
);
1599 netif_info(priv
, probe
, netdev
, "mediatek frame engine at 0x%08lx, irq %d\n",
1600 netdev
->base_addr
, netdev
->irq
);
1605 free_netdev(netdev
);
1607 devm_iounmap(&pdev
->dev
, fe_base
);
1612 static int fe_remove(struct platform_device
*pdev
)
1614 struct net_device
*dev
= platform_get_drvdata(pdev
);
1615 struct fe_priv
*priv
= netdev_priv(dev
);
1617 netif_napi_del(&priv
->rx_napi
);
1618 kfree(priv
->hw_stats
);
1620 cancel_work_sync(&priv
->pending_work
);
1622 unregister_netdev(dev
);
1624 platform_set_drvdata(pdev
, NULL
);
1629 static struct platform_driver fe_driver
= {
1631 .remove
= fe_remove
,
1633 .name
= "mtk_soc_eth",
1634 .owner
= THIS_MODULE
,
1635 .of_match_table
= of_fe_match
,
1639 module_platform_driver(fe_driver
);
1641 MODULE_LICENSE("GPL");
1642 MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
1643 MODULE_DESCRIPTION("Ethernet driver for Ralink SoC");
1644 MODULE_VERSION(MTK_FE_DRV_VERSION
);