1 /* This program is free software; you can redistribute it and/or modify
2 * it under the terms of the GNU General Public License as published by
3 * the Free Software Foundation; version 2 of the License
5 * This program is distributed in the hope that it will be useful,
6 * but WITHOUT ANY WARRANTY; without even the implied warranty of
7 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
8 * GNU General Public License for more details.
10 * Copyright (C) 2014-2016 Sean Wang <sean.wang@mediatek.com>
11 * Copyright (C) 2016-2017 John Crispin <blogic@openwrt.org>
14 #include <linux/dma-mapping.h>
15 #include <linux/delay.h>
18 #include <linux/module.h>
19 #include <linux/of_device.h>
20 #include <linux/platform_device.h>
21 #include <linux/reset.h>
22 #include <linux/netfilter.h>
23 #include <linux/netdevice.h>
24 #include <net/netfilter/nf_flow_table.h>
25 #include <linux/debugfs.h>
26 #include <linux/etherdevice.h>
27 #include <linux/bitfield.h>
29 #include "mtk_eth_soc.h"
33 #define mtk_eth fe_priv
34 #define MTK_GDMA_FWD_CFG(x) (0x500 + (x * 0x1000))
35 #define mtk_m32 fe_m32
38 mtk_r32(struct mtk_eth
*eth
, u32 reg
)
44 mtk_w32(struct mtk_eth
*eth
, u32 val
, u32 reg
)
50 #define MTK_REG_PPE_GLO_CFG 0xe00
51 #define MTK_PPE_GLO_CFG_BUSY BIT(31)
52 #define MTK_PPE_GLO_CFG_TTL0_DROP BIT(4)
53 #define MTK_PPE_GLO_CFG_EN BIT(0)
55 #define MTK_REG_PPE_FLOW_CFG 0xe04
56 #define MTK_PPE_FLOW_CFG_IPV4_GREK_EN BIT(19)
57 #define MTK_PPE_FLOW_CFG_IPV4_NAT_FRAG_EN BIT(17)
58 #define MTK_PPE_FLOW_CFG_IPV4_NAPT_EN BIT(13)
59 #define MTK_PPE_FLOW_CFG_IPV4_NAT_EN BIT(12)
60 #define MTK_PPE_FLOW_CFG_FUC_FOE BIT(2)
61 #define MTK_PPE_FLOW_CFG_FMC_FOE BIT(1)
63 #define MTK_REG_PPE_IP_PROT_CHK 0xe08
65 #define MTK_REG_PPE_TB_BASE 0xe20
67 #define MTK_REG_PPE_BNDR 0xe28
68 #define MTK_PPE_BNDR_RATE_MASK 0xffff
70 #define MTK_REG_PPE_BIND_LMT_0 0xe2C
72 #define MTK_REG_PPE_BIND_LMT_1 0xe30
73 #define MTK_PPE_NTU_KA BIT(16)
75 #define MTK_REG_PPE_KA 0xe34
76 #define MTK_PPE_KA_T BIT(0)
77 #define MTK_PPE_KA_TCP BIT(16)
78 #define MTK_PPE_KA_UDP BIT(24)
80 #define MTK_REG_PPE_UNB_AGE 0xe38
81 #define MTK_PPE_UNB_AGE_MNP_MASK (0xffff << 16)
82 #define MTK_PPE_UNB_AGE_MNP (1000 << 16)
83 #define MTK_PPE_UNB_AGE_DLTA_MASK 0xff
84 #define MTK_PPE_UNB_AGE_DLTA 3
86 #define MTK_REG_PPE_BND_AGE0 0xe3c
87 #define MTK_PPE_BND_AGE0_NTU_DLTA_MASK (0xffff << 16)
88 #define MTK_PPE_BND_AGE0_NTU_DLTA (5 << 16)
89 #define MTK_PPE_BND_AGE0_UDP_DLTA_MASK 0xffff
90 #define MTK_PPE_BND_AGE0_UDP_DLTA 5
92 #define MTK_REG_PPE_BND_AGE1 0xe40
93 #define MTK_PPE_BND_AGE1_FIN_DLTA_MASK (0xffff << 16)
94 #define MTK_PPE_BND_AGE1_FIN_DLTA (5 << 16)
95 #define MTK_PPE_BND_AGE1_TCP_DLTA_MASK 0xffff
96 #define MTK_PPE_BND_AGE1_TCP_DLTA 5
98 #define MTK_REG_PPE_DFT_CPORT 0xe48
100 #define MTK_REG_PPE_TB_CFG 0xe1c
101 #define MTK_PPE_TB_CFG_X_MODE_MASK (3 << 18)
102 #define MTK_PPE_TB_CFG_HASH_MODE1 BIT(14)
103 #define MTK_PPE_TB_CFG_HASH_MODE_MASK (0x3 << 14)
104 #define MTK_PPE_TB_CFG_KA (3 << 12)
105 #define MTK_PPE_TB_CFG_KA_MASK (0x3 << 12)
106 #define MTK_PPE_TB_CFG_FIN_AGE BIT(11)
107 #define MTK_PPE_TB_CFG_UDP_AGE BIT(10)
108 #define MTK_PPE_TB_CFG_TCP_AGE BIT(9)
109 #define MTK_PPE_TB_CFG_UNBD_AGE BIT(8)
110 #define MTK_PPE_TB_CFG_NTU_AGE BIT(7)
111 #define MTK_PPE_TB_CFG_SMA_FWD_CPU (0x3 << 4)
112 #define MTK_PPE_TB_CFG_SMA_MASK (0x3 << 4)
113 #define MTK_PPE_TB_CFG_ENTRY_SZ_64B 0
114 #define MTK_PPE_TB_CFG_ENTRY_SZ_MASK BIT(3)
115 #define MTK_PPE_TB_CFG_TBL_SZ_4K 2
116 #define MTK_PPE_TB_CFG_TBL_SZ_MASK 0x7
118 #define MTK_REG_PPE_HASH_SEED 0xe44
119 #define MTK_PPE_HASH_SEED 0x12345678
122 #define MTK_REG_PPE_CAH_CTRL 0xf20
123 #define MTK_PPE_CAH_CTRL_X_MODE BIT(9)
124 #define MTK_PPE_CAH_CTRL_EN BIT(0)
126 struct mtk_foe_unbind_info_blk
{
128 u32 pcnt
:16; /* packet count */
133 u32 sta
:1; /* static entry */
134 } __attribute__ ((packed
));
136 struct mtk_foe_bind_info_blk
{
138 u32 ka
:1; /* keep alive */
140 u32 psn
:1; /* egress packet has PPPoE session */
142 u32 vpm
:2; /* 0:ethertype remark, 1:0x8100(CR default) */
144 u32 vpm
:1; /* 0:ethertype remark, 1:0x8100(CR default) */
145 u32 ps
:1; /* packet sampling */
147 u32 cah
:1; /* cacheable flag */
148 u32 rmt
:1; /* remove tunnel ip header (6rd/dslite only) */
153 u32 sta
:1; /* static entry */
154 } __attribute__ ((packed
));
156 struct mtk_foe_info_blk2
{
157 u32 qid
:4; /* QID in Qos Port */
158 u32 fqos
:1; /* force to PSE QoS port */
159 u32 dp
:3; /* force to PSE port x
160 0:PSE,1:GSW, 2:GMAC,4:PPE,5:QDMA,7=DROP */
161 u32 mcast
:1; /* multicast this packet to CPU */
162 u32 pcpl
:1; /* OSBN */
163 u32 mlen
:1; /* 0:post 1:pre packet length in meter */
164 u32 alen
:1; /* 0:post 1:pre packet length in accounting */
165 u32 port_mg
:6; /* port meter group */
166 u32 port_ag
:6; /* port account group */
167 u32 dscp
:8; /* DSCP value */
168 } __attribute__ ((packed
));
170 struct mtk_foe_ipv4_hnapt
{
172 struct mtk_foe_bind_info_blk bfib1
;
173 struct mtk_foe_unbind_info_blk udib1
;
181 struct mtk_foe_info_blk2 iblk2
;
191 u32 act_dp
:6; /* UDF */
200 } __attribute__ ((packed
));
202 struct mtk_foe_entry
{
204 struct mtk_foe_unbind_info_blk udib1
;
205 struct mtk_foe_bind_info_blk bfib1
;
206 struct mtk_foe_ipv4_hnapt ipv4_hnapt
;
210 enum mtk_foe_entry_state
{
211 FOE_STATE_INVALID
= 0,
212 FOE_STATE_UNBIND
= 1,
218 #define MTK_RXD4_FOE_ENTRY GENMASK(13, 0)
219 #define MTK_RXD4_CPU_REASON GENMASK(18, 14)
220 #define MTK_RXD4_SRC_PORT GENMASK(21, 19)
221 #define MTK_RXD4_ALG GENMASK(31, 22)
223 enum mtk_foe_cpu_reason
{
224 MTK_CPU_REASON_TTL_EXCEEDED
= 0x02,
225 MTK_CPU_REASON_OPTION_HEADER
= 0x03,
226 MTK_CPU_REASON_NO_FLOW
= 0x07,
227 MTK_CPU_REASON_IPV4_FRAG
= 0x08,
228 MTK_CPU_REASON_IPV4_DSLITE_FRAG
= 0x09,
229 MTK_CPU_REASON_IPV4_DSLITE_NO_TCP_UDP
= 0x0a,
230 MTK_CPU_REASON_IPV6_6RD_NO_TCP_UDP
= 0x0b,
231 MTK_CPU_REASON_TCP_FIN_SYN_RST
= 0x0c,
232 MTK_CPU_REASON_UN_HIT
= 0x0d,
233 MTK_CPU_REASON_HIT_UNBIND
= 0x0e,
234 MTK_CPU_REASON_HIT_UNBIND_RATE_REACHED
= 0x0f,
235 MTK_CPU_REASON_HIT_BIND_TCP_FIN
= 0x10,
236 MTK_CPU_REASON_HIT_TTL_1
= 0x11,
237 MTK_CPU_REASON_HIT_BIND_VLAN_VIOLATION
= 0x12,
238 MTK_CPU_REASON_KEEPALIVE_UC_OLD_HDR
= 0x13,
239 MTK_CPU_REASON_KEEPALIVE_MC_NEW_HDR
= 0x14,
240 MTK_CPU_REASON_KEEPALIVE_DUP_OLD_HDR
= 0x15,
241 MTK_CPU_REASON_HIT_BIND_FORCE_CPU
= 0x16,
242 MTK_CPU_REASON_TUNNEL_OPTION_HEADER
= 0x17,
243 MTK_CPU_REASON_MULTICAST_TO_CPU
= 0x18,
244 MTK_CPU_REASON_MULTICAST_TO_GMAC1_CPU
= 0x19,
245 MTK_CPU_REASON_HIT_PRE_BIND
= 0x1a,
246 MTK_CPU_REASON_PACKET_SAMPLING
= 0x1b,
247 MTK_CPU_REASON_EXCEED_MTU
= 0x1c,
248 MTK_CPU_REASON_PPE_BYPASS
= 0x1e,
249 MTK_CPU_REASON_INVALID
= 0x1f,
253 /* our table size is 4K */
254 #define MTK_PPE_ENTRY_CNT 0x1000
255 #define MTK_PPE_TBL_SZ \
256 (MTK_PPE_ENTRY_CNT * sizeof(struct mtk_foe_entry))
258 int mtk_ppe_debugfs_init(struct mtk_eth
*eth
);