4935b7fbd43e6d2c57c5c966bbf4ddf7a0867cf0
1 /* This program is free software; you can redistribute it and/or modify
2 * it under the terms of the GNU General Public License as published by
3 * the Free Software Foundation; version 2 of the License
5 * This program is distributed in the hope that it will be useful,
6 * but WITHOUT ANY WARRANTY; without even the implied warranty of
7 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
8 * GNU General Public License for more details.
10 * Copyright (C) 2009-2015 John Crispin <blogic@openwrt.org>
11 * Copyright (C) 2009-2015 Felix Fietkau <nbd@nbd.name>
12 * Copyright (C) 2013-2015 Michael Lee <igvtee@gmail.com>
15 #include <linux/module.h>
17 #include <asm/mach-ralink/ralink_regs.h>
19 #include "mtk_eth_soc.h"
20 #include "mdio_rt2880.h"
22 #define RT3883_RSTCTRL_FE BIT(21)
24 static void rt3883_fe_reset(void)
26 fe_reset(RT3883_RSTCTRL_FE
);
29 static int rt3883_fwd_config(struct fe_priv
*priv
)
33 ret
= fe_set_clock_cycle(priv
);
38 fe_w32(FE_PSE_FQFC_CFG_256Q
, FE_PSE_FQ_CFG
);
44 static void rt3883_init_data(struct fe_soc_data
*data
,
45 struct net_device
*netdev
)
47 struct fe_priv
*priv
= netdev_priv(netdev
);
49 priv
->flags
= FE_FLAG_PADDING_64B
| FE_FLAG_PADDING_BUG
|
50 FE_FLAG_JUMBO_FRAME
| FE_FLAG_CALIBRATE_CLK
;
51 netdev
->hw_features
= NETIF_F_SG
| NETIF_F_IP_CSUM
|
52 NETIF_F_RXCSUM
| NETIF_F_HW_VLAN_CTAG_TX
;
55 static struct fe_soc_data rt3883_data
= {
56 .init_data
= rt3883_init_data
,
57 .reset_fe
= rt3883_fe_reset
,
58 .fwd_config
= rt3883_fwd_config
,
59 .pdma_glo_cfg
= FE_PDMA_SIZE_8DWORDS
,
60 .rx_int
= FE_RX_DONE_INT
,
61 .tx_int
= FE_TX_DONE_INT
,
62 .status_int
= FE_CNT_GDM_AF
,
63 .checksum_bit
= RX_DMA_L4VALID
,
64 .mdio_read
= rt2880_mdio_read
,
65 .mdio_write
= rt2880_mdio_write
,
66 .mdio_adjust_link
= rt2880_mdio_link_adjust
,
67 .port_init
= rt2880_port_init
,
70 const struct of_device_id of_fe_match
[] = {
71 { .compatible
= "ralink,rt3883-eth", .data
= &rt3883_data
},
75 MODULE_DEVICE_TABLE(of
, of_fe_match
);