1 /* This program is free software; you can redistribute it and/or modify
2 * it under the terms of the GNU General Public License as published by
3 * the Free Software Foundation; version 2 of the License
5 * This program is distributed in the hope that it will be useful,
6 * but WITHOUT ANY WARRANTY; without even the implied warranty of
7 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
8 * GNU General Public License for more details.
10 * Copyright (C) 2009-2015 John Crispin <blogic@openwrt.org>
11 * Copyright (C) 2009-2015 Felix Fietkau <nbd@nbd.name>
12 * Copyright (C) 2013-2015 Michael Lee <igvtee@gmail.com>
15 #include <linux/module.h>
16 #include <linux/kernel.h>
17 #include <linux/types.h>
18 #include <linux/platform_device.h>
19 #include <linux/of_device.h>
20 #include <linux/of_irq.h>
22 #include <ralink_regs.h>
24 #include "mtk_eth_soc.h"
25 #include "gsw_mt7620.h"
27 void mtk_switch_w32(struct mt7620_gsw
*gsw
, u32 val
, unsigned reg
)
29 iowrite32(val
, gsw
->base
+ reg
);
32 u32
mtk_switch_r32(struct mt7620_gsw
*gsw
, unsigned reg
)
34 return ioread32(gsw
->base
+ reg
);
37 static irqreturn_t
gsw_interrupt_mt7621(int irq
, void *_priv
)
39 struct fe_priv
*priv
= (struct fe_priv
*)_priv
;
40 struct mt7620_gsw
*gsw
= (struct mt7620_gsw
*)priv
->soc
->swpriv
;
43 reg
= mt7530_mdio_r32(gsw
, 0x700c);
45 for (i
= 0; i
< 5; i
++)
49 link
= mt7530_mdio_r32(gsw
,
50 0x3008 + (i
* 0x100)) & 0x1;
52 if (link
!= priv
->link
[i
]) {
55 netdev_info(priv
->netdev
,
56 "port %d link up\n", i
);
58 netdev_info(priv
->netdev
,
59 "port %d link down\n", i
);
63 mt7620_handle_carrier(priv
);
64 mt7530_mdio_w32(gsw
, 0x700c, 0x1f);
69 static void mt7621_hw_init(struct mt7620_gsw
*gsw
, struct device_node
*np
)
74 /* wardware reset the switch */
75 fe_reset(RST_CTRL_MCM
);
78 /* reduce RGMII2 PAD driving strength */
79 rt_sysc_m32(3 << 4, 0, SYSC_PAD_RGMII2_MDIO
);
81 /* gpio mux - RGMII1=Normal mode */
82 rt_sysc_m32(BIT(14), 0, SYSC_GPIO_MODE
);
84 /* set GMAC1 RGMII mode */
85 rt_sysc_m32(3 << 12, 0, SYSC_REG_CFG1
);
87 /* enable MDIO to control MT7530 */
88 rt_sysc_m32(3 << 12, 0, SYSC_GPIO_MODE
);
90 /* turn off all PHYs */
91 for (i
= 0; i
<= 4; i
++) {
92 val
= _mt7620_mii_read(gsw
, i
, 0x0);
94 _mt7620_mii_write(gsw
, i
, 0x0, val
);
97 /* reset the switch */
98 mt7530_mdio_w32(gsw
, 0x7000, 0x3);
101 if ((rt_sysc_r32(SYSC_REG_CHIP_REV_ID
) & 0xFFFF) == 0x0101) {
102 /* (GE1, Force 1000M/FD, FC ON, MAX_RX_LENGTH 1536) */
103 mtk_switch_w32(gsw
, 0x2105e30b, 0x100);
104 mt7530_mdio_w32(gsw
, 0x3600, 0x5e30b);
106 /* (GE1, Force 1000M/FD, FC ON, MAX_RX_LENGTH 1536) */
107 mtk_switch_w32(gsw
, 0x2105e33b, 0x100);
108 mt7530_mdio_w32(gsw
, 0x3600, 0x5e33b);
111 /* (GE2, Link down) */
112 mtk_switch_w32(gsw
, 0x8000, 0x200);
114 /* Enable Port 6, P5 as GMAC5, P5 disable */
115 val
= mt7530_mdio_r32(gsw
, 0x7804);
117 val
|= BIT(6) | BIT(13) | BIT(16);
118 mt7530_mdio_w32(gsw
, 0x7804, val
);
120 val
= rt_sysc_r32(0x10);
121 val
= (val
>> 6) & 0x7;
123 /* 25Mhz Xtal - do nothing */
124 } else if (val
>= 3) {
127 /* disable MT7530 core clock */
128 _mt7620_mii_write(gsw
, 0, 13, 0x1f);
129 _mt7620_mii_write(gsw
, 0, 14, 0x410);
130 _mt7620_mii_write(gsw
, 0, 13, 0x401f);
131 _mt7620_mii_write(gsw
, 0, 14, 0x0);
133 /* disable MT7530 PLL */
134 _mt7620_mii_write(gsw
, 0, 13, 0x1f);
135 _mt7620_mii_write(gsw
, 0, 14, 0x40d);
136 _mt7620_mii_write(gsw
, 0, 13, 0x401f);
137 _mt7620_mii_write(gsw
, 0, 14, 0x2020);
139 /* for MT7530 core clock = 500Mhz */
140 _mt7620_mii_write(gsw
, 0, 13, 0x1f);
141 _mt7620_mii_write(gsw
, 0, 14, 0x40e);
142 _mt7620_mii_write(gsw
, 0, 13, 0x401f);
143 _mt7620_mii_write(gsw
, 0, 14, 0x119);
145 /* enable MT7530 PLL */
146 _mt7620_mii_write(gsw
, 0, 13, 0x1f);
147 _mt7620_mii_write(gsw
, 0, 14, 0x40d);
148 _mt7620_mii_write(gsw
, 0, 13, 0x401f);
149 _mt7620_mii_write(gsw
, 0, 14, 0x2820);
151 usleep_range(20, 40);
153 /* enable MT7530 core clock */
154 _mt7620_mii_write(gsw
, 0, 13, 0x1f);
155 _mt7620_mii_write(gsw
, 0, 14, 0x410);
156 _mt7620_mii_write(gsw
, 0, 13, 0x401f);
158 /* 20Mhz Xtal - TODO */
162 _mt7620_mii_write(gsw
, 0, 14, 0x1);
164 /* set MT7530 central align */
165 val
= mt7530_mdio_r32(gsw
, 0x7830);
168 mt7530_mdio_w32(gsw
, 0x7830, val
);
169 val
= mt7530_mdio_r32(gsw
, 0x7a40);
171 mt7530_mdio_w32(gsw
, 0x7a40, val
);
172 mt7530_mdio_w32(gsw
, 0x7a78, 0x855);
174 /* delay setting for 10/1000M */
175 mt7530_mdio_w32(gsw
, 0x7b00, 0x102);
176 mt7530_mdio_w32(gsw
, 0x7b04, 0x14);
178 /* lower Tx Driving*/
179 mt7530_mdio_w32(gsw
, 0x7a54, 0x44);
180 mt7530_mdio_w32(gsw
, 0x7a5c, 0x44);
181 mt7530_mdio_w32(gsw
, 0x7a64, 0x44);
182 mt7530_mdio_w32(gsw
, 0x7a6c, 0x44);
183 mt7530_mdio_w32(gsw
, 0x7a74, 0x44);
184 mt7530_mdio_w32(gsw
, 0x7a7c, 0x44);
186 /* turn on all PHYs */
187 for (i
= 0; i
<= 4; i
++) {
188 val
= _mt7620_mii_read(gsw
, i
, 0);
190 _mt7620_mii_write(gsw
, i
, 0, val
);
194 val
= mt7530_mdio_r32(gsw
, 0x7808);
196 mt7530_mdio_w32(gsw
, 0x7808, val
);
199 static const struct of_device_id mediatek_gsw_match
[] = {
200 { .compatible
= "mediatek,mt7621-gsw" },
203 MODULE_DEVICE_TABLE(of
, mediatek_gsw_match
);
205 int mtk_gsw_init(struct fe_priv
*priv
)
207 struct device_node
*np
= priv
->switch_np
;
208 struct platform_device
*pdev
= of_find_device_by_node(np
);
209 struct mt7620_gsw
*gsw
;
214 if (!of_device_is_compatible(np
, mediatek_gsw_match
->compatible
))
217 gsw
= platform_get_drvdata(pdev
);
218 priv
->soc
->swpriv
= gsw
;
220 mt7621_hw_init(gsw
, np
);
223 request_irq(gsw
->irq
, gsw_interrupt_mt7621
, 0,
225 mt7530_mdio_w32(gsw
, 0x7008, 0x1f);
231 static int mt7621_gsw_probe(struct platform_device
*pdev
)
233 struct resource
*res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
234 const char *port4
= NULL
;
235 struct mt7620_gsw
*gsw
;
236 struct device_node
*np
;
238 gsw
= devm_kzalloc(&pdev
->dev
, sizeof(struct mt7620_gsw
), GFP_KERNEL
);
242 gsw
->base
= devm_ioremap_resource(&pdev
->dev
, res
);
244 return -EADDRNOTAVAIL
;
246 gsw
->dev
= &pdev
->dev
;
248 of_property_read_string(np
, "mediatek,port4", &port4
);
249 if (port4
&& !strcmp(port4
, "ephy"))
250 gsw
->port4
= PORT4_EPHY
;
251 else if (port4
&& !strcmp(port4
, "gmac"))
252 gsw
->port4
= PORT4_EXT
;
254 gsw
->port4
= PORT4_EPHY
;
256 gsw
->irq
= platform_get_irq(pdev
, 0);
258 platform_set_drvdata(pdev
, gsw
);
263 static int mt7621_gsw_remove(struct platform_device
*pdev
)
265 platform_set_drvdata(pdev
, NULL
);
270 static struct platform_driver gsw_driver
= {
271 .probe
= mt7621_gsw_probe
,
272 .remove
= mt7621_gsw_remove
,
274 .name
= "mt7621-gsw",
275 .owner
= THIS_MODULE
,
276 .of_match_table
= mediatek_gsw_match
,
280 module_platform_driver(gsw_driver
);
282 MODULE_LICENSE("GPL");
283 MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
284 MODULE_DESCRIPTION("GBit switch driver for Mediatek MT7621 SoC");
285 MODULE_VERSION(MTK_FE_DRV_VERSION
);