1 From f281fdccbb3e762d293e6eef7f291a33b84e0f6a Mon Sep 17 00:00:00 2001
2 From: Ralf Baechle <ralf@linux-mips.org>
3 Date: Thu, 20 Jun 2013 14:56:17 +0200
4 Subject: [PATCH 200/215] MIPS: Fix TLBR-use hazards for R2 cores in the TLB
7 MIPS R2 documents state that an execution hazard barrier is needed
8 after a TLBR before reading EntryLo.
10 Original patch by Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>.
12 Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
13 Patchwork: https://patchwork.linux-mips.org/patch/5526/
14 (cherry picked from commit 73acc7df534ff458a81435178dab3ea037ed6d78)
16 arch/mips/mm/tlbex.c | 26 ++++++++++++++++++++++++++
17 1 file changed, 26 insertions(+)
19 --- a/arch/mips/mm/tlbex.c
20 +++ b/arch/mips/mm/tlbex.c
21 @@ -1935,6 +1935,19 @@ static void __cpuinit build_r4000_tlb_lo
26 + switch (current_cpu_type()) {
28 + if (cpu_has_mips_r2) {
31 + case CPU_CAVIUM_OCTEON:
32 + case CPU_CAVIUM_OCTEON_PLUS:
33 + case CPU_CAVIUM_OCTEON2:
38 /* Examine entrylo 0 or 1 based on ptr. */
39 if (use_bbit_insns()) {
40 uasm_i_bbit0(&p, wr.r2, ilog2(sizeof(pte_t)), 8);
41 @@ -1989,6 +2002,19 @@ static void __cpuinit build_r4000_tlb_lo
46 + switch (current_cpu_type()) {
48 + if (cpu_has_mips_r2) {
51 + case CPU_CAVIUM_OCTEON:
52 + case CPU_CAVIUM_OCTEON_PLUS:
53 + case CPU_CAVIUM_OCTEON2:
58 /* Examine entrylo 0 or 1 based on ptr. */
59 if (use_bbit_insns()) {
60 uasm_i_bbit0(&p, wr.r2, ilog2(sizeof(pte_t)), 8);