1 From 259ce690b20562aa5dfef711e72ed02a4f514ce4 Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Sun, 16 Mar 2014 05:19:37 +0000
4 Subject: [PATCH 206/215] MIPS: ralink: add MT7621 support
6 Signed-off-by: John Crispin <blogic@openwrt.org>
8 arch/mips/include/asm/gic.h | 2 +
9 arch/mips/include/asm/mach-ralink/mt7621.h | 39 ++++
10 arch/mips/kernel/vmlinux.lds.S | 1 +
11 arch/mips/ralink/Kconfig | 18 ++
12 arch/mips/ralink/Makefile | 7 +-
13 arch/mips/ralink/Platform | 7 +
14 arch/mips/ralink/irq-gic.c | 271 ++++++++++++++++++++++++++++
15 arch/mips/ralink/malta-amon.c | 81 +++++++++
16 arch/mips/ralink/mt7621.c | 183 +++++++++++++++++++
17 9 files changed, 608 insertions(+), 1 deletion(-)
18 create mode 100644 arch/mips/include/asm/mach-ralink/mt7621.h
19 create mode 100644 arch/mips/ralink/irq-gic.c
20 create mode 100644 arch/mips/ralink/malta-amon.c
21 create mode 100644 arch/mips/ralink/mt7621.c
23 --- a/arch/mips/include/asm/gic.h
24 +++ b/arch/mips/include/asm/gic.h
26 #define GIC_TRIG_EDGE 1
27 #define GIC_TRIG_LEVEL 0
29 +#define GIC_NUM_INTRS 64
31 +#ifndef GIC_NUM_INTRS
32 #define GIC_NUM_INTRS (24 + NR_CPUS * 2)
35 #define MSK(n) ((1 << (n)) - 1)
36 #define REG32(addr) (*(volatile unsigned int *) (addr))
38 +++ b/arch/mips/include/asm/mach-ralink/mt7621.h
41 + * This program is free software; you can redistribute it and/or modify it
42 + * under the terms of the GNU General Public License version 2 as published
43 + * by the Free Software Foundation.
45 + * Parts of this file are based on Ralink's 2.6.21 BSP
47 + * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
48 + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
49 + * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
52 +#ifndef _MT7621_REGS_H_
53 +#define _MT7621_REGS_H_
55 +#define MT7621_SYSC_BASE 0x1E000000
57 +#define SYSC_REG_CHIP_NAME0 0x00
58 +#define SYSC_REG_CHIP_NAME1 0x04
59 +#define SYSC_REG_CHIP_REV 0x0c
60 +#define SYSC_REG_SYSTEM_CONFIG0 0x10
61 +#define SYSC_REG_SYSTEM_CONFIG1 0x14
63 +#define CHIP_REV_PKG_MASK 0x1
64 +#define CHIP_REV_PKG_SHIFT 16
65 +#define CHIP_REV_VER_MASK 0xf
66 +#define CHIP_REV_VER_SHIFT 8
67 +#define CHIP_REV_ECO_MASK 0xf
69 +#define MT7621_DRAM_BASE 0x0
70 +#define MT7621_DDR2_SIZE_MIN 32
71 +#define MT7621_DDR2_SIZE_MAX 256
73 +#define MT7621_CHIP_NAME0 0x3637544D
74 +#define MT7621_CHIP_NAME1 0x20203132
76 +#define MIPS_GIC_IRQ_BASE (MIPS_CPU_IRQ_BASE + 8)
79 --- a/arch/mips/kernel/vmlinux.lds.S
80 +++ b/arch/mips/kernel/vmlinux.lds.S
81 @@ -51,6 +51,7 @@ SECTIONS
83 _text = .; /* Text and read-only data */
85 + /*. = . + 0x8000; */
89 --- a/arch/mips/ralink/Kconfig
90 +++ b/arch/mips/ralink/Kconfig
91 @@ -7,6 +7,11 @@ config CLKEVT_RT3352
98 + depends on !SOC_MT7621
101 prompt "Ralink SoC selection"
103 @@ -35,6 +40,15 @@ choice
104 select USB_ARCH_HAS_EHCI
109 + select MIPS_CPU_SCACHE
110 + select SYS_SUPPORTS_MULTITHREADING
111 + select SYS_SUPPORTS_SMP
112 + select SYS_SUPPORTS_MIPS_CMP
119 @@ -62,6 +76,10 @@ choice
120 bool "MT7620A eval kit"
121 depends on SOC_MT7620
123 + config DTB_MT7621_EVAL
124 + bool "MT7621 eval kit"
125 + depends on SOC_MT7621
130 --- a/arch/mips/ralink/Makefile
131 +++ b/arch/mips/ralink/Makefile
133 # Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
134 # Copyright (C) 2013 John Crispin <blogic@openwrt.org>
136 -obj-y := prom.o of.o reset.o clk.o irq.o timer.o
137 +obj-y := prom.o of.o reset.o clk.o timer.o
139 obj-$(CONFIG_CLKEVT_RT3352) += cevt-rt3352.o
141 obj-$(CONFIG_RALINK_ILL_ACC) += ill_acc.o
143 +obj-$(CONFIG_IRQ_INTC) += irq.o
144 +obj-$(CONFIG_IRQ_GIC) += irq-gic.o
145 +obj-$(CONFIG_MIPS_MT_SMP) += malta-amon.o
147 obj-$(CONFIG_SOC_RT288X) += rt288x.o
148 obj-$(CONFIG_SOC_RT305X) += rt305x.o
149 obj-$(CONFIG_SOC_RT3883) += rt3883.o
150 obj-$(CONFIG_SOC_MT7620) += mt7620.o
151 +obj-$(CONFIG_SOC_MT7621) += mt7621.o
153 obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
155 --- a/arch/mips/ralink/Platform
156 +++ b/arch/mips/ralink/Platform
157 @@ -26,3 +26,10 @@ cflags-$(CONFIG_SOC_RT3883) += -I$(srctr
160 load-$(CONFIG_SOC_MT7620) += 0xffffffff80000000
161 +cflags-$(CONFIG_SOC_MT7620) += -I$(srctree)/arch/mips/include/asm/mach-ralink/mt7620
166 +load-$(CONFIG_SOC_MT7621) += 0xffffffff80001000
167 +cflags-$(CONFIG_SOC_MT7620) += -I$(srctree)/arch/mips/include/asm/mach-ralink/mt7621
169 +++ b/arch/mips/ralink/irq-gic.c
171 +#include <linux/init.h>
172 +#include <linux/sched.h>
173 +#include <linux/slab.h>
174 +#include <linux/interrupt.h>
175 +#include <linux/kernel_stat.h>
176 +#include <linux/hardirq.h>
177 +#include <linux/preempt.h>
178 +#include <linux/irqdomain.h>
179 +#include <linux/of_platform.h>
180 +#include <linux/of_address.h>
181 +#include <linux/of_irq.h>
183 +#include <asm/irq_cpu.h>
184 +#include <asm/mipsregs.h>
186 +#include <asm/irq.h>
187 +#include <asm/setup.h>
189 +#include <asm/gic.h>
190 +#include <asm/gcmpregs.h>
192 +#include <asm/mach-ralink/mt7621.h>
194 +unsigned long _gcmp_base;
195 +static int gic_resched_int_base = 56;
196 +static int gic_call_int_base = 60;
197 +static struct irq_chip *irq_gic;
198 +static struct gic_intr_map gic_intr_map[GIC_NUM_INTRS];
200 +#if defined(CONFIG_MIPS_MT_SMP)
201 +static int gic_resched_int_base;
202 +static int gic_call_int_base;
204 +#define GIC_RESCHED_INT(cpu) (gic_resched_int_base+(cpu))
205 +#define GIC_CALL_INT(cpu) (gic_call_int_base+(cpu))
207 +static irqreturn_t ipi_resched_interrupt(int irq, void *dev_id)
211 + return IRQ_HANDLED;
215 +ipi_call_interrupt(int irq, void *dev_id)
217 + smp_call_function_interrupt();
219 + return IRQ_HANDLED;
222 +static struct irqaction irq_resched = {
223 + .handler = ipi_resched_interrupt,
224 + .flags = IRQF_DISABLED|IRQF_PERCPU,
225 + .name = "ipi resched"
228 +static struct irqaction irq_call = {
229 + .handler = ipi_call_interrupt,
230 + .flags = IRQF_DISABLED|IRQF_PERCPU,
241 + for (i = 0; i < ARRAY_SIZE(gic_intr_map); i++) {
242 + gic_intr_map[i].cpunum = 0;
243 + gic_intr_map[i].pin = GIC_CPU_INT0;
244 + gic_intr_map[i].polarity = GIC_POL_POS;
245 + gic_intr_map[i].trigtype = GIC_TRIG_LEVEL;
246 + gic_intr_map[i].flags = GIC_FLAG_IPI;
249 +#if defined(CONFIG_MIPS_MT_SMP)
253 + gic_call_int_base = ARRAY_SIZE(gic_intr_map) - nr_cpu_ids;
254 + gic_resched_int_base = gic_call_int_base - nr_cpu_ids;
256 + i = gic_resched_int_base;
258 + for (cpu = 0; cpu < nr_cpu_ids; cpu++) {
259 + gic_intr_map[i + cpu].cpunum = cpu;
260 + gic_intr_map[i + cpu].pin = GIC_CPU_INT1;
261 + gic_intr_map[i + cpu].trigtype = GIC_TRIG_EDGE;
263 + gic_intr_map[i + cpu + nr_cpu_ids].cpunum = cpu;
264 + gic_intr_map[i + cpu + nr_cpu_ids].pin = GIC_CPU_INT2;
265 + gic_intr_map[i + cpu + nr_cpu_ids].trigtype = GIC_TRIG_EDGE;
272 +gic_irq_ack(struct irq_data *d)
274 + int irq = (d->irq - gic_irq_base);
276 + GIC_CLR_INTR_MASK(irq);
278 + if (gic_irq_flags[irq] & GIC_TRIG_EDGE)
279 + GICWRITE(GIC_REG(SHARED, GIC_SH_WEDGE), irq);
283 +gic_finish_irq(struct irq_data *d)
285 + GIC_SET_INTR_MASK(d->irq - gic_irq_base);
289 +gic_platform_init(int irqs, struct irq_chip *irq_controller)
291 + irq_gic = irq_controller;
295 +gic_irqdispatch(void)
297 + unsigned int irq = gic_get_int();
299 + if (likely(irq < GIC_NUM_INTRS))
300 + do_IRQ(MIPS_GIC_IRQ_BASE + irq);
302 + pr_err("Spurious GIC Interrupt!\n");
303 + spurious_interrupt();
309 +vi_timer_irqdispatch(void)
311 + do_IRQ(cp0_compare_irq);
314 +#if defined(CONFIG_MIPS_MT_SMP)
316 +plat_ipi_call_int_xlate(unsigned int cpu)
318 + return GIC_CALL_INT(cpu);
322 +plat_ipi_resched_int_xlate(unsigned int cpu)
324 + return GIC_RESCHED_INT(cpu);
329 +plat_irq_dispatch(void)
331 + unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
333 + if (unlikely(!pending)) {
334 + pr_err("Spurious CP0 Interrupt!\n");
335 + spurious_interrupt();
337 + if (pending & CAUSEF_IP7)
338 + do_IRQ(cp0_compare_irq);
340 + if (pending & (CAUSEF_IP4 | CAUSEF_IP3 | CAUSEF_IP2))
345 +unsigned int __cpuinit
346 +get_c0_compare_int(void)
348 + return CP0_LEGACY_COMPARE_IRQ;
352 +gic_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
354 + irq_set_chip_and_handler(irq, irq_gic,
355 +#if defined(CONFIG_MIPS_MT_SMP)
356 + (hw >= gic_resched_int_base) ?
357 + handle_percpu_irq :
364 +static const struct irq_domain_ops irq_domain_ops = {
365 + .xlate = irq_domain_xlate_onecell,
370 +of_gic_init(struct device_node *node,
371 + struct device_node *parent)
373 + struct irq_domain *domain;
374 + struct resource gcmp = { 0 }, gic = { 0 };
375 + unsigned int gic_rev;
378 + if (of_address_to_resource(node, 0, &gic))
379 + panic("Failed to get gic memory range");
380 + if (request_mem_region(gic.start, resource_size(&gic),
382 + panic("Failed to request gic memory");
383 + if (of_address_to_resource(node, 2, &gcmp))
384 + panic("Failed to get gic memory range");
385 + if (request_mem_region(gcmp.start, resource_size(&gcmp),
387 + panic("Failed to request gcmp memory");
389 + _gcmp_base = (unsigned long) ioremap_nocache(gcmp.start, resource_size(&gcmp));
391 + panic("Failed to remap gcmp memory\n");
393 + if ((GCMPGCB(GCMPB) & GCMP_GCB_GCMPB_GCMPBASE_MSK) != gcmp.start)
394 + panic("Failed to find gcmp core\n");
396 + /* tell the gcmp where to find the gic */
397 + GCMPGCB(GICBA) = gic.start | GCMP_GCB_GICBA_EN_MSK;
399 + if (cpu_has_vint) {
400 + set_vi_handler(2, gic_irqdispatch);
401 + set_vi_handler(3, gic_irqdispatch);
402 + set_vi_handler(4, gic_irqdispatch);
403 + set_vi_handler(7, vi_timer_irqdispatch);
408 + gic_init(gic.start, resource_size(&gic), gic_intr_map,
409 + ARRAY_SIZE(gic_intr_map), MIPS_GIC_IRQ_BASE);
411 + GICREAD(GIC_REG(SHARED, GIC_SH_REVISIONID), gic_rev);
412 + pr_info("gic: revision %d.%d\n", (gic_rev >> 8) & 0xff, gic_rev & 0xff);
414 + domain = irq_domain_add_legacy(node, GIC_NUM_INTRS, MIPS_GIC_IRQ_BASE,
415 + 0, &irq_domain_ops, NULL);
417 + panic("Failed to add irqdomain");
419 +#if defined(CONFIG_MIPS_MT_SMP)
420 + for (i = 0; i < nr_cpu_ids; i++) {
421 + setup_irq(MIPS_GIC_IRQ_BASE + GIC_RESCHED_INT(i), &irq_resched);
422 + setup_irq(MIPS_GIC_IRQ_BASE + GIC_CALL_INT(i), &irq_call);
426 + change_c0_status(ST0_IM, STATUSF_IP7 | STATUSF_IP4 | STATUSF_IP3 |
431 +static struct of_device_id __initdata of_irq_ids[] = {
432 + { .compatible = "mti,cpu-interrupt-controller", .data = mips_cpu_intc_init },
433 + { .compatible = "ralink,mt7621-gic", .data = of_gic_init },
440 + of_irq_init(of_irq_ids);
443 +++ b/arch/mips/ralink/malta-amon.c
446 + * Copyright (C) 2007 MIPS Technologies, Inc.
447 + * All rights reserved.
449 + * This program is free software; you can distribute it and/or modify it
450 + * under the terms of the GNU General Public License (Version 2) as
451 + * published by the Free Software Foundation.
453 + * This program is distributed in the hope it will be useful, but WITHOUT
454 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
455 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
456 + * for more details.
458 + * You should have received a copy of the GNU General Public License along
459 + * with this program; if not, write to the Free Software Foundation, Inc.,
460 + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
462 + * Arbitrary Monitor interface
465 +#include <linux/kernel.h>
466 +#include <linux/init.h>
467 +#include <linux/smp.h>
469 +#include <asm/addrspace.h>
470 +#include <asm/mips-boards/launch.h>
471 +#include <asm/mipsmtregs.h>
473 +int amon_cpu_avail(int cpu)
475 + struct cpulaunch *launch = (struct cpulaunch *)CKSEG0ADDR(CPULAUNCH);
477 + if (cpu < 0 || cpu >= NCPULAUNCH) {
478 + pr_debug("avail: cpu%d is out of range\n", cpu);
483 + if (!(launch->flags & LAUNCH_FREADY)) {
484 + pr_debug("avail: cpu%d is not ready\n", cpu);
487 + if (launch->flags & (LAUNCH_FGO|LAUNCH_FGONE)) {
488 + pr_debug("avail: too late.. cpu%d is already gone\n", cpu);
495 +void amon_cpu_start(int cpu,
496 + unsigned long pc, unsigned long sp,
497 + unsigned long gp, unsigned long a0)
499 + volatile struct cpulaunch *launch =
500 + (struct cpulaunch *)CKSEG0ADDR(CPULAUNCH);
502 + if (!amon_cpu_avail(cpu))
504 + if (cpu == smp_processor_id()) {
505 + pr_debug("launch: I am cpu%d!\n", cpu);
510 + pr_debug("launch: starting cpu%d\n", cpu);
517 + smp_wmb(); /* Target must see parameters before go */
518 + launch->flags |= LAUNCH_FGO;
519 + smp_wmb(); /* Target must see go before we poll */
521 + while ((launch->flags & LAUNCH_FGONE) == 0)
523 + smp_rmb(); /* Target will be updating flags soon */
524 + pr_debug("launch: cpu%d gone!\n", cpu);
527 +++ b/arch/mips/ralink/mt7621.c
530 + * This program is free software; you can redistribute it and/or modify it
531 + * under the terms of the GNU General Public License version 2 as published
532 + * by the Free Software Foundation.
534 + * Parts of this file are based on Ralink's 2.6.21 BSP
536 + * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
537 + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
538 + * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
541 +#include <linux/kernel.h>
542 +#include <linux/init.h>
543 +#include <linux/module.h>
544 +#include <asm/gcmpregs.h>
546 +#include <asm/mipsregs.h>
547 +#include <asm/smp-ops.h>
548 +#include <asm/mach-ralink/ralink_regs.h>
549 +#include <asm/mach-ralink/mt7621.h>
555 +#define SYSC_REG_SYSCFG 0x10
556 +#define SYSC_REG_CPLL_CLKCFG0 0x2c
557 +#define SYSC_REG_CUR_CLK_STS 0x44
558 +#define CPU_CLK_SEL (BIT(30) | BIT(31))
560 +#define MT7621_GPIO_MODE_UART1 1
561 +#define MT7621_GPIO_MODE_I2C 2
562 +#define MT7621_GPIO_MODE_UART2 3
563 +#define MT7621_GPIO_MODE_UART3 5
564 +#define MT7621_GPIO_MODE_JTAG 7
565 +#define MT7621_GPIO_MODE_WDT_MASK 0x3
566 +#define MT7621_GPIO_MODE_WDT_SHIFT 8
567 +#define MT7621_GPIO_MODE_WDT_GPIO 1
568 +#define MT7621_GPIO_MODE_PCIE_RST 0
569 +#define MT7621_GPIO_MODE_PCIE_REF 2
570 +#define MT7621_GPIO_MODE_PCIE_MASK 0x3
571 +#define MT7621_GPIO_MODE_PCIE_SHIFT 10
572 +#define MT7621_GPIO_MODE_PCIE_GPIO 1
573 +#define MT7621_GPIO_MODE_MDIO 12
574 +#define MT7621_GPIO_MODE_RGMII1 14
575 +#define MT7621_GPIO_MODE_RGMII2 15
576 +#define MT7621_GPIO_MODE_SPI_MASK 0x3
577 +#define MT7621_GPIO_MODE_SPI_SHIFT 16
578 +#define MT7621_GPIO_MODE_SPI_GPIO 1
579 +#define MT7621_GPIO_MODE_SDHCI_MASK 0x3
580 +#define MT7621_GPIO_MODE_SDHCI_SHIFT 18
581 +#define MT7621_GPIO_MODE_SDHCI_GPIO 1
583 +static struct rt2880_pmx_func uart1_grp[] = { FUNC("uart1", 0, 1, 2) };
584 +static struct rt2880_pmx_func i2c_grp[] = { FUNC("i2c", 0, 3, 2) };
585 +static struct rt2880_pmx_func uart3_grp[] = { FUNC("uart3", 0, 5, 4) };
586 +static struct rt2880_pmx_func uart2_grp[] = { FUNC("uart2", 0, 9, 4) };
587 +static struct rt2880_pmx_func jtag_grp[] = { FUNC("jtag", 0, 13, 5) };
588 +static struct rt2880_pmx_func wdt_grp[] = {
589 + FUNC("wdt rst", 0, 18, 1),
590 + FUNC("wdt refclk", 2, 18, 1),
592 +static struct rt2880_pmx_func pcie_rst_grp[] = {
593 + FUNC("pcie rst", MT7621_GPIO_MODE_PCIE_RST, 19, 1),
594 + FUNC("pcie refclk", MT7621_GPIO_MODE_PCIE_REF, 19, 1)
596 +static struct rt2880_pmx_func mdio_grp[] = { FUNC("mdio", 0, 20, 2) };
597 +static struct rt2880_pmx_func rgmii2_grp[] = { FUNC("rgmii2", 0, 22, 12) };
598 +static struct rt2880_pmx_func spi_grp[] = {
599 + FUNC("spi", 0, 34, 7),
600 + FUNC("nand", 2, 34, 8),
602 +static struct rt2880_pmx_func sdhci_grp[] = {
603 + FUNC("sdhci", 0, 41, 8),
604 + FUNC("nand", 2, 41, 8),
606 +static struct rt2880_pmx_func rgmii1_grp[] = { FUNC("rgmii1", 0, 49, 12) };
608 +static struct rt2880_pmx_group mt7621_pinmux_data[] = {
609 + GRP("uart1", uart1_grp, 1, MT7621_GPIO_MODE_UART1),
610 + GRP("i2c", i2c_grp, 1, MT7621_GPIO_MODE_I2C),
611 + GRP("uart3", uart2_grp, 1, MT7621_GPIO_MODE_UART2),
612 + GRP("uart2", uart3_grp, 1, MT7621_GPIO_MODE_UART3),
613 + GRP("jtag", jtag_grp, 1, MT7621_GPIO_MODE_JTAG),
614 + GRP_G("wdt", wdt_grp, MT7621_GPIO_MODE_WDT_MASK,
615 + MT7621_GPIO_MODE_WDT_GPIO, MT7621_GPIO_MODE_WDT_SHIFT),
616 + GRP_G("pcie", pcie_rst_grp, MT7621_GPIO_MODE_PCIE_MASK,
617 + MT7621_GPIO_MODE_PCIE_GPIO, MT7621_GPIO_MODE_PCIE_SHIFT),
618 + GRP("mdio", mdio_grp, 1, MT7621_GPIO_MODE_MDIO),
619 + GRP("rgmii2", rgmii2_grp, 1, MT7621_GPIO_MODE_RGMII2),
620 + GRP_G("spi", spi_grp, MT7621_GPIO_MODE_SPI_MASK,
621 + MT7621_GPIO_MODE_SPI_GPIO, MT7621_GPIO_MODE_SPI_SHIFT),
622 + GRP_G("sdhci", sdhci_grp, MT7621_GPIO_MODE_SDHCI_MASK,
623 + MT7621_GPIO_MODE_SDHCI_GPIO, MT7621_GPIO_MODE_SDHCI_SHIFT),
624 + GRP("rgmii1", rgmii1_grp, 1, MT7621_GPIO_MODE_RGMII1),
628 +void __init ralink_clk_init(void)
633 + u32 clk_sts, syscfg;
634 + u8 clk_sel = 0, xtal_mode;
637 + if ((rt_sysc_r32(SYSC_REG_CPLL_CLKCFG0) & CPU_CLK_SEL) != 0)
642 + clk_sts = rt_sysc_r32(SYSC_REG_CUR_CLK_STS);
643 + cpu_fdiv = ((clk_sts >> 8) & 0x1F);
644 + cpu_ffrac = (clk_sts & 0x1F);
645 + cpu_clk = (500 * cpu_ffrac / cpu_fdiv) * 1000 * 1000;
649 + fbdiv = ((rt_sysc_r32(0x648) >> 4) & 0x7F) + 1;
650 + syscfg = rt_sysc_r32(SYSC_REG_SYSCFG);
651 + xtal_mode = (syscfg >> 6) & 0x7;
652 + if(xtal_mode >= 6) { //25Mhz Xtal
653 + cpu_clk = 25 * fbdiv * 1000 * 1000;
654 + } else if(xtal_mode >=3) { //40Mhz Xtal
655 + cpu_clk = 40 * fbdiv * 1000 * 1000;
656 + } else { // 20Mhz Xtal
657 + cpu_clk = 20 * fbdiv * 1000 * 1000;
661 + cpu_clk = 880000000;
662 + ralink_clk_add("cpu", cpu_clk);
663 + ralink_clk_add("1e000b00.spi", 50000000);
664 + ralink_clk_add("1e000c00.uartlite", 50000000);
665 + ralink_clk_add("1e000d00.uart", 50000000);
668 +void __init ralink_of_remap(void)
670 + rt_sysc_membase = plat_of_remap_node("mtk,mt7621-sysc");
671 + rt_memc_membase = plat_of_remap_node("mtk,mt7621-memc");
673 + if (!rt_sysc_membase || !rt_memc_membase)
674 + panic("Failed to remap core resources");
677 +void prom_soc_init(struct ralink_soc_info *soc_info)
679 + void __iomem *sysc = (void __iomem *) KSEG1ADDR(MT7621_SYSC_BASE);
680 + unsigned char *name = NULL;
685 + n0 = __raw_readl(sysc + SYSC_REG_CHIP_NAME0);
686 + n1 = __raw_readl(sysc + SYSC_REG_CHIP_NAME1);
688 + if (n0 == MT7621_CHIP_NAME0 && n1 == MT7621_CHIP_NAME1) {
690 + soc_info->compatible = "mtk,mt7621-soc";
692 + panic("mt7621: unknown SoC, n0:%08x n1:%08x\n", n0, n1);
695 + rev = __raw_readl(sysc + SYSC_REG_CHIP_REV);
697 + snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN,
698 + "Mediatek %s ver:%u eco:%u",
700 + (rev >> CHIP_REV_VER_SHIFT) & CHIP_REV_VER_MASK,
701 + (rev & CHIP_REV_ECO_MASK));
703 + soc_info->mem_size_min = MT7621_DDR2_SIZE_MIN;
704 + soc_info->mem_size_max = MT7621_DDR2_SIZE_MAX;
705 + soc_info->mem_base = MT7621_DRAM_BASE;
707 + rt2880_pinmux_data = mt7621_pinmux_data;
709 + if (register_cmp_smp_ops())
710 + panic("failed to register_vsmp_smp_ops()");
713 +++ b/arch/mips/include/asm/mach-ralink/irq.h
715 +#ifndef __ASM_MACH_RALINK_IRQ_H
716 +#define __ASM_MACH_RALINK_IRQ_H
718 +#define GIC_NUM_INTRS 64
721 +#include_next <irq.h>