target/linux/ramips/patches-3.14/0012-MIPS-ralink-add-MT7621-support.patch

   1 From c8c69923236f2f3f184ddcc7eb41c113b5cc3223 Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Sun, 27 Jul 2014 10:57:40 +0100
   4 Subject: [PATCH 12/57] MIPS: ralink: add MT7621 support
   5
   6 Signed-off-by: John Crispin <blogic@openwrt.org>
   7 ---
   8  arch/mips/include/asm/gic.h                |    4 +
   9  arch/mips/include/asm/mach-ralink/irq.h    |    9 +
  10  arch/mips/include/asm/mach-ralink/mt7621.h |   39 ++++
  11  arch/mips/kernel/vmlinux.lds.S             |    1 +
  12  arch/mips/ralink/Kconfig                   |   18 ++
  13  arch/mips/ralink/Makefile                  |    7 +-
  14  arch/mips/ralink/Platform                  |    5 +
  15  arch/mips/ralink/irq-gic.c                 |  271 ++++++++++++++++++++++++++++
  16  arch/mips/ralink/malta-amon.c              |   81 +++++++++
  17  arch/mips/ralink/mt7621.c                  |  183 +++++++++++++++++++
  18  10 files changed, 617 insertions(+), 1 deletion(-)
  19  create mode 100644 arch/mips/include/asm/mach-ralink/irq.h
  20  create mode 100644 arch/mips/include/asm/mach-ralink/mt7621.h
  21  create mode 100644 arch/mips/ralink/irq-gic.c
  22  create mode 100644 arch/mips/ralink/malta-amon.c
  23  create mode 100644 arch/mips/ralink/mt7621.c
  24
  25 diff --git a/arch/mips/include/asm/gic.h b/arch/mips/include/asm/gic.h
  26 index b2e3e93..29fba50 100644
  27 --- a/arch/mips/include/asm/gic.h
  28 +++ b/arch/mips/include/asm/gic.h
  29 @@ -19,7 +19,11 @@
  30  #define GIC_TRIG_EDGE                  1
  31  #define GIC_TRIG_LEVEL                 0
  32
  33 +#define GIC_NUM_INTRS                  64
  34 +
  35 +#ifndef GIC_NUM_INTRS
  36  #define GIC_NUM_INTRS                  (24 + NR_CPUS * 2)
  37 +#endif
  38
  39  #define MSK(n) ((1 << (n)) - 1)
  40  #define REG32(addr)            (*(volatile unsigned int *) (addr))
  41 diff --git a/arch/mips/include/asm/mach-ralink/irq.h b/arch/mips/include/asm/mach-ralink/irq.h
  42 new file mode 100644
  43 index 0000000..4321865
  44 --- /dev/null
  45 +++ b/arch/mips/include/asm/mach-ralink/irq.h
  46 @@ -0,0 +1,9 @@
  47 +#ifndef __ASM_MACH_RALINK_IRQ_H
  48 +#define __ASM_MACH_RALINK_IRQ_H
  49 +
  50 +#define GIC_NUM_INTRS  64
  51 +#define NR_IRQS 256
  52 +
  53 +#include_next <irq.h>
  54 +
  55 +#endif
  56 diff --git a/arch/mips/include/asm/mach-ralink/mt7621.h b/arch/mips/include/asm/mach-ralink/mt7621.h
  57 new file mode 100644
  58 index 0000000..21c8dc2
  59 --- /dev/null
  60 +++ b/arch/mips/include/asm/mach-ralink/mt7621.h
  61 @@ -0,0 +1,39 @@
  62 +/*
  63 + * This program is free software; you can redistribute it and/or modify it
  64 + * under the terms of the GNU General Public License version 2 as published
  65 + * by the Free Software Foundation.
  66 + *
  67 + * Parts of this file are based on Ralink's 2.6.21 BSP
  68 + *
  69 + * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
  70 + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
  71 + * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
  72 + */
  73 +
  74 +#ifndef _MT7621_REGS_H_
  75 +#define _MT7621_REGS_H_
  76 +
  77 +#define MT7621_SYSC_BASE               0x1E000000
  78 +
  79 +#define SYSC_REG_CHIP_NAME0            0x00
  80 +#define SYSC_REG_CHIP_NAME1            0x04
  81 +#define SYSC_REG_CHIP_REV              0x0c
  82 +#define SYSC_REG_SYSTEM_CONFIG0                0x10
  83 +#define SYSC_REG_SYSTEM_CONFIG1                0x14
  84 +
  85 +#define CHIP_REV_PKG_MASK              0x1
  86 +#define CHIP_REV_PKG_SHIFT             16
  87 +#define CHIP_REV_VER_MASK              0xf
  88 +#define CHIP_REV_VER_SHIFT             8
  89 +#define CHIP_REV_ECO_MASK              0xf
  90 +
  91 +#define MT7621_DRAM_BASE                0x0
  92 +#define MT7621_DDR2_SIZE_MIN           32
  93 +#define MT7621_DDR2_SIZE_MAX           256
  94 +
  95 +#define MT7621_CHIP_NAME0              0x3637544D
  96 +#define MT7621_CHIP_NAME1              0x20203132
  97 +
  98 +#define MIPS_GIC_IRQ_BASE           (MIPS_CPU_IRQ_BASE + 8)
  99 +
 100 +#endif
 101 diff --git a/arch/mips/kernel/vmlinux.lds.S b/arch/mips/kernel/vmlinux.lds.S
 102 index 3b46f7c..fa925b7 100644
 103 --- a/arch/mips/kernel/vmlinux.lds.S
 104 +++ b/arch/mips/kernel/vmlinux.lds.S
 105 @@ -51,6 +51,7 @@ SECTIONS
 106         /* read-only */
 107         _text = .;      /* Text and read-only data */
 108         .text : {
 109 +               /*. = . + 0x8000; */
 110                 TEXT_TEXT
 111                 SCHED_TEXT
 112                 LOCK_TEXT
 113 diff --git a/arch/mips/ralink/Kconfig b/arch/mips/ralink/Kconfig
 114 index 1bfd1c1..6a04360 100644
 115 --- a/arch/mips/ralink/Kconfig
 116 +++ b/arch/mips/ralink/Kconfig
 117 @@ -7,6 +7,11 @@ config CLKEVT_RT3352
 118         select CLKSRC_OF
 119         select CLKSRC_MMIO
 120
 121 +config IRQ_INTC
 122 +       bool
 123 +       default y
 124 +       depends on !SOC_MT7621
 125 +
 126  choice
 127         prompt "Ralink SoC selection"
 128         default SOC_RT305X
 129 @@ -34,6 +39,15 @@ choice
 130                 select USB_ARCH_HAS_OHCI
 131                 select USB_ARCH_HAS_EHCI
 132
 133 +       config SOC_MT7621
 134 +               bool "MT7621"
 135 +               select MIPS_CPU_SCACHE
 136 +               select SYS_SUPPORTS_MULTITHREADING
 137 +               select SYS_SUPPORTS_SMP
 138 +               select SYS_SUPPORTS_MIPS_CMP
 139 +               select IRQ_GIC
 140 +               select HW_HAS_PCI
 141 +
 142  endchoice
 143
 144  choice
 145 @@ -61,6 +75,10 @@ choice
 146                 bool "MT7620A eval kit"
 147                 depends on SOC_MT7620
 148
 149 +       config DTB_MT7621_EVAL
 150 +               bool "MT7621 eval kit"
 151 +               depends on SOC_MT7621
 152 +
 153  endchoice
 154
 155  endif
 156 diff --git a/arch/mips/ralink/Makefile b/arch/mips/ralink/Makefile
 157 index fc57c16..ad18cdf 100644
 158 --- a/arch/mips/ralink/Makefile
 159 +++ b/arch/mips/ralink/Makefile
 160 @@ -6,16 +6,21 @@
 161  # Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
 162  # Copyright (C) 2013 John Crispin <blogic@openwrt.org>
 163
 164 -obj-y := prom.o of.o reset.o clk.o irq.o timer.o
 165 +obj-y := prom.o of.o reset.o clk.o timer.o
 166
 167  obj-$(CONFIG_CLKEVT_RT3352) += cevt-rt3352.o
 168
 169  obj-$(CONFIG_RALINK_ILL_ACC) += ill_acc.o
 170
 171 +obj-$(CONFIG_IRQ_INTC) += irq.o
 172 +obj-$(CONFIG_IRQ_GIC) += irq-gic.o
 173 +obj-$(CONFIG_MIPS_MT_SMP) += malta-amon.o
 174 +
 175  obj-$(CONFIG_SOC_RT288X) += rt288x.o
 176  obj-$(CONFIG_SOC_RT305X) += rt305x.o
 177  obj-$(CONFIG_SOC_RT3883) += rt3883.o
 178  obj-$(CONFIG_SOC_MT7620) += mt7620.o
 179 +obj-$(CONFIG_SOC_MT7621) += mt7621.o
 180
 181  obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
 182
 183 diff --git a/arch/mips/ralink/Platform b/arch/mips/ralink/Platform
 184 index 6d9c8c4..6095fcc 100644
 185 --- a/arch/mips/ralink/Platform
 186 +++ b/arch/mips/ralink/Platform
 187 @@ -27,3 +27,8 @@ cflags-$(CONFIG_SOC_RT3883)   += -I$(srctree)/arch/mips/include/asm/mach-ralink/rt
 188  #
 189  load-$(CONFIG_SOC_MT7620)      += 0xffffffff80000000
 190  cflags-$(CONFIG_SOC_MT7620)    += -I$(srctree)/arch/mips/include/asm/mach-ralink/mt7620
 191 +
 192 +# Ralink MT7621
 193 +#
 194 +load-$(CONFIG_SOC_MT7621)      += 0xffffffff80001000
 195 +cflags-$(CONFIG_SOC_MT7621)    += -I$(srctree)/arch/mips/include/asm/mach-ralink/mt7621
 196 diff --git a/arch/mips/ralink/irq-gic.c b/arch/mips/ralink/irq-gic.c
 197 new file mode 100644
 198 index 0000000..0122d42
 199 --- /dev/null
 200 +++ b/arch/mips/ralink/irq-gic.c
 201 @@ -0,0 +1,271 @@
 202 +#include <linux/init.h>
 203 +#include <linux/sched.h>
 204 +#include <linux/slab.h>
 205 +#include <linux/interrupt.h>
 206 +#include <linux/kernel_stat.h>
 207 +#include <linux/hardirq.h>
 208 +#include <linux/preempt.h>
 209 +#include <linux/irqdomain.h>
 210 +#include <linux/of_platform.h>
 211 +#include <linux/of_address.h>
 212 +#include <linux/of_irq.h>
 213 +
 214 +#include <asm/irq_cpu.h>
 215 +#include <asm/mipsregs.h>
 216 +
 217 +#include <asm/irq.h>
 218 +#include <asm/setup.h>
 219 +
 220 +#include <asm/gic.h>
 221 +#include <asm/gcmpregs.h>
 222 +
 223 +#include <asm/mach-ralink/mt7621.h>
 224 +
 225 +unsigned long _gcmp_base;
 226 +static int gic_resched_int_base = 56;
 227 +static int gic_call_int_base = 60;
 228 +static struct irq_chip *irq_gic;
 229 +static struct gic_intr_map gic_intr_map[GIC_NUM_INTRS];
 230 +
 231 +#if defined(CONFIG_MIPS_MT_SMP)
 232 +static int gic_resched_int_base;
 233 +static int gic_call_int_base;
 234 +
 235 +#define GIC_RESCHED_INT(cpu) (gic_resched_int_base+(cpu))
 236 +#define GIC_CALL_INT(cpu) (gic_call_int_base+(cpu))
 237 +
 238 +static irqreturn_t ipi_resched_interrupt(int irq, void *dev_id)
 239 +{
 240 +       scheduler_ipi();
 241 +
 242 +       return IRQ_HANDLED;
 243 +}
 244 +
 245 +static irqreturn_t
 246 +ipi_call_interrupt(int irq, void *dev_id)
 247 +{
 248 +       smp_call_function_interrupt();
 249 +
 250 +       return IRQ_HANDLED;
 251 +}
 252 +
 253 +static struct irqaction irq_resched = {
 254 +        .handler        = ipi_resched_interrupt,
 255 +        .flags          = IRQF_DISABLED|IRQF_PERCPU,
 256 +        .name           = "ipi resched"
 257 +};
 258 +
 259 +static struct irqaction irq_call = {
 260 +        .handler        = ipi_call_interrupt,
 261 +        .flags          = IRQF_DISABLED|IRQF_PERCPU,
 262 +        .name           = "ipi call"
 263 +};
 264 +
 265 +#endif
 266 +
 267 +static void __init
 268 +gic_fill_map(void)
 269 +{
 270 +       int i;
 271 +
 272 +       for (i = 0; i < ARRAY_SIZE(gic_intr_map); i++) {
 273 +               gic_intr_map[i].cpunum = 0;
 274 +               gic_intr_map[i].pin = GIC_CPU_INT0;
 275 +               gic_intr_map[i].polarity = GIC_POL_POS;
 276 +               gic_intr_map[i].trigtype = GIC_TRIG_LEVEL;
 277 +               gic_intr_map[i].flags = GIC_FLAG_IPI;
 278 +       }
 279 +
 280 +#if defined(CONFIG_MIPS_MT_SMP)
 281 +       {
 282 +               int cpu;
 283 +
 284 +               gic_call_int_base = ARRAY_SIZE(gic_intr_map) - nr_cpu_ids;
 285 +               gic_resched_int_base = gic_call_int_base - nr_cpu_ids;
 286 +
 287 +               i = gic_resched_int_base;
 288 +
 289 +               for (cpu = 0; cpu < nr_cpu_ids; cpu++) {
 290 +                       gic_intr_map[i + cpu].cpunum = cpu;
 291 +                       gic_intr_map[i + cpu].pin = GIC_CPU_INT1;
 292 +                       gic_intr_map[i + cpu].trigtype = GIC_TRIG_EDGE;
 293 +
 294 +                       gic_intr_map[i + cpu + nr_cpu_ids].cpunum = cpu;
 295 +                       gic_intr_map[i + cpu + nr_cpu_ids].pin = GIC_CPU_INT2;
 296 +                       gic_intr_map[i + cpu + nr_cpu_ids].trigtype = GIC_TRIG_EDGE;
 297 +               }
 298 +       }
 299 +#endif
 300 +}
 301 +
 302 +void
 303 +gic_irq_ack(struct irq_data *d)
 304 +{
 305 +       int irq = (d->irq - gic_irq_base);
 306 +
 307 +       GIC_CLR_INTR_MASK(irq);
 308 +
 309 +       if (gic_irq_flags[irq] & GIC_TRIG_EDGE)
 310 +               GICWRITE(GIC_REG(SHARED, GIC_SH_WEDGE), irq);
 311 +}
 312 +
 313 +void
 314 +gic_finish_irq(struct irq_data *d)
 315 +{
 316 +       GIC_SET_INTR_MASK(d->irq - gic_irq_base);
 317 +}
 318 +
 319 +void __init
 320 +gic_platform_init(int irqs, struct irq_chip *irq_controller)
 321 +{
 322 +       irq_gic = irq_controller;
 323 +}
 324 +
 325 +static void
 326 +gic_irqdispatch(void)
 327 +{
 328 +       unsigned int irq = gic_get_int();
 329 +
 330 +       if (likely(irq < GIC_NUM_INTRS))
 331 +               do_IRQ(MIPS_GIC_IRQ_BASE + irq);
 332 +       else {
 333 +               pr_err("Spurious GIC Interrupt!\n");
 334 +               spurious_interrupt();
 335 +       }
 336 +
 337 +}
 338 +
 339 +static void
 340 +vi_timer_irqdispatch(void)
 341 +{
 342 +       do_IRQ(cp0_compare_irq);
 343 +}
 344 +
 345 +#if defined(CONFIG_MIPS_MT_SMP)
 346 +unsigned int
 347 +plat_ipi_call_int_xlate(unsigned int cpu)
 348 +{
 349 +       return GIC_CALL_INT(cpu);
 350 +}
 351 +
 352 +unsigned int
 353 +plat_ipi_resched_int_xlate(unsigned int cpu)
 354 +{
 355 +       return GIC_RESCHED_INT(cpu);
 356 +}
 357 +#endif
 358 +
 359 +asmlinkage void
 360 +plat_irq_dispatch(void)
 361 +{
 362 +       unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
 363 +
 364 +       if (unlikely(!pending)) {
 365 +               pr_err("Spurious CP0 Interrupt!\n");
 366 +               spurious_interrupt();
 367 +       } else {
 368 +               if (pending & CAUSEF_IP7)
 369 +                       do_IRQ(cp0_compare_irq);
 370 +
 371 +               if (pending & (CAUSEF_IP4 | CAUSEF_IP3 | CAUSEF_IP2))
 372 +                       gic_irqdispatch();
 373 +       }
 374 +}
 375 +
 376 +unsigned int __cpuinit
 377 +get_c0_compare_int(void)
 378 +{
 379 +       return CP0_LEGACY_COMPARE_IRQ;
 380 +}
 381 +
 382 +static int
 383 +gic_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
 384 +{
 385 +       irq_set_chip_and_handler(irq, irq_gic,
 386 +#if defined(CONFIG_MIPS_MT_SMP)
 387 +               (hw >= gic_resched_int_base) ?
 388 +                       handle_percpu_irq :
 389 +#endif
 390 +                       handle_level_irq);
 391 +
 392 +       return 0;
 393 +}
 394 +
 395 +static const struct irq_domain_ops irq_domain_ops = {
 396 +       .xlate = irq_domain_xlate_onecell,
 397 +       .map = gic_map,
 398 +};
 399 +
 400 +static int __init
 401 +of_gic_init(struct device_node *node,
 402 +                               struct device_node *parent)
 403 +{
 404 +       struct irq_domain *domain;
 405 +       struct resource gcmp = { 0 }, gic = { 0 };
 406 +       unsigned int gic_rev;
 407 +       int i;
 408 +
 409 +       if (of_address_to_resource(node, 0, &gic))
 410 +               panic("Failed to get gic memory range");
 411 +       if (request_mem_region(gic.start, resource_size(&gic),
 412 +                               gic.name) < 0)
 413 +               panic("Failed to request gic memory");
 414 +       if (of_address_to_resource(node, 2, &gcmp))
 415 +               panic("Failed to get gic memory range");
 416 +       if (request_mem_region(gcmp.start, resource_size(&gcmp),
 417 +                               gcmp.name) < 0)
 418 +               panic("Failed to request gcmp memory");
 419 +
 420 +       _gcmp_base = (unsigned long) ioremap_nocache(gcmp.start, resource_size(&gcmp));
 421 +       if (!_gcmp_base)
 422 +               panic("Failed to remap gcmp memory\n");
 423 +
 424 +       if ((GCMPGCB(GCMPB) & GCMP_GCB_GCMPB_GCMPBASE_MSK) != gcmp.start)
 425 +               panic("Failed to find gcmp core\n");
 426 +
 427 +       /* tell the gcmp where to find the gic */
 428 +       GCMPGCB(GICBA) = gic.start | GCMP_GCB_GICBA_EN_MSK;
 429 +       gic_present = 1;
 430 +       if (cpu_has_vint) {
 431 +               set_vi_handler(2, gic_irqdispatch);
 432 +               set_vi_handler(3, gic_irqdispatch);
 433 +               set_vi_handler(4, gic_irqdispatch);
 434 +               set_vi_handler(7, vi_timer_irqdispatch);
 435 +       }
 436 +
 437 +       gic_fill_map();
 438 +
 439 +       gic_init(gic.start, resource_size(&gic), gic_intr_map,
 440 +               ARRAY_SIZE(gic_intr_map), MIPS_GIC_IRQ_BASE);
 441 +
 442 +       GICREAD(GIC_REG(SHARED, GIC_SH_REVISIONID), gic_rev);
 443 +       pr_info("gic: revision %d.%d\n", (gic_rev >> 8) & 0xff, gic_rev & 0xff);
 444 +
 445 +       domain = irq_domain_add_legacy(node, GIC_NUM_INTRS, MIPS_GIC_IRQ_BASE,
 446 +                       0, &irq_domain_ops, NULL);
 447 +       if (!domain)
 448 +               panic("Failed to add irqdomain");
 449 +
 450 +#if defined(CONFIG_MIPS_MT_SMP)
 451 +       for (i = 0; i < nr_cpu_ids; i++) {
 452 +               setup_irq(MIPS_GIC_IRQ_BASE + GIC_RESCHED_INT(i), &irq_resched);
 453 +               setup_irq(MIPS_GIC_IRQ_BASE + GIC_CALL_INT(i), &irq_call);
 454 +       }
 455 +#endif
 456 +
 457 +       change_c0_status(ST0_IM, STATUSF_IP7 | STATUSF_IP4 | STATUSF_IP3 |
 458 +                               STATUSF_IP2);
 459 +       return 0;
 460 +}
 461 +
 462 +static struct of_device_id __initdata of_irq_ids[] = {
 463 +       { .compatible = "mti,cpu-interrupt-controller", .data = mips_cpu_intc_init },
 464 +       { .compatible = "ralink,mt7621-gic", .data = of_gic_init },
 465 +       {},
 466 +};
 467 +
 468 +void __init
 469 +arch_init_irq(void)
 470 +{
 471 +       of_irq_init(of_irq_ids);
 472 +}
 473 diff --git a/arch/mips/ralink/malta-amon.c b/arch/mips/ralink/malta-amon.c
 474 new file mode 100644
 475 index 0000000..1e47844
 476 --- /dev/null
 477 +++ b/arch/mips/ralink/malta-amon.c
 478 @@ -0,0 +1,81 @@
 479 +/*
 480 + * Copyright (C) 2007  MIPS Technologies, Inc.
 481 + *     All rights reserved.
 482 +
 483 + *  This program is free software; you can distribute it and/or modify it
 484 + *  under the terms of the GNU General Public License (Version 2) as
 485 + *  published by the Free Software Foundation.
 486 + *
 487 + *  This program is distributed in the hope it will be useful, but WITHOUT
 488 + *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 489 + *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
 490 + *  for more details.
 491 + *
 492 + *  You should have received a copy of the GNU General Public License along
 493 + *  with this program; if not, write to the Free Software Foundation, Inc.,
 494 + *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
 495 + *
 496 + * Arbitrary Monitor interface
 497 + */
 498 +
 499 +#include <linux/kernel.h>
 500 +#include <linux/init.h>
 501 +#include <linux/smp.h>
 502 +
 503 +#include <asm/addrspace.h>
 504 +#include <asm/mips-boards/launch.h>
 505 +#include <asm/mipsmtregs.h>
 506 +
 507 +int amon_cpu_avail(int cpu)
 508 +{
 509 +       struct cpulaunch *launch = (struct cpulaunch *)CKSEG0ADDR(CPULAUNCH);
 510 +
 511 +       if (cpu < 0 || cpu >= NCPULAUNCH) {
 512 +               pr_debug("avail: cpu%d is out of range\n", cpu);
 513 +               return 0;
 514 +       }
 515 +
 516 +       launch += cpu;
 517 +       if (!(launch->flags & LAUNCH_FREADY)) {
 518 +               pr_debug("avail: cpu%d is not ready\n", cpu);
 519 +               return 0;
 520 +       }
 521 +       if (launch->flags & (LAUNCH_FGO|LAUNCH_FGONE)) {
 522 +               pr_debug("avail: too late.. cpu%d is already gone\n", cpu);
 523 +               return 0;
 524 +       }
 525 +
 526 +       return 1;
 527 +}
 528 +
 529 +void amon_cpu_start(int cpu,
 530 +                   unsigned long pc, unsigned long sp,
 531 +                   unsigned long gp, unsigned long a0)
 532 +{
 533 +       volatile struct cpulaunch *launch =
 534 +               (struct cpulaunch  *)CKSEG0ADDR(CPULAUNCH);
 535 +
 536 +       if (!amon_cpu_avail(cpu))
 537 +               return;
 538 +       if (cpu == smp_processor_id()) {
 539 +               pr_debug("launch: I am cpu%d!\n", cpu);
 540 +               return;
 541 +       }
 542 +       launch += cpu;
 543 +
 544 +       pr_debug("launch: starting cpu%d\n", cpu);
 545 +
 546 +       launch->pc = pc;
 547 +       launch->gp = gp;
 548 +       launch->sp = sp;
 549 +       launch->a0 = a0;
 550 +
 551 +       smp_wmb();              /* Target must see parameters before go */
 552 +       launch->flags |= LAUNCH_FGO;
 553 +       smp_wmb();              /* Target must see go before we poll  */
 554 +
 555 +       while ((launch->flags & LAUNCH_FGONE) == 0)
 556 +               ;
 557 +       smp_rmb();      /* Target will be updating flags soon */
 558 +       pr_debug("launch: cpu%d gone!\n", cpu);
 559 +}
 560 diff --git a/arch/mips/ralink/mt7621.c b/arch/mips/ralink/mt7621.c
 561 new file mode 100644
 562 index 0000000..2aac87c
 563 --- /dev/null
 564 +++ b/arch/mips/ralink/mt7621.c
 565 @@ -0,0 +1,183 @@
 566 +/*
 567 + * This program is free software; you can redistribute it and/or modify it
 568 + * under the terms of the GNU General Public License version 2 as published
 569 + * by the Free Software Foundation.
 570 + *
 571 + * Parts of this file are based on Ralink's 2.6.21 BSP
 572 + *
 573 + * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
 574 + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
 575 + * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
 576 + */
 577 +
 578 +#include <linux/kernel.h>
 579 +#include <linux/init.h>
 580 +#include <linux/module.h>
 581 +#include <asm/gcmpregs.h>
 582 +
 583 +#include <asm/mipsregs.h>
 584 +#include <asm/smp-ops.h>
 585 +#include <asm/mach-ralink/ralink_regs.h>
 586 +#include <asm/mach-ralink/mt7621.h>
 587 +
 588 +#include <pinmux.h>
 589 +
 590 +#include "common.h"
 591 +
 592 +#define SYSC_REG_SYSCFG                0x10
 593 +#define SYSC_REG_CPLL_CLKCFG0  0x2c
 594 +#define SYSC_REG_CUR_CLK_STS   0x44
 595 +#define CPU_CLK_SEL            (BIT(30) | BIT(31))
 596 +
 597 +#define MT7621_GPIO_MODE_UART1         1
 598 +#define MT7621_GPIO_MODE_I2C           2
 599 +#define MT7621_GPIO_MODE_UART2         3
 600 +#define MT7621_GPIO_MODE_UART3         5
 601 +#define MT7621_GPIO_MODE_JTAG          7
 602 +#define MT7621_GPIO_MODE_WDT_MASK      0x3
 603 +#define MT7621_GPIO_MODE_WDT_SHIFT     8
 604 +#define MT7621_GPIO_MODE_WDT_GPIO      1
 605 +#define MT7621_GPIO_MODE_PCIE_RST      0
 606 +#define MT7621_GPIO_MODE_PCIE_REF      2
 607 +#define MT7621_GPIO_MODE_PCIE_MASK     0x3
 608 +#define MT7621_GPIO_MODE_PCIE_SHIFT    10
 609 +#define MT7621_GPIO_MODE_PCIE_GPIO     1
 610 +#define MT7621_GPIO_MODE_MDIO          12
 611 +#define MT7621_GPIO_MODE_RGMII1                14
 612 +#define MT7621_GPIO_MODE_RGMII2                15
 613 +#define MT7621_GPIO_MODE_SPI_MASK      0x3
 614 +#define MT7621_GPIO_MODE_SPI_SHIFT     16
 615 +#define MT7621_GPIO_MODE_SPI_GPIO      1
 616 +#define MT7621_GPIO_MODE_SDHCI_MASK    0x3
 617 +#define MT7621_GPIO_MODE_SDHCI_SHIFT   18
 618 +#define MT7621_GPIO_MODE_SDHCI_GPIO    1
 619 +
 620 +static struct rt2880_pmx_func uart1_grp[] =  { FUNC("uart1", 0, 1, 2) };
 621 +static struct rt2880_pmx_func i2c_grp[] =  { FUNC("i2c", 0, 3, 2) };
 622 +static struct rt2880_pmx_func uart3_grp[] = { FUNC("uart3", 0, 5, 4) };
 623 +static struct rt2880_pmx_func uart2_grp[] = { FUNC("uart2", 0, 9, 4) };
 624 +static struct rt2880_pmx_func jtag_grp[] = { FUNC("jtag", 0, 13, 5) };
 625 +static struct rt2880_pmx_func wdt_grp[] = {
 626 +       FUNC("wdt rst", 0, 18, 1),
 627 +       FUNC("wdt refclk", 2, 18, 1),
 628 +};
 629 +static struct rt2880_pmx_func pcie_rst_grp[] = {
 630 +       FUNC("pcie rst", MT7621_GPIO_MODE_PCIE_RST, 19, 1),
 631 +       FUNC("pcie refclk", MT7621_GPIO_MODE_PCIE_REF, 19, 1)
 632 +};
 633 +static struct rt2880_pmx_func mdio_grp[] = { FUNC("mdio", 0, 20, 2) };
 634 +static struct rt2880_pmx_func rgmii2_grp[] = { FUNC("rgmii2", 0, 22, 12) };
 635 +static struct rt2880_pmx_func spi_grp[] = {
 636 +       FUNC("spi", 0, 34, 7),
 637 +       FUNC("nand", 2, 34, 8),
 638 +};
 639 +static struct rt2880_pmx_func sdhci_grp[] = {
 640 +       FUNC("sdhci", 0, 41, 8),
 641 +       FUNC("nand", 2, 41, 8),
 642 +};
 643 +static struct rt2880_pmx_func rgmii1_grp[] = { FUNC("rgmii1", 0, 49, 12) };
 644 +
 645 +static struct rt2880_pmx_group mt7621_pinmux_data[] = {
 646 +       GRP("uart1", uart1_grp, 1, MT7621_GPIO_MODE_UART1),
 647 +       GRP("i2c", i2c_grp, 1, MT7621_GPIO_MODE_I2C),
 648 +       GRP("uart3", uart2_grp, 1, MT7621_GPIO_MODE_UART2),
 649 +       GRP("uart2", uart3_grp, 1, MT7621_GPIO_MODE_UART3),
 650 +       GRP("jtag", jtag_grp, 1, MT7621_GPIO_MODE_JTAG),
 651 +       GRP_G("wdt", wdt_grp, MT7621_GPIO_MODE_WDT_MASK,
 652 +               MT7621_GPIO_MODE_WDT_GPIO, MT7621_GPIO_MODE_WDT_SHIFT),
 653 +       GRP_G("pcie", pcie_rst_grp, MT7621_GPIO_MODE_PCIE_MASK,
 654 +               MT7621_GPIO_MODE_PCIE_GPIO, MT7621_GPIO_MODE_PCIE_SHIFT),
 655 +       GRP("mdio", mdio_grp, 1, MT7621_GPIO_MODE_MDIO),
 656 +       GRP("rgmii2", rgmii2_grp, 1, MT7621_GPIO_MODE_RGMII2),
 657 +       GRP_G("spi", spi_grp, MT7621_GPIO_MODE_SPI_MASK,
 658 +               MT7621_GPIO_MODE_SPI_GPIO, MT7621_GPIO_MODE_SPI_SHIFT),
 659 +       GRP_G("sdhci", sdhci_grp, MT7621_GPIO_MODE_SDHCI_MASK,
 660 +               MT7621_GPIO_MODE_SDHCI_GPIO, MT7621_GPIO_MODE_SDHCI_SHIFT),
 661 +       GRP("rgmii1", rgmii1_grp, 1, MT7621_GPIO_MODE_RGMII1),
 662 +       { 0 }
 663 +};
 664 +
 665 +void __init ralink_clk_init(void)
 666 +{
 667 +       int cpu_fdiv = 0;
 668 +       int cpu_ffrac = 0;
 669 +       int fbdiv = 0;
 670 +       u32 clk_sts, syscfg;
 671 +       u8 clk_sel = 0, xtal_mode;
 672 +       u32 cpu_clk;
 673 +
 674 +       if ((rt_sysc_r32(SYSC_REG_CPLL_CLKCFG0) & CPU_CLK_SEL) != 0)
 675 +               clk_sel = 1;
 676 +
 677 +       switch (clk_sel) {
 678 +       case 0:
 679 +               clk_sts = rt_sysc_r32(SYSC_REG_CUR_CLK_STS);
 680 +               cpu_fdiv = ((clk_sts >> 8) & 0x1F);
 681 +               cpu_ffrac = (clk_sts & 0x1F);
 682 +               cpu_clk = (500 * cpu_ffrac / cpu_fdiv) * 1000 * 1000;
 683 +               break;
 684 +
 685 +       case 1:
 686 +               fbdiv = ((rt_sysc_r32(0x648) >> 4) & 0x7F) + 1;
 687 +               syscfg = rt_sysc_r32(SYSC_REG_SYSCFG);
 688 +               xtal_mode = (syscfg >> 6) & 0x7;
 689 +               if(xtal_mode >= 6) { //25Mhz Xtal
 690 +                       cpu_clk = 25 * fbdiv * 1000 * 1000;
 691 +               } else if(xtal_mode >=3) { //40Mhz Xtal
 692 +                       cpu_clk = 40 * fbdiv * 1000 * 1000;
 693 +               } else { // 20Mhz Xtal
 694 +                       cpu_clk = 20 * fbdiv * 1000 * 1000;
 695 +               }
 696 +               break;
 697 +       }
 698 +       cpu_clk = 880000000;
 699 +       ralink_clk_add("cpu", cpu_clk);
 700 +       ralink_clk_add("1e000b00.spi", 50000000);
 701 +       ralink_clk_add("1e000c00.uartlite", 50000000);
 702 +       ralink_clk_add("1e000d00.uart", 50000000);
 703 +}
 704 +
 705 +void __init ralink_of_remap(void)
 706 +{
 707 +       rt_sysc_membase = plat_of_remap_node("mtk,mt7621-sysc");
 708 +       rt_memc_membase = plat_of_remap_node("mtk,mt7621-memc");
 709 +
 710 +       if (!rt_sysc_membase || !rt_memc_membase)
 711 +               panic("Failed to remap core resources");
 712 +}
 713 +
 714 +void prom_soc_init(struct ralink_soc_info *soc_info)
 715 +{
 716 +       void __iomem *sysc = (void __iomem *) KSEG1ADDR(MT7621_SYSC_BASE);
 717 +       unsigned char *name = NULL;
 718 +       u32 n0;
 719 +       u32 n1;
 720 +       u32 rev;
 721 +
 722 +       n0 = __raw_readl(sysc + SYSC_REG_CHIP_NAME0);
 723 +       n1 = __raw_readl(sysc + SYSC_REG_CHIP_NAME1);
 724 +
 725 +       if (n0 == MT7621_CHIP_NAME0 && n1 == MT7621_CHIP_NAME1) {
 726 +               name = "MT7621";
 727 +               soc_info->compatible = "mtk,mt7621-soc";
 728 +       } else {
 729 +               panic("mt7621: unknown SoC, n0:%08x n1:%08x\n", n0, n1);
 730 +       }
 731 +
 732 +       rev = __raw_readl(sysc + SYSC_REG_CHIP_REV);
 733 +
 734 +       snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN,
 735 +               "Mediatek %s ver:%u eco:%u",
 736 +               name,
 737 +               (rev >> CHIP_REV_VER_SHIFT) & CHIP_REV_VER_MASK,
 738 +               (rev & CHIP_REV_ECO_MASK));
 739 +
 740 +       soc_info->mem_size_min = MT7621_DDR2_SIZE_MIN;
 741 +       soc_info->mem_size_max = MT7621_DDR2_SIZE_MAX;
 742 +       soc_info->mem_base = MT7621_DRAM_BASE;
 743 +
 744 +       rt2880_pinmux_data = mt7621_pinmux_data;
 745 +
 746 +       if (register_cmp_smp_ops())
 747 +               panic("failed to register_vsmp_smp_ops()");
 748 +}
 749 --
 750 1.7.10.4
 751