1 From 307b7a71a634ae3848fb7c5c05759d647e140e12 Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Sat, 18 May 2013 22:06:15 +0200
4 Subject: [PATCH 32/57] PCI: MIPS: adds mt7620a pcie driver
6 Signed-off-by: John Crispin <blogic@openwrt.org>
8 arch/mips/pci/Makefile | 1 +
9 arch/mips/pci/pci-mt7620.c | 363 +++++++++++++++++++++++++++++++++++++++++++
10 arch/mips/ralink/Kconfig | 1 +
11 3 files changed, 365 insertions(+)
12 create mode 100644 arch/mips/pci/pci-mt7620.c
14 Index: linux-3.14.18/arch/mips/pci/Makefile
15 ===================================================================
16 --- linux-3.14.18.orig/arch/mips/pci/Makefile 2014-11-13 15:45:37.323344081 +0100
17 +++ linux-3.14.18/arch/mips/pci/Makefile 2014-11-13 15:45:37.331344390 +0100
19 obj-$(CONFIG_LANTIQ) += fixup-lantiq.o
20 obj-$(CONFIG_PCI_LANTIQ) += pci-lantiq.o ops-lantiq.o
21 obj-$(CONFIG_SOC_MT7621) += pci-mt7621.o
22 +obj-$(CONFIG_SOC_MT7620) += pci-mt7620.o
23 obj-$(CONFIG_SOC_RT2880) += pci-rt2880.o
24 obj-$(CONFIG_SOC_RT3883) += pci-rt3883.o
25 obj-$(CONFIG_TANBAC_TB0219) += fixup-tb0219.o
26 Index: linux-3.14.18/arch/mips/pci/pci-mt7620.c
27 ===================================================================
28 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
29 +++ linux-3.14.18/arch/mips/pci/pci-mt7620.c 2014-11-13 18:20:27.961225097 +0100
32 + * Ralink MT7620A SoC PCI support
34 + * Copyright (C) 2007-2013 Bruce Chang
35 + * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
37 + * This program is free software; you can redistribute it and/or modify it
38 + * under the terms of the GNU General Public License version 2 as published
39 + * by the Free Software Foundation.
42 +#include <linux/types.h>
43 +#include <linux/pci.h>
44 +#include <linux/io.h>
45 +#include <linux/init.h>
46 +#include <linux/delay.h>
47 +#include <linux/interrupt.h>
48 +#include <linux/module.h>
49 +#include <linux/of.h>
50 +#include <linux/of_irq.h>
51 +#include <linux/of_pci.h>
52 +#include <linux/reset.h>
53 +#include <linux/platform_device.h>
55 +#include <asm/mach-ralink/ralink_regs.h>
56 +#include <asm/mach-ralink/mt7620.h>
58 +#define RALINK_PCI_MM_MAP_BASE 0x20000000
59 +#define RALINK_PCI_IO_MAP_BASE 0x10160000
61 +#define RALINK_INT_PCIE0 4
62 +#define RALINK_SYSCFG1 0x14
63 +#define RALINK_CLKCFG1 0x30
64 +#define RALINK_GPIOMODE 0x60
65 +#define RALINK_PCIE_CLK_GEN 0x7c
66 +#define RALINK_PCIE_CLK_GEN1 0x80
67 +#define PCIEPHY0_CFG 0x90
68 +#define PPLL_CFG1 0x9c
69 +#define PPLL_DRV 0xa0
70 +#define PDRV_SW_SET (1<<31)
71 +#define LC_CKDRVPD_ (1<<19)
73 +#define RALINK_PCI_CONFIG_ADDR 0x20
74 +#define RALINK_PCI_CONFIG_DATA_VIRT_REG 0x24
75 +#define MEMORY_BASE 0x0
76 +#define RALINK_PCIE0_RST (1<<26)
77 +#define RALINK_PCI_BASE 0xB0140000
78 +#define RALINK_PCI_MEMBASE 0x28
79 +#define RALINK_PCI_IOBASE 0x2C
81 +#define RT6855_PCIE0_OFFSET 0x2000
83 +#define RALINK_PCI_PCICFG_ADDR 0x00
84 +#define RALINK_PCI0_BAR0SETUP_ADDR 0x10
85 +#define RALINK_PCI0_IMBASEBAR0_ADDR 0x18
86 +#define RALINK_PCI0_ID 0x30
87 +#define RALINK_PCI0_CLASS 0x34
88 +#define RALINK_PCI0_SUBID 0x38
89 +#define RALINK_PCI0_STATUS 0x50
90 +#define RALINK_PCI_PCIMSK_ADDR 0x0C
92 +#define RALINK_PCIEPHY_P0_CTL_OFFSET 0x7498
93 +#define RALINK_PCIE0_CLK_EN (1 << 26)
95 +#define BUSY 0x80000000
96 +#define WAITRETRY_MAX 10
97 +#define WRITE_MODE (1UL << 23)
101 +static void __iomem *bridge_base;
102 +static void __iomem *pcie_base;
104 +static struct reset_control *rstpcie0;
106 +static inline void bridge_w32(u32 val, unsigned reg)
108 + iowrite32(val, bridge_base + reg);
111 +static inline u32 bridge_r32(unsigned reg)
113 + return ioread32(bridge_base + reg);
116 +static inline void pcie_w32(u32 val, unsigned reg)
118 + iowrite32(val, pcie_base + reg);
121 +static inline u32 pcie_r32(unsigned reg)
123 + return ioread32(pcie_base + reg);
126 +static inline void pcie_m32(u32 clr, u32 set, unsigned reg)
128 + u32 val = pcie_r32(reg);
132 + pcie_w32(val, reg);
135 +static int wait_pciephy_busy(void)
137 + unsigned long reg_value = 0x0, retry = 0;
140 + reg_value = pcie_r32(PCIEPHY0_CFG);
142 + if (reg_value & BUSY)
146 + if (retry++ > WAITRETRY_MAX){
147 + printk("PCIE-PHY retry failed.\n");
154 +static void pcie_phy(unsigned long addr, unsigned long val)
156 + wait_pciephy_busy();
157 + pcie_w32(WRITE_MODE | (val << DATA_SHIFT) | (addr << ADDR_SHIFT), PCIEPHY0_CFG);
159 + wait_pciephy_busy();
162 +static int pci_config_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 * val)
164 + unsigned int slot = PCI_SLOT(devfn);
165 + u8 func = PCI_FUNC(devfn);
173 + address = (((where & 0xF00) >> 8) << 24) | (num << 16) | (slot << 11) | (func << 8) | (where & 0xfc) | 0x80000000;
174 + bridge_w32(address, RALINK_PCI_CONFIG_ADDR);
175 + data = bridge_r32(RALINK_PCI_CONFIG_DATA_VIRT_REG);
179 + *val = (data >> ((where & 3) << 3)) & 0xff;
182 + *val = (data >> ((where & 3) << 3)) & 0xffff;
189 + return PCIBIOS_SUCCESSFUL;
192 +static int pci_config_write(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val)
194 + unsigned int slot = PCI_SLOT(devfn);
195 + u8 func = PCI_FUNC(devfn);
203 + address = (((where & 0xF00) >> 8) << 24) | (num << 16) | (slot << 11) | (func << 8) | (where & 0xfc) | 0x80000000;
204 + bridge_w32(address, RALINK_PCI_CONFIG_ADDR);
205 + data = bridge_r32(RALINK_PCI_CONFIG_DATA_VIRT_REG);
209 + data = (data & ~(0xff << ((where & 3) << 3))) |
210 + (val << ((where & 3) << 3));
213 + data = (data & ~(0xffff << ((where & 3) << 3))) |
214 + (val << ((where & 3) << 3));
221 + bridge_w32(data, RALINK_PCI_CONFIG_DATA_VIRT_REG);
223 + return PCIBIOS_SUCCESSFUL;
226 +struct pci_ops mt7620_pci_ops= {
227 + .read = pci_config_read,
228 + .write = pci_config_write,
231 +static struct resource mt7620_res_pci_mem1;
232 +static struct resource mt7620_res_pci_io1;
233 +struct pci_controller mt7620_controller = {
234 + .pci_ops = &mt7620_pci_ops,
235 + .mem_resource = &mt7620_res_pci_mem1,
236 + .mem_offset = 0x00000000UL,
237 + .io_resource = &mt7620_res_pci_io1,
238 + .io_offset = 0x00000000UL,
239 + .io_map_base = 0xa0000000,
242 +static int mt7620_pci_hw_init(struct platform_device *pdev) {
243 + /* PCIE: bypass PCIe DLL */
244 + pcie_phy(0x0, 0x80);
245 + pcie_phy(0x1, 0x04);
247 + /* PCIE: Elastic buffer control */
248 + pcie_phy(0x68, 0xB4);
250 + reset_control_assert(rstpcie0);
252 + rt_sysc_m32(RALINK_PCIE0_CLK_EN, 0, RALINK_CLKCFG1);
253 + rt_sysc_m32(BIT(19), BIT(31), PPLL_DRV);
254 + rt_sysc_m32(0x3 << 16, 0, RALINK_GPIOMODE);
256 + reset_control_deassert(rstpcie0);
257 + rt_sysc_m32(0, RALINK_PCIE0_CLK_EN, RALINK_CLKCFG1);
261 + if (!(rt_sysc_r32(PPLL_CFG1) & BIT(23))) {
262 + dev_err(&pdev->dev, "MT7620 PPLL unlock\n");
263 + reset_control_assert(rstpcie0);
264 + rt_sysc_m32(RALINK_PCIE0_CLK_EN, 0, RALINK_CLKCFG1);
267 + rt_sysc_m32(BIT(18) | BIT(17), BIT(19) | BIT(31), PPLL_DRV);
272 +static int mt7628_pci_hw_init(struct platform_device *pdev) {
275 + rt_sysc_m32(BIT(16), 0, RALINK_GPIOMODE);
276 + reset_control_deassert(rstpcie0);
277 + rt_sysc_m32(0, RALINK_PCIE0_CLK_EN, RALINK_CLKCFG1);
280 + pcie_m32(~0xff, 0x5, RALINK_PCIEPHY_P0_CTL_OFFSET);
282 + pci_config_read(NULL, 0, 0x70c, 4, &val);
283 + val &= ~(0xff) << 8;
285 + pci_config_write(NULL, 0, 0x70c, 4, val);
287 + pci_config_read(NULL, 0, 0x70c, 4, &val);
288 + dev_err(&pdev->dev, "Port 0 N_FTS = %x\n", (unsigned int) val);
293 +static int mt7620_pci_probe(struct platform_device *pdev)
295 + struct resource *bridge_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
296 + struct resource *pcie_res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
299 + rstpcie0 = devm_reset_control_get(&pdev->dev, "pcie0");
300 + if (IS_ERR(rstpcie0))
301 + return PTR_ERR(rstpcie0);
303 + bridge_base = devm_request_and_ioremap(&pdev->dev, bridge_res);
307 + pcie_base = devm_request_and_ioremap(&pdev->dev, pcie_res);
311 + iomem_resource.start = 0;
312 + iomem_resource.end = ~0;
313 + ioport_resource.start = 0;
314 + ioport_resource.end = ~0;
316 + /* bring up the pci core */
317 + switch (ralink_soc) {
318 + case MT762X_SOC_MT7620A:
319 + if (mt7620_pci_hw_init(pdev))
323 + case MT762X_SOC_MT7628AN:
324 + if (mt7628_pci_hw_init(pdev))
329 + dev_err(&pdev->dev, "pcie is not supported on this hardware\n");
334 + /* enable write access */
335 + pcie_m32(BIT(1), 0, RALINK_PCI_PCICFG_ADDR);
338 + /* check if there is a card present */
339 + if ((pcie_r32(RALINK_PCI0_STATUS) & 0x1) == 0) {
340 + reset_control_assert(rstpcie0);
341 + rt_sysc_m32(RALINK_PCIE0_CLK_EN, 0, RALINK_CLKCFG1);
342 + if (ralink_soc == MT762X_SOC_MT7620A)
343 + rt_sysc_m32(LC_CKDRVPD_, PDRV_SW_SET, PPLL_DRV);
344 + dev_err(&pdev->dev, "PCIE0 no card, disable it(RST&CLK)\n");
349 + bridge_w32(0xffffffff, RALINK_PCI_MEMBASE);
350 + bridge_w32(RALINK_PCI_IO_MAP_BASE, RALINK_PCI_IOBASE);
352 + pcie_w32(0x7FFF0001, RALINK_PCI0_BAR0SETUP_ADDR);
353 + pcie_w32(MEMORY_BASE, RALINK_PCI0_IMBASEBAR0_ADDR);
354 + pcie_w32(0x06040001, RALINK_PCI0_CLASS);
356 + /* enable interrupts */
357 + pcie_m32(0, BIT(20), RALINK_PCI_PCIMSK_ADDR);
359 + /* voodoo from the SDK driver */
360 + pci_config_read(NULL, 0, 4, 4, &val);
361 + pci_config_write(NULL, 0, 4, 4, val | 0x7);
363 + pci_load_of_ranges(&mt7620_controller, pdev->dev.of_node);
364 + register_pci_controller(&mt7620_controller);
369 +int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
375 + if ((dev->bus->number == 0) && (slot == 0)) {
376 + pcie_w32(0x7FFF0001, RALINK_PCI0_BAR0SETUP_ADDR); //open 7FFF:2G; ENABLE
377 + pci_config_write(dev->bus, 0, PCI_BASE_ADDRESS_0, 4, MEMORY_BASE);
378 + pci_config_read(dev->bus, 0, PCI_BASE_ADDRESS_0, 4, &val);
379 + } else if ((dev->bus->number == 1) && (slot == 0x0)) {
380 + irq = RALINK_INT_PCIE0;
382 + dev_err(&dev->dev, "no irq found - bus=0x%x, slot = 0x%x\n", dev->bus->number, slot);
385 + dev_err(&dev->dev, "card - bus=0x%x, slot = 0x%x irq=%d\n", dev->bus->number, slot, irq);
387 + pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 0x14); //configure cache line size 0x14
388 + pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0xFF); //configure latency timer 0x10
389 + pci_read_config_word(dev, PCI_COMMAND, &cmd);
392 + cmd = cmd | PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
393 + pci_write_config_word(dev, PCI_COMMAND, cmd);
394 + pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
395 + //pci_write_config_byte(dev, PCI_INTERRUPT_PIN, dev->irq);
400 +int pcibios_plat_dev_init(struct pci_dev *dev)
405 +static const struct of_device_id mt7620_pci_ids[] = {
406 + { .compatible = "mediatek,mt7620-pci" },
409 +MODULE_DEVICE_TABLE(of, mt7620_pci_ids);
411 +static struct platform_driver mt7620_pci_driver = {
412 + .probe = mt7620_pci_probe,
414 + .name = "mt7620-pci",
415 + .owner = THIS_MODULE,
416 + .of_match_table = of_match_ptr(mt7620_pci_ids),
420 +static int __init mt7620_pci_init(void)
422 + return platform_driver_register(&mt7620_pci_driver);
425 +arch_initcall(mt7620_pci_init);
426 Index: linux-3.14.18/arch/mips/ralink/Kconfig
427 ===================================================================
428 --- linux-3.14.18.orig/arch/mips/ralink/Kconfig 2014-11-13 15:45:37.323344081 +0100
429 +++ linux-3.14.18/arch/mips/ralink/Kconfig 2014-11-13 15:45:37.331344390 +0100
432 select USB_ARCH_HAS_OHCI
433 select USB_ARCH_HAS_EHCI
438 Index: linux-3.14.18/arch/mips/include/asm/mach-ralink/mt7620.h
439 ===================================================================
440 --- linux-3.14.18.orig/arch/mips/include/asm/mach-ralink/mt7620.h 2014-11-13 15:45:37.311343619 +0100
441 +++ linux-3.14.18/arch/mips/include/asm/mach-ralink/mt7620.h 2014-11-13 18:20:31.721370073 +0100
446 +extern enum mt762x_soc_type mt762x_soc;
448 #define MT7620_SYSC_BASE 0x10000000