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[openwrt/openwrt.git] / target / linux / ramips / patches-3.14 / 0035-NET-MIPS-add-ralink-SoC-ethernet-driver.patch
1 From c55d6cf3e2c593bf7d228c6532ec9bd8da82e09d Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Mon, 22 Apr 2013 23:20:03 +0200
4 Subject: [PATCH 35/57] NET: MIPS: add ralink SoC ethernet driver
5
6 Add support for Ralink FE and ESW.
7
8 Signed-off-by: John Crispin <blogic@openwrt.org>
9 ---
10 .../include/asm/mach-ralink/rt305x_esw_platform.h | 27 +
11 arch/mips/ralink/rt305x.c | 1 +
12 drivers/net/ethernet/Kconfig | 1 +
13 drivers/net/ethernet/Makefile | 1 +
14 drivers/net/ethernet/ralink/Kconfig | 32 +
15 drivers/net/ethernet/ralink/Makefile | 18 +
16 drivers/net/ethernet/ralink/esw_rt3052.c | 1463 ++++++++++++++++++++
17 drivers/net/ethernet/ralink/esw_rt3052.h | 32 +
18 drivers/net/ethernet/ralink/gsw_mt7620a.c | 566 ++++++++
19 drivers/net/ethernet/ralink/gsw_mt7620a.h | 30 +
20 drivers/net/ethernet/ralink/mdio.c | 244 ++++
21 drivers/net/ethernet/ralink/mdio.h | 29 +
22 drivers/net/ethernet/ralink/mdio_rt2880.c | 232 ++++
23 drivers/net/ethernet/ralink/mdio_rt2880.h | 26 +
24 drivers/net/ethernet/ralink/mt7530.c | 579 ++++++++
25 drivers/net/ethernet/ralink/mt7530.h | 20 +
26 drivers/net/ethernet/ralink/ralink_soc_eth.c | 844 +++++++++++
27 drivers/net/ethernet/ralink/ralink_soc_eth.h | 384 +++++
28 drivers/net/ethernet/ralink/soc_mt7620.c | 172 +++
29 drivers/net/ethernet/ralink/soc_rt2880.c | 52 +
30 drivers/net/ethernet/ralink/soc_rt305x.c | 113 ++
31 drivers/net/ethernet/ralink/soc_rt3883.c | 60 +
32 22 files changed, 4926 insertions(+)
33 create mode 100644 arch/mips/include/asm/mach-ralink/rt305x_esw_platform.h
34 create mode 100644 drivers/net/ethernet/ralink/Kconfig
35 create mode 100644 drivers/net/ethernet/ralink/Makefile
36 create mode 100644 drivers/net/ethernet/ralink/esw_rt3052.c
37 create mode 100644 drivers/net/ethernet/ralink/esw_rt3052.h
38 create mode 100644 drivers/net/ethernet/ralink/gsw_mt7620a.c
39 create mode 100644 drivers/net/ethernet/ralink/gsw_mt7620a.h
40 create mode 100644 drivers/net/ethernet/ralink/mdio.c
41 create mode 100644 drivers/net/ethernet/ralink/mdio.h
42 create mode 100644 drivers/net/ethernet/ralink/mdio_rt2880.c
43 create mode 100644 drivers/net/ethernet/ralink/mdio_rt2880.h
44 create mode 100644 drivers/net/ethernet/ralink/mt7530.c
45 create mode 100644 drivers/net/ethernet/ralink/mt7530.h
46 create mode 100644 drivers/net/ethernet/ralink/ralink_soc_eth.c
47 create mode 100644 drivers/net/ethernet/ralink/ralink_soc_eth.h
48 create mode 100644 drivers/net/ethernet/ralink/soc_mt7620.c
49 create mode 100644 drivers/net/ethernet/ralink/soc_rt2880.c
50 create mode 100644 drivers/net/ethernet/ralink/soc_rt305x.c
51 create mode 100644 drivers/net/ethernet/ralink/soc_rt3883.c
52
53 diff --git a/arch/mips/include/asm/mach-ralink/rt305x_esw_platform.h b/arch/mips/include/asm/mach-ralink/rt305x_esw_platform.h
54 new file mode 100644
55 index 0000000..2098c5c
56 --- /dev/null
57 +++ b/arch/mips/include/asm/mach-ralink/rt305x_esw_platform.h
58 @@ -0,0 +1,27 @@
59 +/*
60 + * Ralink RT305x SoC platform device registration
61 + *
62 + * Copyright (C) 2010 Gabor Juhos <juhosg@openwrt.org>
63 + *
64 + * This program is free software; you can redistribute it and/or modify it
65 + * under the terms of the GNU General Public License version 2 as published
66 + * by the Free Software Foundation.
67 + */
68 +
69 +#ifndef _RT305X_ESW_PLATFORM_H
70 +#define _RT305X_ESW_PLATFORM_H
71 +
72 +enum {
73 + RT305X_ESW_VLAN_CONFIG_NONE = 0,
74 + RT305X_ESW_VLAN_CONFIG_LLLLW,
75 + RT305X_ESW_VLAN_CONFIG_WLLLL,
76 +};
77 +
78 +struct rt305x_esw_platform_data
79 +{
80 + u8 vlan_config;
81 + u32 reg_initval_fct2;
82 + u32 reg_initval_fpa2;
83 +};
84 +
85 +#endif /* _RT305X_ESW_PLATFORM_H */
86 diff --git a/arch/mips/ralink/rt305x.c b/arch/mips/ralink/rt305x.c
87 index 356d6a0..ef99d78 100644
88 --- a/arch/mips/ralink/rt305x.c
89 +++ b/arch/mips/ralink/rt305x.c
90 @@ -199,6 +199,7 @@ void __init ralink_clk_init(void)
91 }
92
93 ralink_clk_add("cpu", cpu_rate);
94 + ralink_clk_add("sys", sys_rate);
95 ralink_clk_add("10000b00.spi", sys_rate);
96 ralink_clk_add("10000100.timer", wdt_rate);
97 ralink_clk_add("10000120.watchdog", wdt_rate);
98 diff --git a/drivers/net/ethernet/Kconfig b/drivers/net/ethernet/Kconfig
99 index 506b024..ef6a274 100644
100 --- a/drivers/net/ethernet/Kconfig
101 +++ b/drivers/net/ethernet/Kconfig
102 @@ -134,6 +134,7 @@ config ETHOC
103 source "drivers/net/ethernet/packetengines/Kconfig"
104 source "drivers/net/ethernet/pasemi/Kconfig"
105 source "drivers/net/ethernet/qlogic/Kconfig"
106 +source "drivers/net/ethernet/ralink/Kconfig"
107 source "drivers/net/ethernet/realtek/Kconfig"
108 source "drivers/net/ethernet/renesas/Kconfig"
109 source "drivers/net/ethernet/rdc/Kconfig"
110 diff --git a/drivers/net/ethernet/Makefile b/drivers/net/ethernet/Makefile
111 index c0b8789..7c3eb7b 100644
112 --- a/drivers/net/ethernet/Makefile
113 +++ b/drivers/net/ethernet/Makefile
114 @@ -56,6 +56,7 @@ obj-$(CONFIG_ETHOC) += ethoc.o
115 obj-$(CONFIG_NET_PACKET_ENGINE) += packetengines/
116 obj-$(CONFIG_NET_VENDOR_PASEMI) += pasemi/
117 obj-$(CONFIG_NET_VENDOR_QLOGIC) += qlogic/
118 +obj-$(CONFIG_NET_RALINK) += ralink/
119 obj-$(CONFIG_NET_VENDOR_REALTEK) += realtek/
120 obj-$(CONFIG_SH_ETH) += renesas/
121 obj-$(CONFIG_NET_VENDOR_RDC) += rdc/
122 diff --git a/drivers/net/ethernet/ralink/Kconfig b/drivers/net/ethernet/ralink/Kconfig
123 new file mode 100644
124 index 0000000..727ed78
125 --- /dev/null
126 +++ b/drivers/net/ethernet/ralink/Kconfig
127 @@ -0,0 +1,32 @@
128 +config NET_RALINK
129 + tristate "Ralink RT288X/RT3X5X/RT3662/RT3883/MT7620 ethernet driver"
130 + depends on RALINK
131 + help
132 + This driver supports the ethernet mac inside the ralink wisocs
133 +
134 +if NET_RALINK
135 +
136 +config NET_RALINK_MDIO
137 + def_bool NET_RALINK
138 + depends on (SOC_RT288X || SOC_RT3883 || SOC_MT7620)
139 + select PHYLIB
140 +
141 +config NET_RALINK_MDIO_RT2880
142 + def_bool NET_RALINK
143 + depends on (SOC_RT288X || SOC_RT3883)
144 + select NET_RALINK_MDIO
145 +
146 +config NET_RALINK_ESW_RT3052
147 + def_bool NET_RALINK
148 + depends on SOC_RT305X
149 + select PHYLIB
150 + select SWCONFIG
151 +
152 +config NET_RALINK_GSW_MT7620
153 + def_bool NET_RALINK
154 + depends on SOC_MT7620
155 + select INET_LRO
156 + select NET_RALINK_MDIO
157 + select PHYLIB
158 + select SWCONFIG
159 +endif
160 diff --git a/drivers/net/ethernet/ralink/Makefile b/drivers/net/ethernet/ralink/Makefile
161 new file mode 100644
162 index 0000000..de64edf
163 --- /dev/null
164 +++ b/drivers/net/ethernet/ralink/Makefile
165 @@ -0,0 +1,18 @@
166 +#
167 +# Makefile for the Ralink SoCs built-in ethernet macs
168 +#
169 +
170 +ralink-eth-y += ralink_soc_eth.o
171 +
172 +ralink-eth-$(CONFIG_NET_RALINK_MDIO) += mdio.o
173 +ralink-eth-$(CONFIG_NET_RALINK_MDIO_RT2880) += mdio_rt2880.o
174 +
175 +ralink-eth-$(CONFIG_NET_RALINK_ESW_RT3052) += esw_rt3052.o
176 +ralink-eth-$(CONFIG_NET_RALINK_GSW_MT7620) += gsw_mt7620a.o mt7530.o
177 +
178 +ralink-eth-$(CONFIG_SOC_RT288X) += soc_rt2880.o
179 +ralink-eth-$(CONFIG_SOC_RT305X) += soc_rt305x.o
180 +ralink-eth-$(CONFIG_SOC_RT3883) += soc_rt3883.o
181 +ralink-eth-$(CONFIG_SOC_MT7620) += soc_mt7620.o
182 +
183 +obj-$(CONFIG_NET_RALINK) += ralink-eth.o
184 diff --git a/drivers/net/ethernet/ralink/esw_rt3052.c b/drivers/net/ethernet/ralink/esw_rt3052.c
185 new file mode 100644
186 index 0000000..b937062
187 --- /dev/null
188 +++ b/drivers/net/ethernet/ralink/esw_rt3052.c
189 @@ -0,0 +1,1463 @@
190 +/*
191 + * This program is free software; you can redistribute it and/or modify
192 + * it under the terms of the GNU General Public License as published by
193 + * the Free Software Foundation; version 2 of the License
194 + *
195 + * This program is distributed in the hope that it will be useful,
196 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
197 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
198 + * GNU General Public License for more details.
199 + *
200 + * You should have received a copy of the GNU General Public License
201 + * along with this program; if not, write to the Free Software
202 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
203 + *
204 + * Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
205 + */
206 +
207 +#include <linux/module.h>
208 +#include <linux/kernel.h>
209 +#include <linux/types.h>
210 +#include <linux/dma-mapping.h>
211 +#include <linux/init.h>
212 +#include <linux/skbuff.h>
213 +#include <linux/etherdevice.h>
214 +#include <linux/ethtool.h>
215 +#include <linux/platform_device.h>
216 +#include <linux/of_device.h>
217 +#include <linux/clk.h>
218 +#include <linux/of_net.h>
219 +#include <linux/of_mdio.h>
220 +
221 +#include <asm/mach-ralink/ralink_regs.h>
222 +
223 +#include "ralink_soc_eth.h"
224 +
225 +#include <linux/ioport.h>
226 +#include <linux/switch.h>
227 +#include <linux/mii.h>
228 +
229 +#include <ralink_regs.h>
230 +#include <asm/mach-ralink/rt305x.h>
231 +#include <asm/mach-ralink/rt305x_esw_platform.h>
232 +
233 +/*
234 + * HW limitations for this switch:
235 + * - No large frame support (PKT_MAX_LEN at most 1536)
236 + * - Can't have untagged vlan and tagged vlan on one port at the same time,
237 + * though this might be possible using the undocumented PPE.
238 + */
239 +
240 +#define RT305X_ESW_REG_ISR 0x00
241 +#define RT305X_ESW_REG_IMR 0x04
242 +#define RT305X_ESW_REG_FCT0 0x08
243 +#define RT305X_ESW_REG_PFC1 0x14
244 +#define RT305X_ESW_REG_ATS 0x24
245 +#define RT305X_ESW_REG_ATS0 0x28
246 +#define RT305X_ESW_REG_ATS1 0x2c
247 +#define RT305X_ESW_REG_ATS2 0x30
248 +#define RT305X_ESW_REG_PVIDC(_n) (0x40 + 4 * (_n))
249 +#define RT305X_ESW_REG_VLANI(_n) (0x50 + 4 * (_n))
250 +#define RT305X_ESW_REG_VMSC(_n) (0x70 + 4 * (_n))
251 +#define RT305X_ESW_REG_POA 0x80
252 +#define RT305X_ESW_REG_FPA 0x84
253 +#define RT305X_ESW_REG_SOCPC 0x8c
254 +#define RT305X_ESW_REG_POC0 0x90
255 +#define RT305X_ESW_REG_POC1 0x94
256 +#define RT305X_ESW_REG_POC2 0x98
257 +#define RT305X_ESW_REG_SGC 0x9c
258 +#define RT305X_ESW_REG_STRT 0xa0
259 +#define RT305X_ESW_REG_PCR0 0xc0
260 +#define RT305X_ESW_REG_PCR1 0xc4
261 +#define RT305X_ESW_REG_FPA2 0xc8
262 +#define RT305X_ESW_REG_FCT2 0xcc
263 +#define RT305X_ESW_REG_SGC2 0xe4
264 +#define RT305X_ESW_REG_P0LED 0xa4
265 +#define RT305X_ESW_REG_P1LED 0xa8
266 +#define RT305X_ESW_REG_P2LED 0xac
267 +#define RT305X_ESW_REG_P3LED 0xb0
268 +#define RT305X_ESW_REG_P4LED 0xb4
269 +#define RT305X_ESW_REG_PXPC(_x) (0xe8 + (4 * _x))
270 +#define RT305X_ESW_REG_P1PC 0xec
271 +#define RT305X_ESW_REG_P2PC 0xf0
272 +#define RT305X_ESW_REG_P3PC 0xf4
273 +#define RT305X_ESW_REG_P4PC 0xf8
274 +#define RT305X_ESW_REG_P5PC 0xfc
275 +
276 +#define RT305X_ESW_LED_LINK 0
277 +#define RT305X_ESW_LED_100M 1
278 +#define RT305X_ESW_LED_DUPLEX 2
279 +#define RT305X_ESW_LED_ACTIVITY 3
280 +#define RT305X_ESW_LED_COLLISION 4
281 +#define RT305X_ESW_LED_LINKACT 5
282 +#define RT305X_ESW_LED_DUPLCOLL 6
283 +#define RT305X_ESW_LED_10MACT 7
284 +#define RT305X_ESW_LED_100MACT 8
285 +/* Additional led states not in datasheet: */
286 +#define RT305X_ESW_LED_BLINK 10
287 +#define RT305X_ESW_LED_ON 12
288 +
289 +#define RT305X_ESW_LINK_S 25
290 +#define RT305X_ESW_DUPLEX_S 9
291 +#define RT305X_ESW_SPD_S 0
292 +
293 +#define RT305X_ESW_PCR0_WT_NWAY_DATA_S 16
294 +#define RT305X_ESW_PCR0_WT_PHY_CMD BIT(13)
295 +#define RT305X_ESW_PCR0_CPU_PHY_REG_S 8
296 +
297 +#define RT305X_ESW_PCR1_WT_DONE BIT(0)
298 +
299 +#define RT305X_ESW_ATS_TIMEOUT (5 * HZ)
300 +#define RT305X_ESW_PHY_TIMEOUT (5 * HZ)
301 +
302 +#define RT305X_ESW_PVIDC_PVID_M 0xfff
303 +#define RT305X_ESW_PVIDC_PVID_S 12
304 +
305 +#define RT305X_ESW_VLANI_VID_M 0xfff
306 +#define RT305X_ESW_VLANI_VID_S 12
307 +
308 +#define RT305X_ESW_VMSC_MSC_M 0xff
309 +#define RT305X_ESW_VMSC_MSC_S 8
310 +
311 +#define RT305X_ESW_SOCPC_DISUN2CPU_S 0
312 +#define RT305X_ESW_SOCPC_DISMC2CPU_S 8
313 +#define RT305X_ESW_SOCPC_DISBC2CPU_S 16
314 +#define RT305X_ESW_SOCPC_CRC_PADDING BIT(25)
315 +
316 +#define RT305X_ESW_POC0_EN_BP_S 0
317 +#define RT305X_ESW_POC0_EN_FC_S 8
318 +#define RT305X_ESW_POC0_DIS_RMC2CPU_S 16
319 +#define RT305X_ESW_POC0_DIS_PORT_M 0x7f
320 +#define RT305X_ESW_POC0_DIS_PORT_S 23
321 +
322 +#define RT305X_ESW_POC2_UNTAG_EN_M 0xff
323 +#define RT305X_ESW_POC2_UNTAG_EN_S 0
324 +#define RT305X_ESW_POC2_ENAGING_S 8
325 +#define RT305X_ESW_POC2_DIS_UC_PAUSE_S 16
326 +
327 +#define RT305X_ESW_SGC2_DOUBLE_TAG_M 0x7f
328 +#define RT305X_ESW_SGC2_DOUBLE_TAG_S 0
329 +#define RT305X_ESW_SGC2_LAN_PMAP_M 0x3f
330 +#define RT305X_ESW_SGC2_LAN_PMAP_S 24
331 +
332 +#define RT305X_ESW_PFC1_EN_VLAN_M 0xff
333 +#define RT305X_ESW_PFC1_EN_VLAN_S 16
334 +#define RT305X_ESW_PFC1_EN_TOS_S 24
335 +
336 +#define RT305X_ESW_VLAN_NONE 0xfff
337 +
338 +#define RT305X_ESW_GSC_BC_STROM_MASK 0x3
339 +#define RT305X_ESW_GSC_BC_STROM_SHIFT 4
340 +
341 +#define RT305X_ESW_GSC_LED_FREQ_MASK 0x3
342 +#define RT305X_ESW_GSC_LED_FREQ_SHIFT 23
343 +
344 +#define RT305X_ESW_POA_LINK_MASK 0x1f
345 +#define RT305X_ESW_POA_LINK_SHIFT 25
346 +
347 +#define RT305X_ESW_PORT_ST_CHG BIT(26)
348 +#define RT305X_ESW_PORT0 0
349 +#define RT305X_ESW_PORT1 1
350 +#define RT305X_ESW_PORT2 2
351 +#define RT305X_ESW_PORT3 3
352 +#define RT305X_ESW_PORT4 4
353 +#define RT305X_ESW_PORT5 5
354 +#define RT305X_ESW_PORT6 6
355 +
356 +#define RT305X_ESW_PORTS_NONE 0
357 +
358 +#define RT305X_ESW_PMAP_LLLLLL 0x3f
359 +#define RT305X_ESW_PMAP_LLLLWL 0x2f
360 +#define RT305X_ESW_PMAP_WLLLLL 0x3e
361 +
362 +#define RT305X_ESW_PORTS_INTERNAL \
363 + (BIT(RT305X_ESW_PORT0) | BIT(RT305X_ESW_PORT1) | \
364 + BIT(RT305X_ESW_PORT2) | BIT(RT305X_ESW_PORT3) | \
365 + BIT(RT305X_ESW_PORT4))
366 +
367 +#define RT305X_ESW_PORTS_NOCPU \
368 + (RT305X_ESW_PORTS_INTERNAL | BIT(RT305X_ESW_PORT5))
369 +
370 +#define RT305X_ESW_PORTS_CPU BIT(RT305X_ESW_PORT6)
371 +
372 +#define RT305X_ESW_PORTS_ALL \
373 + (RT305X_ESW_PORTS_NOCPU | RT305X_ESW_PORTS_CPU)
374 +
375 +#define RT305X_ESW_NUM_VLANS 16
376 +#define RT305X_ESW_NUM_VIDS 4096
377 +#define RT305X_ESW_NUM_PORTS 7
378 +#define RT305X_ESW_NUM_LANWAN 6
379 +#define RT305X_ESW_NUM_LEDS 5
380 +
381 +#define RT5350_ESW_REG_PXTPC(_x) (0x150 + (4 * _x))
382 +#define RT5350_EWS_REG_LED_POLARITY 0x168
383 +#define RT5350_RESET_EPHY BIT(24)
384 +#define SYSC_REG_RESET_CTRL 0x34
385 +
386 +enum {
387 + /* Global attributes. */
388 + RT305X_ESW_ATTR_ENABLE_VLAN,
389 + RT305X_ESW_ATTR_ALT_VLAN_DISABLE,
390 + RT305X_ESW_ATTR_BC_STATUS,
391 + RT305X_ESW_ATTR_LED_FREQ,
392 + /* Port attributes. */
393 + RT305X_ESW_ATTR_PORT_DISABLE,
394 + RT305X_ESW_ATTR_PORT_DOUBLETAG,
395 + RT305X_ESW_ATTR_PORT_UNTAG,
396 + RT305X_ESW_ATTR_PORT_LED,
397 + RT305X_ESW_ATTR_PORT_LAN,
398 + RT305X_ESW_ATTR_PORT_RECV_BAD,
399 + RT305X_ESW_ATTR_PORT_RECV_GOOD,
400 + RT5350_ESW_ATTR_PORT_TR_BAD,
401 + RT5350_ESW_ATTR_PORT_TR_GOOD,
402 +};
403 +
404 +struct esw_port {
405 + bool disable;
406 + bool doubletag;
407 + bool untag;
408 + u8 led;
409 + u16 pvid;
410 +};
411 +
412 +struct esw_vlan {
413 + u8 ports;
414 + u16 vid;
415 +};
416 +
417 +struct rt305x_esw {
418 + struct device *dev;
419 + void __iomem *base;
420 + int irq;
421 + const struct rt305x_esw_platform_data *pdata;
422 + /* Protects against concurrent register rmw operations. */
423 + spinlock_t reg_rw_lock;
424 +
425 + unsigned char port_map;
426 + unsigned int reg_initval_fct2;
427 + unsigned int reg_initval_fpa2;
428 + unsigned int reg_led_polarity;
429 +
430 +
431 + struct switch_dev swdev;
432 + bool global_vlan_enable;
433 + bool alt_vlan_disable;
434 + int bc_storm_protect;
435 + int led_frequency;
436 + struct esw_vlan vlans[RT305X_ESW_NUM_VLANS];
437 + struct esw_port ports[RT305X_ESW_NUM_PORTS];
438 +
439 +};
440 +
441 +static inline void esw_w32(struct rt305x_esw *esw, u32 val, unsigned reg)
442 +{
443 + __raw_writel(val, esw->base + reg);
444 +}
445 +
446 +static inline u32 esw_r32(struct rt305x_esw *esw, unsigned reg)
447 +{
448 + return __raw_readl(esw->base + reg);
449 +}
450 +
451 +static inline void esw_rmw_raw(struct rt305x_esw *esw, unsigned reg, unsigned long mask,
452 + unsigned long val)
453 +{
454 + unsigned long t;
455 +
456 + t = __raw_readl(esw->base + reg) & ~mask;
457 + __raw_writel(t | val, esw->base + reg);
458 +}
459 +
460 +static void esw_rmw(struct rt305x_esw *esw, unsigned reg, unsigned long mask,
461 + unsigned long val)
462 +{
463 + unsigned long flags;
464 +
465 + spin_lock_irqsave(&esw->reg_rw_lock, flags);
466 + esw_rmw_raw(esw, reg, mask, val);
467 + spin_unlock_irqrestore(&esw->reg_rw_lock, flags);
468 +}
469 +
470 +static u32 rt305x_mii_write(struct rt305x_esw *esw, u32 phy_addr, u32 phy_register,
471 + u32 write_data)
472 +{
473 + unsigned long t_start = jiffies;
474 + int ret = 0;
475 +
476 + while (1) {
477 + if (!(esw_r32(esw, RT305X_ESW_REG_PCR1) &
478 + RT305X_ESW_PCR1_WT_DONE))
479 + break;
480 + if (time_after(jiffies, t_start + RT305X_ESW_PHY_TIMEOUT)) {
481 + ret = 1;
482 + goto out;
483 + }
484 + }
485 +
486 + write_data &= 0xffff;
487 + esw_w32(esw,
488 + (write_data << RT305X_ESW_PCR0_WT_NWAY_DATA_S) |
489 + (phy_register << RT305X_ESW_PCR0_CPU_PHY_REG_S) |
490 + (phy_addr) | RT305X_ESW_PCR0_WT_PHY_CMD,
491 + RT305X_ESW_REG_PCR0);
492 +
493 + t_start = jiffies;
494 + while (1) {
495 + if (esw_r32(esw, RT305X_ESW_REG_PCR1) &
496 + RT305X_ESW_PCR1_WT_DONE)
497 + break;
498 +
499 + if (time_after(jiffies, t_start + RT305X_ESW_PHY_TIMEOUT)) {
500 + ret = 1;
501 + break;
502 + }
503 + }
504 +out:
505 + if (ret)
506 + printk(KERN_ERR "ramips_eth: MDIO timeout\n");
507 + return ret;
508 +}
509 +
510 +static unsigned esw_get_vlan_id(struct rt305x_esw *esw, unsigned vlan)
511 +{
512 + unsigned s;
513 + unsigned val;
514 +
515 + s = RT305X_ESW_VLANI_VID_S * (vlan % 2);
516 + val = esw_r32(esw, RT305X_ESW_REG_VLANI(vlan / 2));
517 + val = (val >> s) & RT305X_ESW_VLANI_VID_M;
518 +
519 + return val;
520 +}
521 +
522 +static void esw_set_vlan_id(struct rt305x_esw *esw, unsigned vlan, unsigned vid)
523 +{
524 + unsigned s;
525 +
526 + s = RT305X_ESW_VLANI_VID_S * (vlan % 2);
527 + esw_rmw(esw,
528 + RT305X_ESW_REG_VLANI(vlan / 2),
529 + RT305X_ESW_VLANI_VID_M << s,
530 + (vid & RT305X_ESW_VLANI_VID_M) << s);
531 +}
532 +
533 +static unsigned esw_get_pvid(struct rt305x_esw *esw, unsigned port)
534 +{
535 + unsigned s, val;
536 +
537 + s = RT305X_ESW_PVIDC_PVID_S * (port % 2);
538 + val = esw_r32(esw, RT305X_ESW_REG_PVIDC(port / 2));
539 + return (val >> s) & RT305X_ESW_PVIDC_PVID_M;
540 +}
541 +
542 +static void esw_set_pvid(struct rt305x_esw *esw, unsigned port, unsigned pvid)
543 +{
544 + unsigned s;
545 +
546 + s = RT305X_ESW_PVIDC_PVID_S * (port % 2);
547 + esw_rmw(esw,
548 + RT305X_ESW_REG_PVIDC(port / 2),
549 + RT305X_ESW_PVIDC_PVID_M << s,
550 + (pvid & RT305X_ESW_PVIDC_PVID_M) << s);
551 +}
552 +
553 +static unsigned esw_get_vmsc(struct rt305x_esw *esw, unsigned vlan)
554 +{
555 + unsigned s, val;
556 +
557 + s = RT305X_ESW_VMSC_MSC_S * (vlan % 4);
558 + val = esw_r32(esw, RT305X_ESW_REG_VMSC(vlan / 4));
559 + val = (val >> s) & RT305X_ESW_VMSC_MSC_M;
560 +
561 + return val;
562 +}
563 +
564 +static void esw_set_vmsc(struct rt305x_esw *esw, unsigned vlan, unsigned msc)
565 +{
566 + unsigned s;
567 +
568 + s = RT305X_ESW_VMSC_MSC_S * (vlan % 4);
569 + esw_rmw(esw,
570 + RT305X_ESW_REG_VMSC(vlan / 4),
571 + RT305X_ESW_VMSC_MSC_M << s,
572 + (msc & RT305X_ESW_VMSC_MSC_M) << s);
573 +}
574 +
575 +static unsigned esw_get_port_disable(struct rt305x_esw *esw)
576 +{
577 + unsigned reg;
578 + reg = esw_r32(esw, RT305X_ESW_REG_POC0);
579 + return (reg >> RT305X_ESW_POC0_DIS_PORT_S) &
580 + RT305X_ESW_POC0_DIS_PORT_M;
581 +}
582 +
583 +static void esw_set_port_disable(struct rt305x_esw *esw, unsigned disable_mask)
584 +{
585 + unsigned old_mask;
586 + unsigned enable_mask;
587 + unsigned changed;
588 + int i;
589 +
590 + old_mask = esw_get_port_disable(esw);
591 + changed = old_mask ^ disable_mask;
592 + enable_mask = old_mask & disable_mask;
593 +
594 + /* enable before writing to MII */
595 + esw_rmw(esw, RT305X_ESW_REG_POC0,
596 + (RT305X_ESW_POC0_DIS_PORT_M <<
597 + RT305X_ESW_POC0_DIS_PORT_S),
598 + enable_mask << RT305X_ESW_POC0_DIS_PORT_S);
599 +
600 + for (i = 0; i < RT305X_ESW_NUM_LEDS; i++) {
601 + if (!(changed & (1 << i)))
602 + continue;
603 + if (disable_mask & (1 << i)) {
604 + /* disable */
605 + rt305x_mii_write(esw, i, MII_BMCR,
606 + BMCR_PDOWN);
607 + } else {
608 + /* enable */
609 + rt305x_mii_write(esw, i, MII_BMCR,
610 + BMCR_FULLDPLX |
611 + BMCR_ANENABLE |
612 + BMCR_ANRESTART |
613 + BMCR_SPEED100);
614 + }
615 + }
616 +
617 + /* disable after writing to MII */
618 + esw_rmw(esw, RT305X_ESW_REG_POC0,
619 + (RT305X_ESW_POC0_DIS_PORT_M <<
620 + RT305X_ESW_POC0_DIS_PORT_S),
621 + disable_mask << RT305X_ESW_POC0_DIS_PORT_S);
622 +}
623 +
624 +static void esw_set_gsc(struct rt305x_esw *esw)
625 +{
626 + esw_rmw(esw, RT305X_ESW_REG_SGC,
627 + RT305X_ESW_GSC_BC_STROM_MASK << RT305X_ESW_GSC_BC_STROM_SHIFT,
628 + esw->bc_storm_protect << RT305X_ESW_GSC_BC_STROM_SHIFT);
629 + esw_rmw(esw, RT305X_ESW_REG_SGC,
630 + RT305X_ESW_GSC_LED_FREQ_MASK << RT305X_ESW_GSC_LED_FREQ_SHIFT,
631 + esw->led_frequency << RT305X_ESW_GSC_LED_FREQ_SHIFT);
632 +}
633 +
634 +static int esw_apply_config(struct switch_dev *dev);
635 +
636 +static void esw_hw_init(struct rt305x_esw *esw)
637 +{
638 + int i;
639 + u8 port_disable = 0;
640 + u8 port_map = RT305X_ESW_PMAP_LLLLLL;
641 +
642 + /* vodoo from original driver */
643 + esw_w32(esw, 0xC8A07850, RT305X_ESW_REG_FCT0);
644 + esw_w32(esw, 0x00000000, RT305X_ESW_REG_SGC2);
645 + /* Port priority 1 for all ports, vlan enabled. */
646 + esw_w32(esw, 0x00005555 |
647 + (RT305X_ESW_PORTS_ALL << RT305X_ESW_PFC1_EN_VLAN_S),
648 + RT305X_ESW_REG_PFC1);
649 +
650 + /* Enable Back Pressure, and Flow Control */
651 + esw_w32(esw,
652 + ((RT305X_ESW_PORTS_ALL << RT305X_ESW_POC0_EN_BP_S) |
653 + (RT305X_ESW_PORTS_ALL << RT305X_ESW_POC0_EN_FC_S)),
654 + RT305X_ESW_REG_POC0);
655 +
656 + /* Enable Aging, and VLAN TAG removal */
657 + esw_w32(esw,
658 + ((RT305X_ESW_PORTS_ALL << RT305X_ESW_POC2_ENAGING_S) |
659 + (RT305X_ESW_PORTS_NOCPU << RT305X_ESW_POC2_UNTAG_EN_S)),
660 + RT305X_ESW_REG_POC2);
661 +
662 + if (esw->reg_initval_fct2)
663 + esw_w32(esw, esw->reg_initval_fct2, RT305X_ESW_REG_FCT2);
664 + else
665 + esw_w32(esw, esw->pdata->reg_initval_fct2, RT305X_ESW_REG_FCT2);
666 +
667 + /*
668 + * 300s aging timer, max packet len 1536, broadcast storm prevention
669 + * disabled, disable collision abort, mac xor48 hash, 10 packet back
670 + * pressure jam, GMII disable was_transmit, back pressure disabled,
671 + * 30ms led flash, unmatched IGMP as broadcast, rmc tb fault to all
672 + * ports.
673 + */
674 + esw_w32(esw, 0x0008a301, RT305X_ESW_REG_SGC);
675 +
676 + /* Setup SoC Port control register */
677 + esw_w32(esw,
678 + (RT305X_ESW_SOCPC_CRC_PADDING |
679 + (RT305X_ESW_PORTS_CPU << RT305X_ESW_SOCPC_DISUN2CPU_S) |
680 + (RT305X_ESW_PORTS_CPU << RT305X_ESW_SOCPC_DISMC2CPU_S) |
681 + (RT305X_ESW_PORTS_CPU << RT305X_ESW_SOCPC_DISBC2CPU_S)),
682 + RT305X_ESW_REG_SOCPC);
683 +
684 + if (esw->reg_initval_fpa2)
685 + esw_w32(esw, esw->reg_initval_fpa2, RT305X_ESW_REG_FPA2);
686 + else
687 + esw_w32(esw, esw->pdata->reg_initval_fpa2, RT305X_ESW_REG_FPA2);
688 + esw_w32(esw, 0x00000000, RT305X_ESW_REG_FPA);
689 +
690 + /* Force Link/Activity on ports */
691 + esw_w32(esw, 0x00000005, RT305X_ESW_REG_P0LED);
692 + esw_w32(esw, 0x00000005, RT305X_ESW_REG_P1LED);
693 + esw_w32(esw, 0x00000005, RT305X_ESW_REG_P2LED);
694 + esw_w32(esw, 0x00000005, RT305X_ESW_REG_P3LED);
695 + esw_w32(esw, 0x00000005, RT305X_ESW_REG_P4LED);
696 +
697 + /* Copy disabled port configuration from bootloader setup */
698 + port_disable = esw_get_port_disable(esw);
699 + for (i = 0; i < 6; i++)
700 + esw->ports[i].disable = (port_disable & (1 << i)) != 0;
701 +
702 + if (soc_is_rt3352()) {
703 + /* reset EPHY */
704 + u32 val = rt_sysc_r32(SYSC_REG_RESET_CTRL);
705 + rt_sysc_w32(val | RT5350_RESET_EPHY, SYSC_REG_RESET_CTRL);
706 + rt_sysc_w32(val, SYSC_REG_RESET_CTRL);
707 +
708 + rt305x_mii_write(esw, 0, 31, 0x8000);
709 + for (i = 0; i < 5; i++) {
710 + if (esw->ports[i].disable) {
711 + rt305x_mii_write(esw, i, MII_BMCR, BMCR_PDOWN);
712 + } else {
713 + rt305x_mii_write(esw, i, MII_BMCR,
714 + BMCR_FULLDPLX |
715 + BMCR_ANENABLE |
716 + BMCR_SPEED100);
717 + }
718 + /* TX10 waveform coefficient LSB=0 disable PHY */
719 + rt305x_mii_write(esw, i, 26, 0x1601);
720 + /* TX100/TX10 AD/DA current bias */
721 + rt305x_mii_write(esw, i, 29, 0x7016);
722 + /* TX100 slew rate control */
723 + rt305x_mii_write(esw, i, 30, 0x0038);
724 + }
725 +
726 + /* select global register */
727 + rt305x_mii_write(esw, 0, 31, 0x0);
728 + /* enlarge agcsel threshold 3 and threshold 2 */
729 + rt305x_mii_write(esw, 0, 1, 0x4a40);
730 + /* enlarge agcsel threshold 5 and threshold 4 */
731 + rt305x_mii_write(esw, 0, 2, 0x6254);
732 + /* enlarge agcsel threshold */
733 + rt305x_mii_write(esw, 0, 3, 0xa17f);
734 + rt305x_mii_write(esw, 0,12, 0x7eaa);
735 + /* longer TP_IDL tail length */
736 + rt305x_mii_write(esw, 0, 14, 0x65);
737 + /* increased squelch pulse count threshold. */
738 + rt305x_mii_write(esw, 0, 16, 0x0684);
739 + /* set TX10 signal amplitude threshold to minimum */
740 + rt305x_mii_write(esw, 0, 17, 0x0fe0);
741 + /* set squelch amplitude to higher threshold */
742 + rt305x_mii_write(esw, 0, 18, 0x40ba);
743 + /* tune TP_IDL tail and head waveform, enable power down slew rate control */
744 + rt305x_mii_write(esw, 0, 22, 0x253f);
745 + /* set PLL/Receive bias current are calibrated */
746 + rt305x_mii_write(esw, 0, 27, 0x2fda);
747 + /* change PLL/Receive bias current to internal(RT3350) */
748 + rt305x_mii_write(esw, 0, 28, 0xc410);
749 + /* change PLL bias current to internal(RT3052_MP3) */
750 + rt305x_mii_write(esw, 0, 29, 0x598b);
751 + /* select local register */
752 + rt305x_mii_write(esw, 0, 31, 0x8000);
753 + } else if (soc_is_rt5350()) {
754 + /* reset EPHY */
755 + u32 val = rt_sysc_r32(SYSC_REG_RESET_CTRL);
756 + rt_sysc_w32(val | RT5350_RESET_EPHY, SYSC_REG_RESET_CTRL);
757 + rt_sysc_w32(val, SYSC_REG_RESET_CTRL);
758 +
759 + /* set the led polarity */
760 + esw_w32(esw, esw->reg_led_polarity & 0x1F, RT5350_EWS_REG_LED_POLARITY);
761 +
762 + /* local registers */
763 + rt305x_mii_write(esw, 0, 31, 0x8000);
764 + for (i = 0; i < 5; i++) {
765 + if (esw->ports[i].disable) {
766 + rt305x_mii_write(esw, i, MII_BMCR, BMCR_PDOWN);
767 + } else {
768 + rt305x_mii_write(esw, i, MII_BMCR,
769 + BMCR_FULLDPLX |
770 + BMCR_ANENABLE |
771 + BMCR_SPEED100);
772 + }
773 + /* TX10 waveform coefficient LSB=0 disable PHY */
774 + rt305x_mii_write(esw, i, 26, 0x1601);
775 + /* TX100/TX10 AD/DA current bias */
776 + rt305x_mii_write(esw, i, 29, 0x7015);
777 + /* TX100 slew rate control */
778 + rt305x_mii_write(esw, i, 30, 0x0038);
779 + }
780 +
781 + /* global registers */
782 + rt305x_mii_write(esw, 0, 31, 0x0);
783 + /* enlarge agcsel threshold 3 and threshold 2 */
784 + rt305x_mii_write(esw, 0, 1, 0x4a40);
785 + /* enlarge agcsel threshold 5 and threshold 4 */
786 + rt305x_mii_write(esw, 0, 2, 0x6254);
787 + /* enlarge agcsel threshold 6 */
788 + rt305x_mii_write(esw, 0, 3, 0xa17f);
789 + rt305x_mii_write(esw, 0, 12, 0x7eaa);
790 + /* longer TP_IDL tail length */
791 + rt305x_mii_write(esw, 0, 14, 0x65);
792 + /* increased squelch pulse count threshold. */
793 + rt305x_mii_write(esw, 0, 16, 0x0684);
794 + /* set TX10 signal amplitude threshold to minimum */
795 + rt305x_mii_write(esw, 0, 17, 0x0fe0);
796 + /* set squelch amplitude to higher threshold */
797 + rt305x_mii_write(esw, 0, 18, 0x40ba);
798 + /* tune TP_IDL tail and head waveform, enable power down slew rate control */
799 + rt305x_mii_write(esw, 0, 22, 0x253f);
800 + /* set PLL/Receive bias current are calibrated */
801 + rt305x_mii_write(esw, 0, 27, 0x2fda);
802 + /* change PLL/Receive bias current to internal(RT3350) */
803 + rt305x_mii_write(esw, 0, 28, 0xc410);
804 + /* change PLL bias current to internal(RT3052_MP3) */
805 + rt305x_mii_write(esw, 0, 29, 0x598b);
806 + /* select local register */
807 + rt305x_mii_write(esw, 0, 31, 0x8000);
808 + } else {
809 + rt305x_mii_write(esw, 0, 31, 0x8000);
810 + for (i = 0; i < 5; i++) {
811 + if (esw->ports[i].disable) {
812 + rt305x_mii_write(esw, i, MII_BMCR, BMCR_PDOWN);
813 + } else {
814 + rt305x_mii_write(esw, i, MII_BMCR,
815 + BMCR_FULLDPLX |
816 + BMCR_ANENABLE |
817 + BMCR_SPEED100);
818 + }
819 + /* TX10 waveform coefficient */
820 + rt305x_mii_write(esw, i, 26, 0x1601);
821 + /* TX100/TX10 AD/DA current bias */
822 + rt305x_mii_write(esw, i, 29, 0x7058);
823 + /* TX100 slew rate control */
824 + rt305x_mii_write(esw, i, 30, 0x0018);
825 + }
826 +
827 + /* PHY IOT */
828 + /* select global register */
829 + rt305x_mii_write(esw, 0, 31, 0x0);
830 + /* tune TP_IDL tail and head waveform */
831 + rt305x_mii_write(esw, 0, 22, 0x052f);
832 + /* set TX10 signal amplitude threshold to minimum */
833 + rt305x_mii_write(esw, 0, 17, 0x0fe0);
834 + /* set squelch amplitude to higher threshold */
835 + rt305x_mii_write(esw, 0, 18, 0x40ba);
836 + /* longer TP_IDL tail length */
837 + rt305x_mii_write(esw, 0, 14, 0x65);
838 + /* select local register */
839 + rt305x_mii_write(esw, 0, 31, 0x8000);
840 + }
841 +
842 + if (esw->port_map)
843 + port_map = esw->port_map;
844 + else
845 + port_map = RT305X_ESW_PMAP_LLLLLL;
846 +
847 + /*
848 + * Unused HW feature, but still nice to be consistent here...
849 + * This is also exported to userspace ('lan' attribute) so it's
850 + * conveniently usable to decide which ports go into the wan vlan by
851 + * default.
852 + */
853 + esw_rmw(esw, RT305X_ESW_REG_SGC2,
854 + RT305X_ESW_SGC2_LAN_PMAP_M << RT305X_ESW_SGC2_LAN_PMAP_S,
855 + port_map << RT305X_ESW_SGC2_LAN_PMAP_S);
856 +
857 + /* make the switch leds blink */
858 + for (i = 0; i < RT305X_ESW_NUM_LEDS; i++)
859 + esw->ports[i].led = 0x05;
860 +
861 + /* Apply the empty config. */
862 + esw_apply_config(&esw->swdev);
863 +
864 + /* Only unmask the port change interrupt */
865 + esw_w32(esw, ~RT305X_ESW_PORT_ST_CHG, RT305X_ESW_REG_IMR);
866 +}
867 +
868 +static irqreturn_t esw_interrupt(int irq, void *_esw)
869 +{
870 + struct rt305x_esw *esw = (struct rt305x_esw *) _esw;
871 + u32 status;
872 +
873 + status = esw_r32(esw, RT305X_ESW_REG_ISR);
874 + if (status & RT305X_ESW_PORT_ST_CHG) {
875 + u32 link = esw_r32(esw, RT305X_ESW_REG_POA);
876 + link >>= RT305X_ESW_POA_LINK_SHIFT;
877 + link &= RT305X_ESW_POA_LINK_MASK;
878 + dev_info(esw->dev, "link changed 0x%02X\n", link);
879 + }
880 + esw_w32(esw, status, RT305X_ESW_REG_ISR);
881 +
882 + return IRQ_HANDLED;
883 +}
884 +
885 +static int esw_apply_config(struct switch_dev *dev)
886 +{
887 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
888 + int i;
889 + u8 disable = 0;
890 + u8 doubletag = 0;
891 + u8 en_vlan = 0;
892 + u8 untag = 0;
893 +
894 + for (i = 0; i < RT305X_ESW_NUM_VLANS; i++) {
895 + u32 vid, vmsc;
896 + if (esw->global_vlan_enable) {
897 + vid = esw->vlans[i].vid;
898 + vmsc = esw->vlans[i].ports;
899 + } else {
900 + vid = RT305X_ESW_VLAN_NONE;
901 + vmsc = RT305X_ESW_PORTS_NONE;
902 + }
903 + esw_set_vlan_id(esw, i, vid);
904 + esw_set_vmsc(esw, i, vmsc);
905 + }
906 +
907 + for (i = 0; i < RT305X_ESW_NUM_PORTS; i++) {
908 + u32 pvid;
909 + disable |= esw->ports[i].disable << i;
910 + if (esw->global_vlan_enable) {
911 + doubletag |= esw->ports[i].doubletag << i;
912 + en_vlan |= 1 << i;
913 + untag |= esw->ports[i].untag << i;
914 + pvid = esw->ports[i].pvid;
915 + } else {
916 + int x = esw->alt_vlan_disable ? 0 : 1;
917 + doubletag |= x << i;
918 + en_vlan |= x << i;
919 + untag |= x << i;
920 + pvid = 0;
921 + }
922 + esw_set_pvid(esw, i, pvid);
923 + if (i < RT305X_ESW_NUM_LEDS)
924 + esw_w32(esw, esw->ports[i].led,
925 + RT305X_ESW_REG_P0LED + 4*i);
926 + }
927 +
928 + esw_set_gsc(esw);
929 + esw_set_port_disable(esw, disable);
930 + esw_rmw(esw, RT305X_ESW_REG_SGC2,
931 + (RT305X_ESW_SGC2_DOUBLE_TAG_M <<
932 + RT305X_ESW_SGC2_DOUBLE_TAG_S),
933 + doubletag << RT305X_ESW_SGC2_DOUBLE_TAG_S);
934 + esw_rmw(esw, RT305X_ESW_REG_PFC1,
935 + RT305X_ESW_PFC1_EN_VLAN_M << RT305X_ESW_PFC1_EN_VLAN_S,
936 + en_vlan << RT305X_ESW_PFC1_EN_VLAN_S);
937 + esw_rmw(esw, RT305X_ESW_REG_POC2,
938 + RT305X_ESW_POC2_UNTAG_EN_M << RT305X_ESW_POC2_UNTAG_EN_S,
939 + untag << RT305X_ESW_POC2_UNTAG_EN_S);
940 +
941 + if (!esw->global_vlan_enable) {
942 + /*
943 + * Still need to put all ports into vlan 0 or they'll be
944 + * isolated.
945 + * NOTE: vlan 0 is special, no vlan tag is prepended
946 + */
947 + esw_set_vlan_id(esw, 0, 0);
948 + esw_set_vmsc(esw, 0, RT305X_ESW_PORTS_ALL);
949 + }
950 +
951 + return 0;
952 +}
953 +
954 +static int esw_reset_switch(struct switch_dev *dev)
955 +{
956 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
957 +
958 + esw->global_vlan_enable = 0;
959 + memset(esw->ports, 0, sizeof(esw->ports));
960 + memset(esw->vlans, 0, sizeof(esw->vlans));
961 + esw_hw_init(esw);
962 +
963 + return 0;
964 +}
965 +
966 +static int esw_get_vlan_enable(struct switch_dev *dev,
967 + const struct switch_attr *attr,
968 + struct switch_val *val)
969 +{
970 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
971 +
972 + val->value.i = esw->global_vlan_enable;
973 +
974 + return 0;
975 +}
976 +
977 +static int esw_set_vlan_enable(struct switch_dev *dev,
978 + const struct switch_attr *attr,
979 + struct switch_val *val)
980 +{
981 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
982 +
983 + esw->global_vlan_enable = val->value.i != 0;
984 +
985 + return 0;
986 +}
987 +
988 +static int esw_get_alt_vlan_disable(struct switch_dev *dev,
989 + const struct switch_attr *attr,
990 + struct switch_val *val)
991 +{
992 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
993 +
994 + val->value.i = esw->alt_vlan_disable;
995 +
996 + return 0;
997 +}
998 +
999 +static int esw_set_alt_vlan_disable(struct switch_dev *dev,
1000 + const struct switch_attr *attr,
1001 + struct switch_val *val)
1002 +{
1003 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1004 +
1005 + esw->alt_vlan_disable = val->value.i != 0;
1006 +
1007 + return 0;
1008 +}
1009 +
1010 +static int
1011 +rt305x_esw_set_bc_status(struct switch_dev *dev,
1012 + const struct switch_attr *attr,
1013 + struct switch_val *val)
1014 +{
1015 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1016 +
1017 + esw->bc_storm_protect = val->value.i & RT305X_ESW_GSC_BC_STROM_MASK;
1018 +
1019 + return 0;
1020 +}
1021 +
1022 +static int
1023 +rt305x_esw_get_bc_status(struct switch_dev *dev,
1024 + const struct switch_attr *attr,
1025 + struct switch_val *val)
1026 +{
1027 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1028 +
1029 + val->value.i = esw->bc_storm_protect;
1030 +
1031 + return 0;
1032 +}
1033 +
1034 +static int
1035 +rt305x_esw_set_led_freq(struct switch_dev *dev,
1036 + const struct switch_attr *attr,
1037 + struct switch_val *val)
1038 +{
1039 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1040 +
1041 + esw->led_frequency = val->value.i & RT305X_ESW_GSC_LED_FREQ_MASK;
1042 +
1043 + return 0;
1044 +}
1045 +
1046 +static int
1047 +rt305x_esw_get_led_freq(struct switch_dev *dev,
1048 + const struct switch_attr *attr,
1049 + struct switch_val *val)
1050 +{
1051 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1052 +
1053 + val->value.i = esw->led_frequency;
1054 +
1055 + return 0;
1056 +}
1057 +
1058 +static int esw_get_port_link(struct switch_dev *dev,
1059 + int port,
1060 + struct switch_port_link *link)
1061 +{
1062 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1063 + u32 speed, poa;
1064 +
1065 + if (port < 0 || port >= RT305X_ESW_NUM_PORTS)
1066 + return -EINVAL;
1067 +
1068 + poa = esw_r32(esw, RT305X_ESW_REG_POA) >> port;
1069 +
1070 + link->link = (poa >> RT305X_ESW_LINK_S) & 1;
1071 + link->duplex = (poa >> RT305X_ESW_DUPLEX_S) & 1;
1072 + if (port < RT305X_ESW_NUM_LEDS) {
1073 + speed = (poa >> RT305X_ESW_SPD_S) & 1;
1074 + } else {
1075 + if (port == RT305X_ESW_NUM_PORTS - 1)
1076 + poa >>= 1;
1077 + speed = (poa >> RT305X_ESW_SPD_S) & 3;
1078 + }
1079 + switch (speed) {
1080 + case 0:
1081 + link->speed = SWITCH_PORT_SPEED_10;
1082 + break;
1083 + case 1:
1084 + link->speed = SWITCH_PORT_SPEED_100;
1085 + break;
1086 + case 2:
1087 + case 3: /* forced gige speed can be 2 or 3 */
1088 + link->speed = SWITCH_PORT_SPEED_1000;
1089 + break;
1090 + default:
1091 + link->speed = SWITCH_PORT_SPEED_UNKNOWN;
1092 + break;
1093 + }
1094 +
1095 + return 0;
1096 +}
1097 +
1098 +static int esw_get_port_bool(struct switch_dev *dev,
1099 + const struct switch_attr *attr,
1100 + struct switch_val *val)
1101 +{
1102 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1103 + int idx = val->port_vlan;
1104 + u32 x, reg, shift;
1105 +
1106 + if (idx < 0 || idx >= RT305X_ESW_NUM_PORTS)
1107 + return -EINVAL;
1108 +
1109 + switch (attr->id) {
1110 + case RT305X_ESW_ATTR_PORT_DISABLE:
1111 + reg = RT305X_ESW_REG_POC0;
1112 + shift = RT305X_ESW_POC0_DIS_PORT_S;
1113 + break;
1114 + case RT305X_ESW_ATTR_PORT_DOUBLETAG:
1115 + reg = RT305X_ESW_REG_SGC2;
1116 + shift = RT305X_ESW_SGC2_DOUBLE_TAG_S;
1117 + break;
1118 + case RT305X_ESW_ATTR_PORT_UNTAG:
1119 + reg = RT305X_ESW_REG_POC2;
1120 + shift = RT305X_ESW_POC2_UNTAG_EN_S;
1121 + break;
1122 + case RT305X_ESW_ATTR_PORT_LAN:
1123 + reg = RT305X_ESW_REG_SGC2;
1124 + shift = RT305X_ESW_SGC2_LAN_PMAP_S;
1125 + if (idx >= RT305X_ESW_NUM_LANWAN)
1126 + return -EINVAL;
1127 + break;
1128 + default:
1129 + return -EINVAL;
1130 + }
1131 +
1132 + x = esw_r32(esw, reg);
1133 + val->value.i = (x >> (idx + shift)) & 1;
1134 +
1135 + return 0;
1136 +}
1137 +
1138 +static int esw_set_port_bool(struct switch_dev *dev,
1139 + const struct switch_attr *attr,
1140 + struct switch_val *val)
1141 +{
1142 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1143 + int idx = val->port_vlan;
1144 +
1145 + if (idx < 0 || idx >= RT305X_ESW_NUM_PORTS ||
1146 + val->value.i < 0 || val->value.i > 1)
1147 + return -EINVAL;
1148 +
1149 + switch (attr->id) {
1150 + case RT305X_ESW_ATTR_PORT_DISABLE:
1151 + esw->ports[idx].disable = val->value.i;
1152 + break;
1153 + case RT305X_ESW_ATTR_PORT_DOUBLETAG:
1154 + esw->ports[idx].doubletag = val->value.i;
1155 + break;
1156 + case RT305X_ESW_ATTR_PORT_UNTAG:
1157 + esw->ports[idx].untag = val->value.i;
1158 + break;
1159 + default:
1160 + return -EINVAL;
1161 + }
1162 +
1163 + return 0;
1164 +}
1165 +
1166 +static int esw_get_port_recv_badgood(struct switch_dev *dev,
1167 + const struct switch_attr *attr,
1168 + struct switch_val *val)
1169 +{
1170 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1171 + int idx = val->port_vlan;
1172 + int shift = attr->id == RT305X_ESW_ATTR_PORT_RECV_GOOD ? 0 : 16;
1173 + u32 reg;
1174 +
1175 + if (idx < 0 || idx >= RT305X_ESW_NUM_LANWAN)
1176 + return -EINVAL;
1177 + reg = esw_r32(esw, RT305X_ESW_REG_PXPC(idx));
1178 + val->value.i = (reg >> shift) & 0xffff;
1179 +
1180 + return 0;
1181 +}
1182 +
1183 +static int
1184 +esw_get_port_tr_badgood(struct switch_dev *dev,
1185 + const struct switch_attr *attr,
1186 + struct switch_val *val)
1187 +{
1188 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1189 +
1190 + int idx = val->port_vlan;
1191 + int shift = attr->id == RT5350_ESW_ATTR_PORT_TR_GOOD ? 0 : 16;
1192 + u32 reg;
1193 +
1194 + if (!soc_is_rt5350())
1195 + return -EINVAL;
1196 +
1197 + if (idx < 0 || idx >= RT305X_ESW_NUM_LANWAN)
1198 + return -EINVAL;
1199 +
1200 + reg = esw_r32(esw, RT5350_ESW_REG_PXTPC(idx));
1201 + val->value.i = (reg >> shift) & 0xffff;
1202 +
1203 + return 0;
1204 +}
1205 +
1206 +static int esw_get_port_led(struct switch_dev *dev,
1207 + const struct switch_attr *attr,
1208 + struct switch_val *val)
1209 +{
1210 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1211 + int idx = val->port_vlan;
1212 +
1213 + if (idx < 0 || idx >= RT305X_ESW_NUM_PORTS ||
1214 + idx >= RT305X_ESW_NUM_LEDS)
1215 + return -EINVAL;
1216 +
1217 + val->value.i = esw_r32(esw, RT305X_ESW_REG_P0LED + 4*idx);
1218 +
1219 + return 0;
1220 +}
1221 +
1222 +static int esw_set_port_led(struct switch_dev *dev,
1223 + const struct switch_attr *attr,
1224 + struct switch_val *val)
1225 +{
1226 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1227 + int idx = val->port_vlan;
1228 +
1229 + if (idx < 0 || idx >= RT305X_ESW_NUM_LEDS)
1230 + return -EINVAL;
1231 +
1232 + esw->ports[idx].led = val->value.i;
1233 +
1234 + return 0;
1235 +}
1236 +
1237 +static int esw_get_port_pvid(struct switch_dev *dev, int port, int *val)
1238 +{
1239 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1240 +
1241 + if (port >= RT305X_ESW_NUM_PORTS)
1242 + return -EINVAL;
1243 +
1244 + *val = esw_get_pvid(esw, port);
1245 +
1246 + return 0;
1247 +}
1248 +
1249 +static int esw_set_port_pvid(struct switch_dev *dev, int port, int val)
1250 +{
1251 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1252 +
1253 + if (port >= RT305X_ESW_NUM_PORTS)
1254 + return -EINVAL;
1255 +
1256 + esw->ports[port].pvid = val;
1257 +
1258 + return 0;
1259 +}
1260 +
1261 +static int esw_get_vlan_ports(struct switch_dev *dev, struct switch_val *val)
1262 +{
1263 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1264 + u32 vmsc, poc2;
1265 + int vlan_idx = -1;
1266 + int i;
1267 +
1268 + val->len = 0;
1269 +
1270 + if (val->port_vlan < 0 || val->port_vlan >= RT305X_ESW_NUM_VIDS)
1271 + return -EINVAL;
1272 +
1273 + /* valid vlan? */
1274 + for (i = 0; i < RT305X_ESW_NUM_VLANS; i++) {
1275 + if (esw_get_vlan_id(esw, i) == val->port_vlan &&
1276 + esw_get_vmsc(esw, i) != RT305X_ESW_PORTS_NONE) {
1277 + vlan_idx = i;
1278 + break;
1279 + }
1280 + }
1281 +
1282 + if (vlan_idx == -1)
1283 + return -EINVAL;
1284 +
1285 + vmsc = esw_get_vmsc(esw, vlan_idx);
1286 + poc2 = esw_r32(esw, RT305X_ESW_REG_POC2);
1287 +
1288 + for (i = 0; i < RT305X_ESW_NUM_PORTS; i++) {
1289 + struct switch_port *p;
1290 + int port_mask = 1 << i;
1291 +
1292 + if (!(vmsc & port_mask))
1293 + continue;
1294 +
1295 + p = &val->value.ports[val->len++];
1296 + p->id = i;
1297 + if (poc2 & (port_mask << RT305X_ESW_POC2_UNTAG_EN_S))
1298 + p->flags = 0;
1299 + else
1300 + p->flags = 1 << SWITCH_PORT_FLAG_TAGGED;
1301 + }
1302 +
1303 + return 0;
1304 +}
1305 +
1306 +static int esw_set_vlan_ports(struct switch_dev *dev, struct switch_val *val)
1307 +{
1308 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1309 + int ports;
1310 + int vlan_idx = -1;
1311 + int i;
1312 +
1313 + if (val->port_vlan < 0 || val->port_vlan >= RT305X_ESW_NUM_VIDS ||
1314 + val->len > RT305X_ESW_NUM_PORTS)
1315 + return -EINVAL;
1316 +
1317 + /* one of the already defined vlans? */
1318 + for (i = 0; i < RT305X_ESW_NUM_VLANS; i++) {
1319 + if (esw->vlans[i].vid == val->port_vlan &&
1320 + esw->vlans[i].ports != RT305X_ESW_PORTS_NONE) {
1321 + vlan_idx = i;
1322 + break;
1323 + }
1324 + }
1325 +
1326 + /* select a free slot */
1327 + for (i = 0; vlan_idx == -1 && i < RT305X_ESW_NUM_VLANS; i++) {
1328 + if (esw->vlans[i].ports == RT305X_ESW_PORTS_NONE)
1329 + vlan_idx = i;
1330 + }
1331 +
1332 + /* bail if all slots are in use */
1333 + if (vlan_idx == -1)
1334 + return -EINVAL;
1335 +
1336 + ports = RT305X_ESW_PORTS_NONE;
1337 + for (i = 0; i < val->len; i++) {
1338 + struct switch_port *p = &val->value.ports[i];
1339 + int port_mask = 1 << p->id;
1340 + bool untagged = !(p->flags & (1 << SWITCH_PORT_FLAG_TAGGED));
1341 +
1342 + if (p->id >= RT305X_ESW_NUM_PORTS)
1343 + return -EINVAL;
1344 +
1345 + ports |= port_mask;
1346 + esw->ports[p->id].untag = untagged;
1347 + }
1348 + esw->vlans[vlan_idx].ports = ports;
1349 + if (ports == RT305X_ESW_PORTS_NONE)
1350 + esw->vlans[vlan_idx].vid = RT305X_ESW_VLAN_NONE;
1351 + else
1352 + esw->vlans[vlan_idx].vid = val->port_vlan;
1353 +
1354 + return 0;
1355 +}
1356 +
1357 +static const struct switch_attr esw_global[] = {
1358 + {
1359 + .type = SWITCH_TYPE_INT,
1360 + .name = "enable_vlan",
1361 + .description = "VLAN mode (1:enabled)",
1362 + .max = 1,
1363 + .id = RT305X_ESW_ATTR_ENABLE_VLAN,
1364 + .get = esw_get_vlan_enable,
1365 + .set = esw_set_vlan_enable,
1366 + },
1367 + {
1368 + .type = SWITCH_TYPE_INT,
1369 + .name = "alternate_vlan_disable",
1370 + .description = "Use en_vlan instead of doubletag to disable"
1371 + " VLAN mode",
1372 + .max = 1,
1373 + .id = RT305X_ESW_ATTR_ALT_VLAN_DISABLE,
1374 + .get = esw_get_alt_vlan_disable,
1375 + .set = esw_set_alt_vlan_disable,
1376 + },
1377 + {
1378 + .type = SWITCH_TYPE_INT,
1379 + .name = "bc_storm_protect",
1380 + .description = "Global broadcast storm protection (0:Disable, 1:64 blocks, 2:96 blocks, 3:128 blocks)",
1381 + .max = 3,
1382 + .id = RT305X_ESW_ATTR_BC_STATUS,
1383 + .get = rt305x_esw_get_bc_status,
1384 + .set = rt305x_esw_set_bc_status,
1385 + },
1386 + {
1387 + .type = SWITCH_TYPE_INT,
1388 + .name = "led_frequency",
1389 + .description = "LED Flash frequency (0:30mS, 1:60mS, 2:240mS, 3:480mS)",
1390 + .max = 3,
1391 + .id = RT305X_ESW_ATTR_LED_FREQ,
1392 + .get = rt305x_esw_get_led_freq,
1393 + .set = rt305x_esw_set_led_freq,
1394 + }
1395 +};
1396 +
1397 +static const struct switch_attr esw_port[] = {
1398 + {
1399 + .type = SWITCH_TYPE_INT,
1400 + .name = "disable",
1401 + .description = "Port state (1:disabled)",
1402 + .max = 1,
1403 + .id = RT305X_ESW_ATTR_PORT_DISABLE,
1404 + .get = esw_get_port_bool,
1405 + .set = esw_set_port_bool,
1406 + },
1407 + {
1408 + .type = SWITCH_TYPE_INT,
1409 + .name = "doubletag",
1410 + .description = "Double tagging for incoming vlan packets "
1411 + "(1:enabled)",
1412 + .max = 1,
1413 + .id = RT305X_ESW_ATTR_PORT_DOUBLETAG,
1414 + .get = esw_get_port_bool,
1415 + .set = esw_set_port_bool,
1416 + },
1417 + {
1418 + .type = SWITCH_TYPE_INT,
1419 + .name = "untag",
1420 + .description = "Untag (1:strip outgoing vlan tag)",
1421 + .max = 1,
1422 + .id = RT305X_ESW_ATTR_PORT_UNTAG,
1423 + .get = esw_get_port_bool,
1424 + .set = esw_set_port_bool,
1425 + },
1426 + {
1427 + .type = SWITCH_TYPE_INT,
1428 + .name = "led",
1429 + .description = "LED mode (0:link, 1:100m, 2:duplex, 3:activity,"
1430 + " 4:collision, 5:linkact, 6:duplcoll, 7:10mact,"
1431 + " 8:100mact, 10:blink, 11:off, 12:on)",
1432 + .max = 15,
1433 + .id = RT305X_ESW_ATTR_PORT_LED,
1434 + .get = esw_get_port_led,
1435 + .set = esw_set_port_led,
1436 + },
1437 + {
1438 + .type = SWITCH_TYPE_INT,
1439 + .name = "lan",
1440 + .description = "HW port group (0:wan, 1:lan)",
1441 + .max = 1,
1442 + .id = RT305X_ESW_ATTR_PORT_LAN,
1443 + .get = esw_get_port_bool,
1444 + },
1445 + {
1446 + .type = SWITCH_TYPE_INT,
1447 + .name = "recv_bad",
1448 + .description = "Receive bad packet counter",
1449 + .id = RT305X_ESW_ATTR_PORT_RECV_BAD,
1450 + .get = esw_get_port_recv_badgood,
1451 + },
1452 + {
1453 + .type = SWITCH_TYPE_INT,
1454 + .name = "recv_good",
1455 + .description = "Receive good packet counter",
1456 + .id = RT305X_ESW_ATTR_PORT_RECV_GOOD,
1457 + .get = esw_get_port_recv_badgood,
1458 + },
1459 + {
1460 + .type = SWITCH_TYPE_INT,
1461 + .name = "tr_bad",
1462 +
1463 + .description = "Transmit bad packet counter. rt5350 only",
1464 + .id = RT5350_ESW_ATTR_PORT_TR_BAD,
1465 + .get = esw_get_port_tr_badgood,
1466 + },
1467 + {
1468 + .type = SWITCH_TYPE_INT,
1469 + .name = "tr_good",
1470 +
1471 + .description = "Transmit good packet counter. rt5350 only",
1472 + .id = RT5350_ESW_ATTR_PORT_TR_GOOD,
1473 + .get = esw_get_port_tr_badgood,
1474 + },
1475 +};
1476 +
1477 +static const struct switch_attr esw_vlan[] = {
1478 +};
1479 +
1480 +static const struct switch_dev_ops esw_ops = {
1481 + .attr_global = {
1482 + .attr = esw_global,
1483 + .n_attr = ARRAY_SIZE(esw_global),
1484 + },
1485 + .attr_port = {
1486 + .attr = esw_port,
1487 + .n_attr = ARRAY_SIZE(esw_port),
1488 + },
1489 + .attr_vlan = {
1490 + .attr = esw_vlan,
1491 + .n_attr = ARRAY_SIZE(esw_vlan),
1492 + },
1493 + .get_vlan_ports = esw_get_vlan_ports,
1494 + .set_vlan_ports = esw_set_vlan_ports,
1495 + .get_port_pvid = esw_get_port_pvid,
1496 + .set_port_pvid = esw_set_port_pvid,
1497 + .get_port_link = esw_get_port_link,
1498 + .apply_config = esw_apply_config,
1499 + .reset_switch = esw_reset_switch,
1500 +};
1501 +
1502 +static struct rt305x_esw_platform_data rt3050_esw_data = {
1503 + /* All ports are LAN ports. */
1504 + .vlan_config = RT305X_ESW_VLAN_CONFIG_NONE,
1505 + .reg_initval_fct2 = 0x00d6500c,
1506 + /*
1507 + * ext phy base addr 31, enable port 5 polling, rx/tx clock skew 1,
1508 + * turbo mii off, rgmi 3.3v off
1509 + * port5: disabled
1510 + * port6: enabled, gige, full-duplex, rx/tx-flow-control
1511 + */
1512 + .reg_initval_fpa2 = 0x3f502b28,
1513 +};
1514 +
1515 +static const struct of_device_id ralink_esw_match[] = {
1516 + { .compatible = "ralink,rt3050-esw", .data = &rt3050_esw_data },
1517 + {},
1518 +};
1519 +MODULE_DEVICE_TABLE(of, ralink_esw_match);
1520 +
1521 +static int esw_probe(struct platform_device *pdev)
1522 +{
1523 + struct device_node *np = pdev->dev.of_node;
1524 + const struct rt305x_esw_platform_data *pdata;
1525 + const __be32 *port_map, *reg_init;
1526 + struct rt305x_esw *esw;
1527 + struct switch_dev *swdev;
1528 + struct resource *res, *irq;
1529 + int err;
1530 +
1531 + pdata = pdev->dev.platform_data;
1532 + if (!pdata) {
1533 + const struct of_device_id *match;
1534 + match = of_match_device(ralink_esw_match, &pdev->dev);
1535 + if (match)
1536 + pdata = (struct rt305x_esw_platform_data *) match->data;
1537 + }
1538 + if (!pdata)
1539 + return -EINVAL;
1540 +
1541 + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1542 + if (!res) {
1543 + dev_err(&pdev->dev, "no memory resource found\n");
1544 + return -ENOMEM;
1545 + }
1546 +
1547 + irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1548 + if (!irq) {
1549 + dev_err(&pdev->dev, "no irq resource found\n");
1550 + return -ENOMEM;
1551 + }
1552 +
1553 + esw = kzalloc(sizeof(struct rt305x_esw), GFP_KERNEL);
1554 + if (!esw) {
1555 + dev_err(&pdev->dev, "no memory for private data\n");
1556 + return -ENOMEM;
1557 + }
1558 +
1559 + esw->dev = &pdev->dev;
1560 + esw->irq = irq->start;
1561 + esw->base = ioremap(res->start, resource_size(res));
1562 + if (!esw->base) {
1563 + dev_err(&pdev->dev, "ioremap failed\n");
1564 + err = -ENOMEM;
1565 + goto free_esw;
1566 + }
1567 +
1568 + port_map = of_get_property(np, "ralink,portmap", NULL);
1569 + if (port_map)
1570 + esw->port_map = be32_to_cpu(*port_map);
1571 +
1572 + reg_init = of_get_property(np, "ralink,fct2", NULL);
1573 + if (reg_init)
1574 + esw->reg_initval_fct2 = be32_to_cpu(*reg_init);
1575 +
1576 + reg_init = of_get_property(np, "ralink,fpa2", NULL);
1577 + if (reg_init)
1578 + esw->reg_initval_fpa2 = be32_to_cpu(*reg_init);
1579 +
1580 + reg_init = of_get_property(np, "ralink,led_polarity", NULL);
1581 + if (reg_init)
1582 + esw->reg_led_polarity = be32_to_cpu(*reg_init);
1583 +
1584 + swdev = &esw->swdev;
1585 + swdev->of_node = pdev->dev.of_node;
1586 + swdev->name = "rt305x-esw";
1587 + swdev->alias = "rt305x";
1588 + swdev->cpu_port = RT305X_ESW_PORT6;
1589 + swdev->ports = RT305X_ESW_NUM_PORTS;
1590 + swdev->vlans = RT305X_ESW_NUM_VIDS;
1591 + swdev->ops = &esw_ops;
1592 +
1593 + err = register_switch(swdev, NULL);
1594 + if (err < 0) {
1595 + dev_err(&pdev->dev, "register_switch failed\n");
1596 + goto unmap_base;
1597 + }
1598 +
1599 + platform_set_drvdata(pdev, esw);
1600 +
1601 + esw->pdata = pdata;
1602 + spin_lock_init(&esw->reg_rw_lock);
1603 +
1604 + esw_hw_init(esw);
1605 +
1606 + esw_w32(esw, RT305X_ESW_PORT_ST_CHG, RT305X_ESW_REG_ISR);
1607 + esw_w32(esw, ~RT305X_ESW_PORT_ST_CHG, RT305X_ESW_REG_IMR);
1608 + request_irq(esw->irq, esw_interrupt, 0, "esw", esw);
1609 +
1610 + return 0;
1611 +
1612 +unmap_base:
1613 + iounmap(esw->base);
1614 +free_esw:
1615 + kfree(esw);
1616 + return err;
1617 +}
1618 +
1619 +static int esw_remove(struct platform_device *pdev)
1620 +{
1621 + struct rt305x_esw *esw;
1622 +
1623 + esw = platform_get_drvdata(pdev);
1624 + if (esw) {
1625 + unregister_switch(&esw->swdev);
1626 + platform_set_drvdata(pdev, NULL);
1627 + iounmap(esw->base);
1628 + kfree(esw);
1629 + }
1630 +
1631 + return 0;
1632 +}
1633 +
1634 +static struct platform_driver esw_driver = {
1635 + .probe = esw_probe,
1636 + .remove = esw_remove,
1637 + .driver = {
1638 + .name = "rt305x-esw",
1639 + .owner = THIS_MODULE,
1640 + .of_match_table = ralink_esw_match,
1641 + },
1642 +};
1643 +
1644 +int __init rtesw_init(void)
1645 +{
1646 + return platform_driver_register(&esw_driver);
1647 +}
1648 +
1649 +void rtesw_exit(void)
1650 +{
1651 + platform_driver_unregister(&esw_driver);
1652 +}
1653 diff --git a/drivers/net/ethernet/ralink/esw_rt3052.h b/drivers/net/ethernet/ralink/esw_rt3052.h
1654 new file mode 100644
1655 index 0000000..2ced3dff
1656 --- /dev/null
1657 +++ b/drivers/net/ethernet/ralink/esw_rt3052.h
1658 @@ -0,0 +1,32 @@
1659 +/*
1660 + * This program is free software; you can redistribute it and/or modify
1661 + * it under the terms of the GNU General Public License as published by
1662 + * the Free Software Foundation; version 2 of the License
1663 + *
1664 + * This program is distributed in the hope that it will be useful,
1665 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
1666 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1667 + * GNU General Public License for more details.
1668 + *
1669 + * You should have received a copy of the GNU General Public License
1670 + * along with this program; if not, write to the Free Software
1671 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
1672 + *
1673 + * Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
1674 + */
1675 +
1676 +#ifndef _RALINK_ESW_RT3052_H__
1677 +#define _RALINK_ESW_RT3052_H__
1678 +
1679 +#ifdef CONFIG_NET_RALINK_ESW_RT3052
1680 +
1681 +int __init rtesw_init(void);
1682 +void rtesw_exit(void);
1683 +
1684 +#else
1685 +
1686 +static inline int __init rtesw_init(void) { return 0; }
1687 +static inline void rtesw_exit(void) { }
1688 +
1689 +#endif
1690 +#endif
1691 diff --git a/drivers/net/ethernet/ralink/gsw_mt7620a.c b/drivers/net/ethernet/ralink/gsw_mt7620a.c
1692 new file mode 100644
1693 index 0000000..70f81e3
1694 --- /dev/null
1695 +++ b/drivers/net/ethernet/ralink/gsw_mt7620a.c
1696 @@ -0,0 +1,566 @@
1697 +/*
1698 + * This program is free software; you can redistribute it and/or modify
1699 + * it under the terms of the GNU General Public License as published by
1700 + * the Free Software Foundation; version 2 of the License
1701 + *
1702 + * This program is distributed in the hope that it will be useful,
1703 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
1704 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1705 + * GNU General Public License for more details.
1706 + *
1707 + * You should have received a copy of the GNU General Public License
1708 + * along with this program; if not, write to the Free Software
1709 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
1710 + *
1711 + * Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
1712 + */
1713 +
1714 +#include <linux/module.h>
1715 +#include <linux/kernel.h>
1716 +#include <linux/types.h>
1717 +#include <linux/dma-mapping.h>
1718 +#include <linux/init.h>
1719 +#include <linux/skbuff.h>
1720 +#include <linux/etherdevice.h>
1721 +#include <linux/ethtool.h>
1722 +#include <linux/platform_device.h>
1723 +#include <linux/of_device.h>
1724 +#include <linux/clk.h>
1725 +#include <linux/of_net.h>
1726 +#include <linux/of_mdio.h>
1727 +#include <linux/of_irq.h>
1728 +#include <linux/of_address.h>
1729 +#include <linux/switch.h>
1730 +
1731 +#include <asm/mach-ralink/ralink_regs.h>
1732 +
1733 +#include "ralink_soc_eth.h"
1734 +
1735 +#include <linux/ioport.h>
1736 +#include <linux/switch.h>
1737 +#include <linux/mii.h>
1738 +
1739 +#include <ralink_regs.h>
1740 +#include <asm/mach-ralink/mt7620.h>
1741 +
1742 +#include "ralink_soc_eth.h"
1743 +#include "gsw_mt7620a.h"
1744 +#include "mt7530.h"
1745 +#include "mdio.h"
1746 +
1747 +#define GSW_REG_PHY_TIMEOUT (5 * HZ)
1748 +
1749 +#define MT7620A_GSW_REG_PIAC 0x7004
1750 +
1751 +#define GSW_NUM_VLANS 16
1752 +#define GSW_NUM_VIDS 4096
1753 +#define GSW_NUM_PORTS 7
1754 +#define GSW_PORT6 6
1755 +
1756 +#define GSW_MDIO_ACCESS BIT(31)
1757 +#define GSW_MDIO_READ BIT(19)
1758 +#define GSW_MDIO_WRITE BIT(18)
1759 +#define GSW_MDIO_START BIT(16)
1760 +#define GSW_MDIO_ADDR_SHIFT 20
1761 +#define GSW_MDIO_REG_SHIFT 25
1762 +
1763 +#define GSW_REG_PORT_PMCR(x) (0x3000 + (x * 0x100))
1764 +#define GSW_REG_PORT_STATUS(x) (0x3008 + (x * 0x100))
1765 +#define GSW_REG_SMACCR0 0x3fE4
1766 +#define GSW_REG_SMACCR1 0x3fE8
1767 +#define GSW_REG_CKGCR 0x3ff0
1768 +
1769 +#define GSW_REG_IMR 0x7008
1770 +#define GSW_REG_ISR 0x700c
1771 +
1772 +#define SYSC_REG_CFG1 0x14
1773 +
1774 +#define PORT_IRQ_ST_CHG 0x7f
1775 +
1776 +#define SYSCFG1 0x14
1777 +
1778 +#define ESW_PHY_POLLING 0x7000
1779 +
1780 +#define PMCR_IPG BIT(18)
1781 +#define PMCR_MAC_MODE BIT(16)
1782 +#define PMCR_FORCE BIT(15)
1783 +#define PMCR_TX_EN BIT(14)
1784 +#define PMCR_RX_EN BIT(13)
1785 +#define PMCR_BACKOFF BIT(9)
1786 +#define PMCR_BACKPRES BIT(8)
1787 +#define PMCR_RX_FC BIT(5)
1788 +#define PMCR_TX_FC BIT(4)
1789 +#define PMCR_SPEED(_x) (_x << 2)
1790 +#define PMCR_DUPLEX BIT(1)
1791 +#define PMCR_LINK BIT(0)
1792 +
1793 +#define PHY_AN_EN BIT(31)
1794 +#define PHY_PRE_EN BIT(30)
1795 +#define PMY_MDC_CONF(_x) ((_x & 0x3f) << 24)
1796 +
1797 +enum {
1798 + /* Global attributes. */
1799 + GSW_ATTR_ENABLE_VLAN,
1800 + /* Port attributes. */
1801 + GSW_ATTR_PORT_UNTAG,
1802 +};
1803 +
1804 +enum {
1805 + PORT4_EPHY = 0,
1806 + PORT4_EXT,
1807 +};
1808 +
1809 +struct mt7620_gsw {
1810 + struct device *dev;
1811 + void __iomem *base;
1812 + int irq;
1813 + int port4;
1814 + long unsigned int autopoll;
1815 +};
1816 +
1817 +static inline void gsw_w32(struct mt7620_gsw *gsw, u32 val, unsigned reg)
1818 +{
1819 + iowrite32(val, gsw->base + reg);
1820 +}
1821 +
1822 +static inline u32 gsw_r32(struct mt7620_gsw *gsw, unsigned reg)
1823 +{
1824 + return ioread32(gsw->base + reg);
1825 +}
1826 +
1827 +static int mt7620_mii_busy_wait(struct mt7620_gsw *gsw)
1828 +{
1829 + unsigned long t_start = jiffies;
1830 +
1831 + while (1) {
1832 + if (!(gsw_r32(gsw, MT7620A_GSW_REG_PIAC) & GSW_MDIO_ACCESS))
1833 + return 0;
1834 + if (time_after(jiffies, t_start + GSW_REG_PHY_TIMEOUT)) {
1835 + break;
1836 + }
1837 + }
1838 +
1839 + printk(KERN_ERR "mdio: MDIO timeout\n");
1840 + return -1;
1841 +}
1842 +
1843 +static u32 _mt7620_mii_write(struct mt7620_gsw *gsw, u32 phy_addr, u32 phy_register,
1844 + u32 write_data)
1845 +{
1846 + if (mt7620_mii_busy_wait(gsw))
1847 + return -1;
1848 +
1849 + write_data &= 0xffff;
1850 +
1851 + gsw_w32(gsw, GSW_MDIO_ACCESS | GSW_MDIO_START | GSW_MDIO_WRITE |
1852 + (phy_register << GSW_MDIO_REG_SHIFT) |
1853 + (phy_addr << GSW_MDIO_ADDR_SHIFT) | write_data,
1854 + MT7620A_GSW_REG_PIAC);
1855 +
1856 + if (mt7620_mii_busy_wait(gsw))
1857 + return -1;
1858 +
1859 + return 0;
1860 +}
1861 +
1862 +static u32 _mt7620_mii_read(struct mt7620_gsw *gsw, int phy_addr, int phy_reg)
1863 +{
1864 + u32 d;
1865 +
1866 + if (mt7620_mii_busy_wait(gsw))
1867 + return 0xffff;
1868 +
1869 + gsw_w32(gsw, GSW_MDIO_ACCESS | GSW_MDIO_START | GSW_MDIO_READ |
1870 + (phy_reg << GSW_MDIO_REG_SHIFT) |
1871 + (phy_addr << GSW_MDIO_ADDR_SHIFT),
1872 + MT7620A_GSW_REG_PIAC);
1873 +
1874 + if (mt7620_mii_busy_wait(gsw))
1875 + return 0xffff;
1876 +
1877 + d = gsw_r32(gsw, MT7620A_GSW_REG_PIAC) & 0xffff;
1878 +
1879 + return d;
1880 +}
1881 +
1882 +int mt7620_mdio_write(struct mii_bus *bus, int phy_addr, int phy_reg, u16 val)
1883 +{
1884 + struct fe_priv *priv = bus->priv;
1885 + struct mt7620_gsw *gsw = (struct mt7620_gsw *) priv->soc->swpriv;
1886 +
1887 + return _mt7620_mii_write(gsw, phy_addr, phy_reg, val);
1888 +}
1889 +
1890 +int mt7620_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg)
1891 +{
1892 + struct fe_priv *priv = bus->priv;
1893 + struct mt7620_gsw *gsw = (struct mt7620_gsw *) priv->soc->swpriv;
1894 +
1895 + return _mt7620_mii_read(gsw, phy_addr, phy_reg);
1896 +}
1897 +
1898 +static unsigned char *fe_speed_str(int speed)
1899 +{
1900 + switch (speed) {
1901 + case 2:
1902 + case SPEED_1000:
1903 + return "1000";
1904 + case 1:
1905 + case SPEED_100:
1906 + return "100";
1907 + case 0:
1908 + case SPEED_10:
1909 + return "10";
1910 + }
1911 +
1912 + return "? ";
1913 +}
1914 +
1915 +int mt7620a_has_carrier(struct fe_priv *priv)
1916 +{
1917 + struct mt7620_gsw *gsw = (struct mt7620_gsw *) priv->soc->swpriv;
1918 + int i;
1919 +
1920 + for (i = 0; i < GSW_PORT6; i++)
1921 + if (gsw_r32(gsw, GSW_REG_PORT_STATUS(i)) & 0x1)
1922 + return 1;
1923 + return 0;
1924 +}
1925 +
1926 +static void mt7620a_handle_carrier(struct fe_priv *priv)
1927 +{
1928 + if (!priv->phy)
1929 + return;
1930 +
1931 + if (mt7620a_has_carrier(priv))
1932 + netif_carrier_on(priv->netdev);
1933 + else
1934 + netif_carrier_off(priv->netdev);
1935 +}
1936 +
1937 +void mt7620_mdio_link_adjust(struct fe_priv *priv, int port)
1938 +{
1939 + if (priv->link[port])
1940 + netdev_info(priv->netdev, "port %d link up (%sMbps/%s duplex)\n",
1941 + port, fe_speed_str(priv->phy->speed[port]),
1942 + (DUPLEX_FULL == priv->phy->duplex[port]) ? "Full" : "Half");
1943 + else
1944 + netdev_info(priv->netdev, "port %d link down\n", port);
1945 + mt7620a_handle_carrier(priv);
1946 +}
1947 +
1948 +static irqreturn_t gsw_interrupt(int irq, void *_priv)
1949 +{
1950 + struct fe_priv *priv = (struct fe_priv *) _priv;
1951 + struct mt7620_gsw *gsw = (struct mt7620_gsw *) priv->soc->swpriv;
1952 + u32 status;
1953 + int i, max = (gsw->port4 == PORT4_EPHY) ? (4) : (3);
1954 +
1955 + status = gsw_r32(gsw, GSW_REG_ISR);
1956 + if (status & PORT_IRQ_ST_CHG)
1957 + for (i = 0; i <= max; i++) {
1958 + u32 status = gsw_r32(gsw, GSW_REG_PORT_STATUS(i));
1959 + int link = status & 0x1;
1960 +
1961 + if (link != priv->link[i]) {
1962 + if (link)
1963 + netdev_info(priv->netdev, "port %d link up (%sMbps/%s duplex)\n",
1964 + i, fe_speed_str((status >> 2) & 3),
1965 + (status & 0x2) ? "Full" : "Half");
1966 + else
1967 + netdev_info(priv->netdev, "port %d link down\n", i);
1968 + }
1969 +
1970 + priv->link[i] = link;
1971 + }
1972 + mt7620a_handle_carrier(priv);
1973 +
1974 + gsw_w32(gsw, status, GSW_REG_ISR);
1975 +
1976 + return IRQ_HANDLED;
1977 +}
1978 +
1979 +static int mt7620_is_bga(void)
1980 +{
1981 + u32 bga = rt_sysc_r32(0x0c);
1982 +
1983 + return (bga >> 16) & 1;
1984 +}
1985 +
1986 +static void gsw_auto_poll(struct mt7620_gsw *gsw)
1987 +{
1988 + int phy;
1989 + int lsb = -1, msb = 0;
1990 +
1991 + for_each_set_bit(phy, &gsw->autopoll, 32) {
1992 + if (lsb < 0)
1993 + lsb = phy;
1994 + msb = phy;
1995 + }
1996 +
1997 + gsw_w32(gsw, PHY_AN_EN | PHY_PRE_EN | PMY_MDC_CONF(5) | (msb << 8) | lsb, ESW_PHY_POLLING);
1998 +}
1999 +
2000 +void mt7620_port_init(struct fe_priv *priv, struct device_node *np)
2001 +{
2002 + struct mt7620_gsw *gsw = (struct mt7620_gsw *) priv->soc->swpriv;
2003 + const __be32 *_id = of_get_property(np, "reg", NULL);
2004 + int phy_mode, size, id;
2005 + int shift = 12;
2006 + u32 val, mask = 0;
2007 + int min = (gsw->port4 == PORT4_EPHY) ? (5) : (4);
2008 +
2009 + if (!_id || (be32_to_cpu(*_id) < min) || (be32_to_cpu(*_id) > 5)) {
2010 + if (_id)
2011 + pr_err("%s: invalid port id %d\n", np->name, be32_to_cpu(*_id));
2012 + else
2013 + pr_err("%s: invalid port id\n", np->name);
2014 + return;
2015 + }
2016 +
2017 + id = be32_to_cpu(*_id);
2018 +
2019 + if (id == 4)
2020 + shift = 14;
2021 +
2022 + priv->phy->phy_fixed[id] = of_get_property(np, "ralink,fixed-link", &size);
2023 + if (priv->phy->phy_fixed[id] && (size != (4 * sizeof(*priv->phy->phy_fixed[id])))) {
2024 + pr_err("%s: invalid fixed link property\n", np->name);
2025 + priv->phy->phy_fixed[id] = NULL;
2026 + return;
2027 + }
2028 +
2029 + phy_mode = of_get_phy_mode(np);
2030 + switch (phy_mode) {
2031 + case PHY_INTERFACE_MODE_RGMII:
2032 + mask = 0;
2033 + break;
2034 + case PHY_INTERFACE_MODE_MII:
2035 + mask = 1;
2036 + break;
2037 + case PHY_INTERFACE_MODE_RMII:
2038 + mask = 2;
2039 + break;
2040 + default:
2041 + dev_err(priv->device, "port %d - invalid phy mode\n", id);
2042 + return;
2043 + }
2044 +
2045 + priv->phy->phy_node[id] = of_parse_phandle(np, "phy-handle", 0);
2046 + if (!priv->phy->phy_node[id] && !priv->phy->phy_fixed[id])
2047 + return;
2048 +
2049 + val = rt_sysc_r32(SYSCFG1);
2050 + val &= ~(3 << shift);
2051 + val |= mask << shift;
2052 + rt_sysc_w32(val, SYSCFG1);
2053 +
2054 + if (priv->phy->phy_fixed[id]) {
2055 + const __be32 *link = priv->phy->phy_fixed[id];
2056 + int tx_fc, rx_fc;
2057 + u32 val = 0;
2058 +
2059 + priv->phy->speed[id] = be32_to_cpup(link++);
2060 + tx_fc = be32_to_cpup(link++);
2061 + rx_fc = be32_to_cpup(link++);
2062 + priv->phy->duplex[id] = be32_to_cpup(link++);
2063 + priv->link[id] = 1;
2064 +
2065 + switch (priv->phy->speed[id]) {
2066 + case SPEED_10:
2067 + val = 0;
2068 + break;
2069 + case SPEED_100:
2070 + val = 1;
2071 + break;
2072 + case SPEED_1000:
2073 + val = 2;
2074 + break;
2075 + default:
2076 + dev_err(priv->device, "invalid link speed: %d\n", priv->phy->speed[id]);
2077 + priv->phy->phy_fixed[id] = 0;
2078 + return;
2079 + }
2080 + val = PMCR_SPEED(val);
2081 + val |= PMCR_LINK | PMCR_BACKPRES | PMCR_BACKOFF | PMCR_RX_EN |
2082 + PMCR_TX_EN | PMCR_FORCE | PMCR_MAC_MODE | PMCR_IPG;
2083 + if (tx_fc)
2084 + val |= PMCR_TX_FC;
2085 + if (rx_fc)
2086 + val |= PMCR_RX_FC;
2087 + if (priv->phy->duplex[id])
2088 + val |= PMCR_DUPLEX;
2089 + gsw_w32(gsw, val, GSW_REG_PORT_PMCR(id));
2090 + dev_info(priv->device, "using fixed link parameters\n");
2091 + return;
2092 + }
2093 +
2094 + if (priv->phy->phy_node[id] && priv->mii_bus->phy_map[id]) {
2095 + u32 val = PMCR_BACKPRES | PMCR_BACKOFF | PMCR_RX_EN |
2096 + PMCR_TX_EN | PMCR_MAC_MODE | PMCR_IPG;
2097 +
2098 + gsw_w32(gsw, val, GSW_REG_PORT_PMCR(id));
2099 + fe_connect_phy_node(priv, priv->phy->phy_node[id]);
2100 + gsw->autopoll |= BIT(id);
2101 + gsw_auto_poll(gsw);
2102 + return;
2103 + }
2104 +}
2105 +
2106 +static void gsw_hw_init(struct mt7620_gsw *gsw)
2107 +{
2108 + u32 is_BGA = mt7620_is_bga();
2109 +
2110 + rt_sysc_w32(rt_sysc_r32(SYSC_REG_CFG1) | BIT(8), SYSC_REG_CFG1);
2111 + gsw_w32(gsw, gsw_r32(gsw, GSW_REG_CKGCR) & ~(0x3 << 4), GSW_REG_CKGCR);
2112 +
2113 + /*correct PHY setting L3.0 BGA*/
2114 + _mt7620_mii_write(gsw, 1, 31, 0x4000); //global, page 4
2115 +
2116 + _mt7620_mii_write(gsw, 1, 17, 0x7444);
2117 + if (is_BGA)
2118 + _mt7620_mii_write(gsw, 1, 19, 0x0114);
2119 + else
2120 + _mt7620_mii_write(gsw, 1, 19, 0x0117);
2121 +
2122 + _mt7620_mii_write(gsw, 1, 22, 0x10cf);
2123 + _mt7620_mii_write(gsw, 1, 25, 0x6212);
2124 + _mt7620_mii_write(gsw, 1, 26, 0x0777);
2125 + _mt7620_mii_write(gsw, 1, 29, 0x4000);
2126 + _mt7620_mii_write(gsw, 1, 28, 0xc077);
2127 + _mt7620_mii_write(gsw, 1, 24, 0x0000);
2128 +
2129 + _mt7620_mii_write(gsw, 1, 31, 0x3000); //global, page 3
2130 + _mt7620_mii_write(gsw, 1, 17, 0x4838);
2131 +
2132 + _mt7620_mii_write(gsw, 1, 31, 0x2000); //global, page 2
2133 + if (is_BGA) {
2134 + _mt7620_mii_write(gsw, 1, 21, 0x0515);
2135 + _mt7620_mii_write(gsw, 1, 22, 0x0053);
2136 + _mt7620_mii_write(gsw, 1, 23, 0x00bf);
2137 + _mt7620_mii_write(gsw, 1, 24, 0x0aaf);
2138 + _mt7620_mii_write(gsw, 1, 25, 0x0fad);
2139 + _mt7620_mii_write(gsw, 1, 26, 0x0fc1);
2140 + } else {
2141 + _mt7620_mii_write(gsw, 1, 21, 0x0517);
2142 + _mt7620_mii_write(gsw, 1, 22, 0x0fd2);
2143 + _mt7620_mii_write(gsw, 1, 23, 0x00bf);
2144 + _mt7620_mii_write(gsw, 1, 24, 0x0aab);
2145 + _mt7620_mii_write(gsw, 1, 25, 0x00ae);
2146 + _mt7620_mii_write(gsw, 1, 26, 0x0fff);
2147 + }
2148 + _mt7620_mii_write(gsw, 1, 31, 0x1000); //global, page 1
2149 + _mt7620_mii_write(gsw, 1, 17, 0xe7f8);
2150 +
2151 + _mt7620_mii_write(gsw, 1, 31, 0x8000); //local, page 0
2152 + _mt7620_mii_write(gsw, 0, 30, 0xa000);
2153 + _mt7620_mii_write(gsw, 1, 30, 0xa000);
2154 + _mt7620_mii_write(gsw, 2, 30, 0xa000);
2155 + _mt7620_mii_write(gsw, 3, 30, 0xa000);
2156 +
2157 + _mt7620_mii_write(gsw, 0, 4, 0x05e1);
2158 + _mt7620_mii_write(gsw, 1, 4, 0x05e1);
2159 + _mt7620_mii_write(gsw, 2, 4, 0x05e1);
2160 + _mt7620_mii_write(gsw, 3, 4, 0x05e1);
2161 + _mt7620_mii_write(gsw, 1, 31, 0xa000); //local, page 2
2162 + _mt7620_mii_write(gsw, 0, 16, 0x1111);
2163 + _mt7620_mii_write(gsw, 1, 16, 0x1010);
2164 + _mt7620_mii_write(gsw, 2, 16, 0x1515);
2165 + _mt7620_mii_write(gsw, 3, 16, 0x0f0f);
2166 +
2167 + /* CPU Port6 Force Link 1G, FC ON */
2168 + gsw_w32(gsw, 0x5e33b, GSW_REG_PORT_PMCR(6));
2169 + /* Set Port6 CPU Port */
2170 + gsw_w32(gsw, 0x7f7f7fe0, 0x0010);
2171 +
2172 + /* setup port 4 */
2173 + if (gsw->port4 == PORT4_EPHY) {
2174 + u32 val = rt_sysc_r32(SYSCFG1);
2175 + val |= 3 << 14;
2176 + rt_sysc_w32(val, SYSCFG1);
2177 + _mt7620_mii_write(gsw, 4, 30, 0xa000);
2178 + _mt7620_mii_write(gsw, 4, 4, 0x05e1);
2179 + _mt7620_mii_write(gsw, 4, 16, 0x1313);
2180 + pr_info("gsw: setting port4 to ephy mode\n");
2181 + }
2182 +}
2183 +
2184 +void mt7620_set_mac(struct fe_priv *priv, unsigned char *mac)
2185 +{
2186 + struct mt7620_gsw *gsw = (struct mt7620_gsw *) priv->soc->swpriv;
2187 + unsigned long flags;
2188 +
2189 + spin_lock_irqsave(&priv->page_lock, flags);
2190 + gsw_w32(gsw, (mac[0] << 8) | mac[1], GSW_REG_SMACCR1);
2191 + gsw_w32(gsw, (mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5],
2192 + GSW_REG_SMACCR0);
2193 + spin_unlock_irqrestore(&priv->page_lock, flags);
2194 +}
2195 +
2196 +static struct of_device_id gsw_match[] = {
2197 + { .compatible = "ralink,mt7620a-gsw" },
2198 + {}
2199 +};
2200 +
2201 +int mt7620_gsw_config(struct fe_priv *priv)
2202 +{
2203 + struct mt7620_gsw *gsw = (struct mt7620_gsw *) priv->soc->swpriv;
2204 +
2205 + /* is the mt7530 internal or external */
2206 + if ((_mt7620_mii_read(gsw, 0x1f, 2) == 1) && (_mt7620_mii_read(gsw, 0x1f, 3) == 0xbeef))
2207 + mt7530_probe(priv->device, NULL, priv->mii_bus);
2208 + else
2209 + mt7530_probe(priv->device, gsw->base, NULL);
2210 +
2211 + return 0;
2212 +}
2213 +
2214 +int mt7620_gsw_probe(struct fe_priv *priv)
2215 +{
2216 + struct mt7620_gsw *gsw;
2217 + struct device_node *np;
2218 + const char *port4 = NULL;
2219 +
2220 + np = of_find_matching_node(NULL, gsw_match);
2221 + if (!np) {
2222 + dev_err(priv->device, "no gsw node found\n");
2223 + return -EINVAL;
2224 + }
2225 + np = of_node_get(np);
2226 +
2227 + gsw = devm_kzalloc(priv->device, sizeof(struct mt7620_gsw), GFP_KERNEL);
2228 + if (!gsw) {
2229 + dev_err(priv->device, "no gsw memory for private data\n");
2230 + return -ENOMEM;
2231 + }
2232 +
2233 + gsw->irq = irq_of_parse_and_map(np, 0);
2234 + if (!gsw->irq) {
2235 + dev_err(priv->device, "no gsw irq resource found\n");
2236 + return -ENOMEM;
2237 + }
2238 +
2239 + gsw->base = of_iomap(np, 0);
2240 + if (!gsw->base) {
2241 + dev_err(priv->device, "gsw ioremap failed\n");
2242 + return -ENOMEM;
2243 + }
2244 +
2245 + gsw->dev = priv->device;
2246 + priv->soc->swpriv = gsw;
2247 +
2248 + of_property_read_string(np, "ralink,port4", &port4);
2249 + if (port4 && !strcmp(port4, "ephy"))
2250 + gsw->port4 = PORT4_EPHY;
2251 + else if (port4 && !strcmp(port4, "gmac"))
2252 + gsw->port4 = PORT4_EXT;
2253 + else
2254 + WARN_ON(port4);
2255 +
2256 + gsw_hw_init(gsw);
2257 +
2258 + gsw_w32(gsw, ~PORT_IRQ_ST_CHG, GSW_REG_IMR);
2259 + request_irq(gsw->irq, gsw_interrupt, 0, "gsw", priv);
2260 +
2261 + return 0;
2262 +}
2263 diff --git a/drivers/net/ethernet/ralink/gsw_mt7620a.h b/drivers/net/ethernet/ralink/gsw_mt7620a.h
2264 new file mode 100644
2265 index 0000000..c87761a
2266 --- /dev/null
2267 +++ b/drivers/net/ethernet/ralink/gsw_mt7620a.h
2268 @@ -0,0 +1,30 @@
2269 +/*
2270 + * This program is free software; you can redistribute it and/or modify
2271 + * it under the terms of the GNU General Public License as published by
2272 + * the Free Software Foundation; version 2 of the License
2273 + *
2274 + * This program is distributed in the hope that it will be useful,
2275 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
2276 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2277 + * GNU General Public License for more details.
2278 + *
2279 + * You should have received a copy of the GNU General Public License
2280 + * along with this program; if not, write to the Free Software
2281 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
2282 + *
2283 + * Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
2284 + */
2285 +
2286 +#ifndef _RALINK_GSW_MT7620_H__
2287 +#define _RALINK_GSW_MT7620_H__
2288 +
2289 +extern int mt7620_gsw_config(struct fe_priv *priv);
2290 +extern int mt7620_gsw_probe(struct fe_priv *priv);
2291 +extern void mt7620_set_mac(struct fe_priv *priv, unsigned char *mac);
2292 +extern int mt7620_mdio_write(struct mii_bus *bus, int phy_addr, int phy_reg, u16 val);
2293 +extern int mt7620_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg);
2294 +extern void mt7620_mdio_link_adjust(struct fe_priv *priv, int port);
2295 +extern void mt7620_port_init(struct fe_priv *priv, struct device_node *np);
2296 +extern int mt7620a_has_carrier(struct fe_priv *priv);
2297 +
2298 +#endif
2299 diff --git a/drivers/net/ethernet/ralink/mdio.c b/drivers/net/ethernet/ralink/mdio.c
2300 new file mode 100644
2301 index 0000000..32bf98b
2302 --- /dev/null
2303 +++ b/drivers/net/ethernet/ralink/mdio.c
2304 @@ -0,0 +1,244 @@
2305 +/*
2306 + * This program is free software; you can redistribute it and/or modify
2307 + * it under the terms of the GNU General Public License as published by
2308 + * the Free Software Foundation; version 2 of the License
2309 + *
2310 + * This program is distributed in the hope that it will be useful,
2311 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
2312 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2313 + * GNU General Public License for more details.
2314 + *
2315 + * You should have received a copy of the GNU General Public License
2316 + * along with this program; if not, write to the Free Software
2317 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
2318 + *
2319 + * Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
2320 + */
2321 +
2322 +#include <linux/module.h>
2323 +#include <linux/kernel.h>
2324 +#include <linux/types.h>
2325 +#include <linux/dma-mapping.h>
2326 +#include <linux/init.h>
2327 +#include <linux/skbuff.h>
2328 +#include <linux/etherdevice.h>
2329 +#include <linux/ethtool.h>
2330 +#include <linux/platform_device.h>
2331 +#include <linux/phy.h>
2332 +#include <linux/of_device.h>
2333 +#include <linux/clk.h>
2334 +#include <linux/of_net.h>
2335 +#include <linux/of_mdio.h>
2336 +
2337 +#include "ralink_soc_eth.h"
2338 +#include "mdio.h"
2339 +
2340 +static int fe_mdio_reset(struct mii_bus *bus)
2341 +{
2342 + /* TODO */
2343 + return 0;
2344 +}
2345 +
2346 +static void fe_phy_link_adjust(struct net_device *dev)
2347 +{
2348 + struct fe_priv *priv = netdev_priv(dev);
2349 + unsigned long flags;
2350 + int i;
2351 +
2352 + spin_lock_irqsave(&priv->phy->lock, flags);
2353 + for (i = 0; i < 8; i++) {
2354 + if (priv->phy->phy_node[i]) {
2355 + struct phy_device *phydev = priv->phy->phy[i];
2356 + int status_change = 0;
2357 +
2358 + if (phydev->link)
2359 + if (priv->phy->duplex[i] != phydev->duplex ||
2360 + priv->phy->speed[i] != phydev->speed)
2361 + status_change = 1;
2362 +
2363 + if (phydev->link != priv->link[i])
2364 + status_change = 1;
2365 +
2366 + switch (phydev->speed) {
2367 + case SPEED_1000:
2368 + case SPEED_100:
2369 + case SPEED_10:
2370 + priv->link[i] = phydev->link;
2371 + priv->phy->duplex[i] = phydev->duplex;
2372 + priv->phy->speed[i] = phydev->speed;
2373 +
2374 + if (status_change && priv->soc->mdio_adjust_link)
2375 + priv->soc->mdio_adjust_link(priv, i);
2376 + break;
2377 + }
2378 + }
2379 + }
2380 +}
2381 +
2382 +int fe_connect_phy_node(struct fe_priv *priv, struct device_node *phy_node)
2383 +{
2384 + const __be32 *_port = NULL;
2385 + struct phy_device *phydev;
2386 + int phy_mode, port;
2387 +
2388 + _port = of_get_property(phy_node, "reg", NULL);
2389 +
2390 + if (!_port || (be32_to_cpu(*_port) >= 0x20)) {
2391 + pr_err("%s: invalid port id\n", phy_node->name);
2392 + return -EINVAL;
2393 + }
2394 + port = be32_to_cpu(*_port);
2395 + phy_mode = of_get_phy_mode(phy_node);
2396 + if (phy_mode < 0) {
2397 + dev_err(priv->device, "incorrect phy-mode %d\n", phy_mode);
2398 + priv->phy->phy_node[port] = NULL;
2399 + return -EINVAL;
2400 + }
2401 +
2402 + phydev = of_phy_connect(priv->netdev, phy_node, fe_phy_link_adjust,
2403 + 0, phy_mode);
2404 + if (IS_ERR(phydev)) {
2405 + dev_err(priv->device, "could not connect to PHY\n");
2406 + priv->phy->phy_node[port] = NULL;
2407 + return PTR_ERR(phydev);
2408 + }
2409 +
2410 + phydev->supported &= PHY_GBIT_FEATURES;
2411 + phydev->advertising = phydev->supported;
2412 + phydev->no_auto_carrier_off = 1;
2413 +
2414 + dev_info(priv->device,
2415 + "connected port %d to PHY at %s [uid=%08x, driver=%s]\n",
2416 + port, dev_name(&phydev->dev), phydev->phy_id,
2417 + phydev->drv->name);
2418 +
2419 + priv->phy->phy[port] = phydev;
2420 + priv->link[port] = 0;
2421 +
2422 + return 0;
2423 +}
2424 +
2425 +static int fe_phy_connect(struct fe_priv *priv)
2426 +{
2427 + return 0;
2428 +}
2429 +
2430 +static void fe_phy_disconnect(struct fe_priv *priv)
2431 +{
2432 + unsigned long flags;
2433 + int i;
2434 +
2435 + for (i = 0; i < 8; i++)
2436 + if (priv->phy->phy_fixed[i]) {
2437 + spin_lock_irqsave(&priv->phy->lock, flags);
2438 + priv->link[i] = 0;
2439 + if (priv->soc->mdio_adjust_link)
2440 + priv->soc->mdio_adjust_link(priv, i);
2441 + spin_unlock_irqrestore(&priv->phy->lock, flags);
2442 + } else if (priv->phy->phy[i]) {
2443 + phy_disconnect(priv->phy->phy[i]);
2444 + }
2445 +}
2446 +
2447 +static void fe_phy_start(struct fe_priv *priv)
2448 +{
2449 + unsigned long flags;
2450 + int i;
2451 +
2452 + for (i = 0; i < 8; i++) {
2453 + if (priv->phy->phy_fixed[i]) {
2454 + spin_lock_irqsave(&priv->phy->lock, flags);
2455 + priv->link[i] = 1;
2456 + if (priv->soc->mdio_adjust_link)
2457 + priv->soc->mdio_adjust_link(priv, i);
2458 + spin_unlock_irqrestore(&priv->phy->lock, flags);
2459 + } else if (priv->phy->phy[i]) {
2460 + phy_start(priv->phy->phy[i]);
2461 + }
2462 + }
2463 +}
2464 +
2465 +static void fe_phy_stop(struct fe_priv *priv)
2466 +{
2467 + unsigned long flags;
2468 + int i;
2469 +
2470 + for (i = 0; i < 8; i++)
2471 + if (priv->phy->phy_fixed[i]) {
2472 + spin_lock_irqsave(&priv->phy->lock, flags);
2473 + priv->link[i] = 0;
2474 + if (priv->soc->mdio_adjust_link)
2475 + priv->soc->mdio_adjust_link(priv, i);
2476 + spin_unlock_irqrestore(&priv->phy->lock, flags);
2477 + } else if (priv->phy->phy[i]) {
2478 + phy_stop(priv->phy->phy[i]);
2479 + }
2480 +}
2481 +
2482 +static struct fe_phy phy_ralink = {
2483 + .connect = fe_phy_connect,
2484 + .disconnect = fe_phy_disconnect,
2485 + .start = fe_phy_start,
2486 + .stop = fe_phy_stop,
2487 +};
2488 +
2489 +int fe_mdio_init(struct fe_priv *priv)
2490 +{
2491 + struct device_node *mii_np;
2492 + int err;
2493 +
2494 + if (!priv->soc->mdio_read || !priv->soc->mdio_write)
2495 + return 0;
2496 +
2497 + spin_lock_init(&phy_ralink.lock);
2498 + priv->phy = &phy_ralink;
2499 +
2500 + mii_np = of_get_child_by_name(priv->device->of_node, "mdio-bus");
2501 + if (!mii_np) {
2502 + dev_err(priv->device, "no %s child node found", "mdio-bus");
2503 + return -ENODEV;
2504 + }
2505 +
2506 + if (!of_device_is_available(mii_np)) {
2507 + err = 0;
2508 + goto err_put_node;
2509 + }
2510 +
2511 + priv->mii_bus = mdiobus_alloc();
2512 + if (priv->mii_bus == NULL) {
2513 + err = -ENOMEM;
2514 + goto err_put_node;
2515 + }
2516 +
2517 + priv->mii_bus->name = "mdio";
2518 + priv->mii_bus->read = priv->soc->mdio_read;
2519 + priv->mii_bus->write = priv->soc->mdio_write;
2520 + priv->mii_bus->reset = fe_mdio_reset;
2521 + priv->mii_bus->irq = priv->mii_irq;
2522 + priv->mii_bus->priv = priv;
2523 + priv->mii_bus->parent = priv->device;
2524 +
2525 + snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s", mii_np->name);
2526 + err = of_mdiobus_register(priv->mii_bus, mii_np);
2527 + if (err)
2528 + goto err_free_bus;
2529 +
2530 + return 0;
2531 +
2532 +err_free_bus:
2533 + kfree(priv->mii_bus);
2534 +err_put_node:
2535 + of_node_put(mii_np);
2536 + priv->mii_bus = NULL;
2537 + return err;
2538 +}
2539 +
2540 +void fe_mdio_cleanup(struct fe_priv *priv)
2541 +{
2542 + if (!priv->mii_bus)
2543 + return;
2544 +
2545 + mdiobus_unregister(priv->mii_bus);
2546 + of_node_put(priv->mii_bus->dev.of_node);
2547 + kfree(priv->mii_bus);
2548 +}
2549 diff --git a/drivers/net/ethernet/ralink/mdio.h b/drivers/net/ethernet/ralink/mdio.h
2550 new file mode 100644
2551 index 0000000..c3910a0
2552 --- /dev/null
2553 +++ b/drivers/net/ethernet/ralink/mdio.h
2554 @@ -0,0 +1,29 @@
2555 +/*
2556 + * This program is free software; you can redistribute it and/or modify
2557 + * it under the terms of the GNU General Public License as published by
2558 + * the Free Software Foundation; version 2 of the License
2559 + *
2560 + * This program is distributed in the hope that it will be useful,
2561 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
2562 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2563 + * GNU General Public License for more details.
2564 + *
2565 + * You should have received a copy of the GNU General Public License
2566 + * along with this program; if not, write to the Free Software
2567 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
2568 + *
2569 + * Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
2570 + */
2571 +
2572 +#ifndef _RALINK_MDIO_H__
2573 +#define _RALINK_MDIO_H__
2574 +
2575 +#ifdef CONFIG_NET_RALINK_MDIO
2576 +extern int fe_mdio_init(struct fe_priv *priv);
2577 +extern void fe_mdio_cleanup(struct fe_priv *priv);
2578 +extern int fe_connect_phy_node(struct fe_priv *priv, struct device_node *phy_node);
2579 +#else
2580 +static inline int fe_mdio_init(struct fe_priv *priv) { return 0; }
2581 +static inline void fe_mdio_cleanup(struct fe_priv *priv) {}
2582 +#endif
2583 +#endif
2584 diff --git a/drivers/net/ethernet/ralink/mdio_rt2880.c b/drivers/net/ethernet/ralink/mdio_rt2880.c
2585 new file mode 100644
2586 index 0000000..b99eb46
2587 --- /dev/null
2588 +++ b/drivers/net/ethernet/ralink/mdio_rt2880.c
2589 @@ -0,0 +1,232 @@
2590 +/*
2591 + * This program is free software; you can redistribute it and/or modify
2592 + * it under the terms of the GNU General Public License as published by
2593 + * the Free Software Foundation; version 2 of the License
2594 + *
2595 + * This program is distributed in the hope that it will be useful,
2596 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
2597 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2598 + * GNU General Public License for more details.
2599 + *
2600 + * You should have received a copy of the GNU General Public License
2601 + * along with this program; if not, write to the Free Software
2602 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
2603 + *
2604 + * Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
2605 + */
2606 +
2607 +#include <linux/module.h>
2608 +#include <linux/kernel.h>
2609 +#include <linux/types.h>
2610 +#include <linux/dma-mapping.h>
2611 +#include <linux/init.h>
2612 +#include <linux/skbuff.h>
2613 +#include <linux/etherdevice.h>
2614 +#include <linux/ethtool.h>
2615 +#include <linux/platform_device.h>
2616 +#include <linux/phy.h>
2617 +#include <linux/of_device.h>
2618 +#include <linux/clk.h>
2619 +#include <linux/of_net.h>
2620 +#include <linux/of_mdio.h>
2621 +
2622 +#include "ralink_soc_eth.h"
2623 +#include "mdio_rt2880.h"
2624 +#include "mdio.h"
2625 +
2626 +#define FE_MDIO_RETRY 1000
2627 +
2628 +static unsigned char *rt2880_speed_str(struct fe_priv *priv)
2629 +{
2630 + switch (priv->phy->speed[0]) {
2631 + case SPEED_1000:
2632 + return "1000";
2633 + case SPEED_100:
2634 + return "100";
2635 + case SPEED_10:
2636 + return "10";
2637 + }
2638 +
2639 + return "?";
2640 +}
2641 +
2642 +void rt2880_mdio_link_adjust(struct fe_priv *priv, int port)
2643 +{
2644 + u32 mdio_cfg;
2645 +
2646 + if (!priv->link[0]) {
2647 + netif_carrier_off(priv->netdev);
2648 + netdev_info(priv->netdev, "link down\n");
2649 + return;
2650 + }
2651 +
2652 + mdio_cfg = FE_MDIO_CFG_TX_CLK_SKEW_200 |
2653 + FE_MDIO_CFG_RX_CLK_SKEW_200 |
2654 + FE_MDIO_CFG_GP1_FRC_EN;
2655 +
2656 + if (priv->phy->duplex[0] == DUPLEX_FULL)
2657 + mdio_cfg |= FE_MDIO_CFG_GP1_DUPLEX;
2658 +
2659 + if (priv->phy->tx_fc[0])
2660 + mdio_cfg |= FE_MDIO_CFG_GP1_FC_TX;
2661 +
2662 + if (priv->phy->rx_fc[0])
2663 + mdio_cfg |= FE_MDIO_CFG_GP1_FC_RX;
2664 +
2665 + switch (priv->phy->speed[0]) {
2666 + case SPEED_10:
2667 + mdio_cfg |= FE_MDIO_CFG_GP1_SPEED_10;
2668 + break;
2669 + case SPEED_100:
2670 + mdio_cfg |= FE_MDIO_CFG_GP1_SPEED_100;
2671 + break;
2672 + case SPEED_1000:
2673 + mdio_cfg |= FE_MDIO_CFG_GP1_SPEED_1000;
2674 + break;
2675 + default:
2676 + BUG();
2677 + }
2678 +
2679 + fe_w32(mdio_cfg, FE_MDIO_CFG);
2680 +
2681 + netif_carrier_on(priv->netdev);
2682 + netdev_info(priv->netdev, "link up (%sMbps/%s duplex)\n",
2683 + rt2880_speed_str(priv),
2684 + (DUPLEX_FULL == priv->phy->duplex[0]) ? "Full" : "Half");
2685 +}
2686 +
2687 +static int rt2880_mdio_wait_ready(struct fe_priv *priv)
2688 +{
2689 + int retries;
2690 +
2691 + retries = FE_MDIO_RETRY;
2692 + while (1) {
2693 + u32 t;
2694 +
2695 + t = fe_r32(FE_MDIO_ACCESS);
2696 + if ((t & (0x1 << 31)) == 0)
2697 + return 0;
2698 +
2699 + if (retries-- == 0)
2700 + break;
2701 +
2702 + udelay(1);
2703 + }
2704 +
2705 + dev_err(priv->device, "MDIO operation timed out\n");
2706 + return -ETIMEDOUT;
2707 +}
2708 +
2709 +int rt2880_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg)
2710 +{
2711 + struct fe_priv *priv = bus->priv;
2712 + int err;
2713 + u32 t;
2714 +
2715 + err = rt2880_mdio_wait_ready(priv);
2716 + if (err)
2717 + return 0xffff;
2718 +
2719 + t = (phy_addr << 24) | (phy_reg << 16);
2720 + fe_w32(t, FE_MDIO_ACCESS);
2721 + t |= (1 << 31);
2722 + fe_w32(t, FE_MDIO_ACCESS);
2723 +
2724 + err = rt2880_mdio_wait_ready(priv);
2725 + if (err)
2726 + return 0xffff;
2727 +
2728 + pr_debug("%s: addr=%04x, reg=%04x, value=%04x\n", __func__,
2729 + phy_addr, phy_reg, fe_r32(FE_MDIO_ACCESS) & 0xffff);
2730 +
2731 + return fe_r32(FE_MDIO_ACCESS) & 0xffff;
2732 +}
2733 +
2734 +int rt2880_mdio_write(struct mii_bus *bus, int phy_addr, int phy_reg, u16 val)
2735 +{
2736 + struct fe_priv *priv = bus->priv;
2737 + int err;
2738 + u32 t;
2739 +
2740 + pr_debug("%s: addr=%04x, reg=%04x, value=%04x\n", __func__,
2741 + phy_addr, phy_reg, fe_r32(FE_MDIO_ACCESS) & 0xffff);
2742 +
2743 + err = rt2880_mdio_wait_ready(priv);
2744 + if (err)
2745 + return err;
2746 +
2747 + t = (1 << 30) | (phy_addr << 24) | (phy_reg << 16) | val;
2748 + fe_w32(t, FE_MDIO_ACCESS);
2749 + t |= (1 << 31);
2750 + fe_w32(t, FE_MDIO_ACCESS);
2751 +
2752 + return rt2880_mdio_wait_ready(priv);
2753 +}
2754 +
2755 +void rt2880_port_init(struct fe_priv *priv, struct device_node *np)
2756 +{
2757 + const __be32 *id = of_get_property(np, "reg", NULL);
2758 + const __be32 *link;
2759 + int size;
2760 + int phy_mode;
2761 +
2762 + if (!id || (be32_to_cpu(*id) != 0)) {
2763 + pr_err("%s: invalid port id\n", np->name);
2764 + return;
2765 + }
2766 +
2767 + priv->phy->phy_fixed[0] = of_get_property(np, "ralink,fixed-link", &size);
2768 + if (priv->phy->phy_fixed[0] && (size != (4 * sizeof(*priv->phy->phy_fixed[0])))) {
2769 + pr_err("%s: invalid fixed link property\n", np->name);
2770 + priv->phy->phy_fixed[0] = NULL;
2771 + return;
2772 + }
2773 +
2774 + phy_mode = of_get_phy_mode(np);
2775 + switch (phy_mode) {
2776 + case PHY_INTERFACE_MODE_RGMII:
2777 + break;
2778 + case PHY_INTERFACE_MODE_MII:
2779 + break;
2780 + case PHY_INTERFACE_MODE_RMII:
2781 + break;
2782 + default:
2783 + if (!priv->phy->phy_fixed[0])
2784 + dev_err(priv->device, "port %d - invalid phy mode\n", priv->phy->speed[0]);
2785 + break;
2786 + }
2787 +
2788 + priv->phy->phy_node[0] = of_parse_phandle(np, "phy-handle", 0);
2789 + if (!priv->phy->phy_node[0] && !priv->phy->phy_fixed[0])
2790 + return;
2791 +
2792 + if (priv->phy->phy_fixed[0]) {
2793 + link = priv->phy->phy_fixed[0];
2794 + priv->phy->speed[0] = be32_to_cpup(link++);
2795 + priv->phy->duplex[0] = be32_to_cpup(link++);
2796 + priv->phy->tx_fc[0] = be32_to_cpup(link++);
2797 + priv->phy->rx_fc[0] = be32_to_cpup(link++);
2798 +
2799 + priv->link[0] = 1;
2800 + switch (priv->phy->speed[0]) {
2801 + case SPEED_10:
2802 + break;
2803 + case SPEED_100:
2804 + break;
2805 + case SPEED_1000:
2806 + break;
2807 + default:
2808 + dev_err(priv->device, "invalid link speed: %d\n", priv->phy->speed[0]);
2809 + priv->phy->phy_fixed[0] = 0;
2810 + return;
2811 + }
2812 + dev_info(priv->device, "using fixed link parameters\n");
2813 + rt2880_mdio_link_adjust(priv, 0);
2814 + return;
2815 + }
2816 + if (priv->phy->phy_node[0] && priv->mii_bus->phy_map[0]) {
2817 + fe_connect_phy_node(priv, priv->phy->phy_node[0]);
2818 + }
2819 +
2820 + return;
2821 +}
2822 diff --git a/drivers/net/ethernet/ralink/mdio_rt2880.h b/drivers/net/ethernet/ralink/mdio_rt2880.h
2823 new file mode 100644
2824 index 0000000..51e3633
2825 --- /dev/null
2826 +++ b/drivers/net/ethernet/ralink/mdio_rt2880.h
2827 @@ -0,0 +1,26 @@
2828 +/*
2829 + * This program is free software; you can redistribute it and/or modify
2830 + * it under the terms of the GNU General Public License as published by
2831 + * the Free Software Foundation; version 2 of the License
2832 + *
2833 + * This program is distributed in the hope that it will be useful,
2834 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
2835 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2836 + * GNU General Public License for more details.
2837 + *
2838 + * You should have received a copy of the GNU General Public License
2839 + * along with this program; if not, write to the Free Software
2840 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
2841 + *
2842 + * Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
2843 + */
2844 +
2845 +#ifndef _RALINK_MDIO_RT2880_H__
2846 +#define _RALINK_MDIO_RT2880_H__
2847 +
2848 +void rt2880_mdio_link_adjust(struct fe_priv *priv, int port);
2849 +int rt2880_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg);
2850 +int rt2880_mdio_write(struct mii_bus *bus, int phy_addr, int phy_reg, u16 val);
2851 +void rt2880_port_init(struct fe_priv *priv, struct device_node *np);
2852 +
2853 +#endif
2854 diff --git a/drivers/net/ethernet/ralink/mt7530.c b/drivers/net/ethernet/ralink/mt7530.c
2855 new file mode 100644
2856 index 0000000..06b67ee
2857 --- /dev/null
2858 +++ b/drivers/net/ethernet/ralink/mt7530.c
2859 @@ -0,0 +1,579 @@
2860 +/*
2861 + * This program is free software; you can redistribute it and/or
2862 + * modify it under the terms of the GNU General Public License
2863 + * as published by the Free Software Foundation; either version 2
2864 + * of the License, or (at your option) any later version.
2865 + *
2866 + * This program is distributed in the hope that it will be useful,
2867 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
2868 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2869 + * GNU General Public License for more details.
2870 + *
2871 + * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
2872 + */
2873 +
2874 +#include <linux/if.h>
2875 +#include <linux/module.h>
2876 +#include <linux/init.h>
2877 +#include <linux/list.h>
2878 +#include <linux/if_ether.h>
2879 +#include <linux/skbuff.h>
2880 +#include <linux/netdevice.h>
2881 +#include <linux/netlink.h>
2882 +#include <linux/bitops.h>
2883 +#include <net/genetlink.h>
2884 +#include <linux/switch.h>
2885 +#include <linux/delay.h>
2886 +#include <linux/phy.h>
2887 +#include <linux/netdevice.h>
2888 +#include <linux/etherdevice.h>
2889 +#include <linux/lockdep.h>
2890 +#include <linux/workqueue.h>
2891 +#include <linux/of_device.h>
2892 +
2893 +#include "mt7530.h"
2894 +
2895 +#define MT7530_CPU_PORT 6
2896 +#define MT7530_NUM_PORTS 8
2897 +#define MT7530_NUM_VLANS 16
2898 +#define MT7530_MAX_VID 4095
2899 +#define MT7530_MIN_VID 0
2900 +
2901 +/* registers */
2902 +#define REG_ESW_VLAN_VTCR 0x90
2903 +#define REG_ESW_VLAN_VAWD1 0x94
2904 +#define REG_ESW_VLAN_VAWD2 0x98
2905 +#define REG_ESW_VLAN_VTIM(x) (0x100 + 4 * ((x) / 2))
2906 +
2907 +#define REG_ESW_VLAN_VAWD1_IVL_MAC BIT(30)
2908 +#define REG_ESW_VLAN_VAWD1_VTAG_EN BIT(28)
2909 +#define REG_ESW_VLAN_VAWD1_VALID BIT(0)
2910 +
2911 +/* vlan egress mode */
2912 +enum {
2913 + ETAG_CTRL_UNTAG = 0,
2914 + ETAG_CTRL_TAG = 2,
2915 + ETAG_CTRL_SWAP = 1,
2916 + ETAG_CTRL_STACK = 3,
2917 +};
2918 +
2919 +#define REG_ESW_PORT_PCR(x) (0x2004 | ((x) << 8))
2920 +#define REG_ESW_PORT_PVC(x) (0x2010 | ((x) << 8))
2921 +#define REG_ESW_PORT_PPBV1(x) (0x2014 | ((x) << 8))
2922 +enum {
2923 + /* Global attributes. */
2924 + MT7530_ATTR_ENABLE_VLAN,
2925 +};
2926 +
2927 +struct mt7530_port_entry {
2928 + u16 pvid;
2929 +};
2930 +
2931 +struct mt7530_vlan_entry {
2932 + u16 vid;
2933 + u8 member;
2934 + u8 etags;
2935 +};
2936 +
2937 +struct mt7530_priv {
2938 + void __iomem *base;
2939 + struct mii_bus *bus;
2940 + struct switch_dev swdev;
2941 +
2942 + bool global_vlan_enable;
2943 + struct mt7530_vlan_entry vlan_entries[MT7530_NUM_VLANS];
2944 + struct mt7530_port_entry port_entries[MT7530_NUM_PORTS];
2945 +};
2946 +
2947 +struct mt7530_mapping {
2948 + char *name;
2949 + u16 pvids[MT7530_NUM_PORTS];
2950 + u8 members[MT7530_NUM_VLANS];
2951 + u8 etags[MT7530_NUM_VLANS];
2952 + u16 vids[MT7530_NUM_VLANS];
2953 +} mt7530_defaults[] = {
2954 + {
2955 + .name = "llllw",
2956 + .pvids = { 1, 1, 1, 1, 2, 1, 1 },
2957 + .members = { 0, 0x6f, 0x50 },
2958 + .etags = { 0, 0x40, 0x40 },
2959 + .vids = { 0, 1, 2 },
2960 + }, {
2961 + .name = "wllll",
2962 + .pvids = { 2, 1, 1, 1, 1, 1, 1 },
2963 + .members = { 0, 0x7e, 0x41 },
2964 + .etags = { 0, 0x40, 0x40 },
2965 + .vids = { 0, 1, 2 },
2966 + },
2967 +};
2968 +
2969 +struct mt7530_mapping*
2970 +mt7530_find_mapping(struct device_node *np)
2971 +{
2972 + const char *map;
2973 + int i;
2974 +
2975 + if (of_property_read_string(np, "ralink,port-map", &map))
2976 + return NULL;
2977 +
2978 + for (i = 0; i < ARRAY_SIZE(mt7530_defaults); i++)
2979 + if (!strcmp(map, mt7530_defaults[i].name))
2980 + return &mt7530_defaults[i];
2981 +
2982 + return NULL;
2983 +}
2984 +
2985 +static void
2986 +mt7530_apply_mapping(struct mt7530_priv *mt7530, struct mt7530_mapping *map)
2987 +{
2988 + int i = 0;
2989 +
2990 + mt7530->global_vlan_enable = 1;
2991 +
2992 + for (i = 0; i < MT7530_NUM_PORTS; i++)
2993 + mt7530->port_entries[i].pvid = map->pvids[i];
2994 +
2995 + for (i = 0; i < MT7530_NUM_VLANS; i++) {
2996 + mt7530->vlan_entries[i].member = map->members[i];
2997 + mt7530->vlan_entries[i].etags = map->etags[i];
2998 + mt7530->vlan_entries[i].vid = map->vids[i];
2999 + }
3000 +}
3001 +
3002 +static int
3003 +mt7530_reset_switch(struct switch_dev *dev)
3004 +{
3005 + struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
3006 + int i;
3007 +
3008 + memset(priv->port_entries, 0, sizeof(priv->port_entries));
3009 + memset(priv->vlan_entries, 0, sizeof(priv->vlan_entries));
3010 +
3011 + /* set default vid of each vlan to the same number of vlan, so the vid
3012 + * won't need be set explicitly.
3013 + */
3014 + for (i = 0; i < MT7530_NUM_VLANS; i++) {
3015 + priv->vlan_entries[i].vid = i;
3016 + }
3017 +
3018 + return 0;
3019 +}
3020 +
3021 +static int
3022 +mt7530_get_vlan_enable(struct switch_dev *dev,
3023 + const struct switch_attr *attr,
3024 + struct switch_val *val)
3025 +{
3026 + struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
3027 +
3028 + val->value.i = priv->global_vlan_enable;
3029 +
3030 + return 0;
3031 +}
3032 +
3033 +static int
3034 +mt7530_set_vlan_enable(struct switch_dev *dev,
3035 + const struct switch_attr *attr,
3036 + struct switch_val *val)
3037 +{
3038 + struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
3039 +
3040 + priv->global_vlan_enable = val->value.i != 0;
3041 +
3042 + return 0;
3043 +}
3044 +
3045 +static u32
3046 +mt7530_r32(struct mt7530_priv *priv, u32 reg)
3047 +{
3048 + u32 val;
3049 + if (priv->bus) {
3050 + u16 high, low;
3051 +
3052 + mdiobus_write(priv->bus, 0x1f, 0x1f, (reg >> 6) & 0x3ff);
3053 + low = mdiobus_read(priv->bus, 0x1f, (reg >> 2) & 0xf);
3054 + high = mdiobus_read(priv->bus, 0x1f, 0x10);
3055 +
3056 + return (high << 16) | (low & 0xffff);
3057 + }
3058 +
3059 + val = ioread32(priv->base + reg);
3060 + pr_debug("MT7530 MDIO Read [%04x]=%08x\n", reg, val);
3061 +
3062 + return val;
3063 +}
3064 +
3065 +static void
3066 +mt7530_w32(struct mt7530_priv *priv, u32 reg, u32 val)
3067 +{
3068 + if (priv->bus) {
3069 + mdiobus_write(priv->bus, 0x1f, 0x1f, (reg >> 6) & 0x3ff);
3070 + mdiobus_write(priv->bus, 0x1f, (reg >> 2) & 0xf, val & 0xffff);
3071 + mdiobus_write(priv->bus, 0x1f, 0x10, val >> 16);
3072 + return;
3073 + }
3074 +
3075 + pr_debug("MT7530 MDIO Write[%04x]=%08x\n", reg, val);
3076 + iowrite32(val, priv->base + reg);
3077 +}
3078 +
3079 +static void
3080 +mt7530_vtcr(struct mt7530_priv *priv, u32 cmd, u32 val)
3081 +{
3082 + int i;
3083 +
3084 + mt7530_w32(priv, REG_ESW_VLAN_VTCR, BIT(31) | (cmd << 12) | val);
3085 +
3086 + for (i = 0; i < 20; i++) {
3087 + u32 val = mt7530_r32(priv, REG_ESW_VLAN_VTCR);
3088 +
3089 + if ((val & BIT(31)) == 0)
3090 + break;
3091 +
3092 + udelay(1000);
3093 + }
3094 + if (i == 20)
3095 + printk("mt7530: vtcr timeout\n");
3096 +}
3097 +
3098 +static int
3099 +mt7530_get_port_pvid(struct switch_dev *dev, int port, int *val)
3100 +{
3101 + struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
3102 +
3103 + if (port >= MT7530_NUM_PORTS)
3104 + return -EINVAL;
3105 +
3106 + *val = mt7530_r32(priv, REG_ESW_PORT_PPBV1(port));
3107 + *val &= 0xfff;
3108 +
3109 + return 0;
3110 +}
3111 +
3112 +static int
3113 +mt7530_set_port_pvid(struct switch_dev *dev, int port, int pvid)
3114 +{
3115 + struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
3116 +
3117 + if (port >= MT7530_NUM_PORTS)
3118 + return -EINVAL;
3119 +
3120 + if (pvid < MT7530_MIN_VID || pvid > MT7530_MAX_VID)
3121 + return -EINVAL;
3122 +
3123 + priv->port_entries[port].pvid = pvid;
3124 +
3125 + return 0;
3126 +}
3127 +
3128 +static int
3129 +mt7530_get_vlan_ports(struct switch_dev *dev, struct switch_val *val)
3130 +{
3131 + struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
3132 + u32 member;
3133 + u32 etags;
3134 + int i;
3135 +
3136 + val->len = 0;
3137 +
3138 + if (val->port_vlan < 0 || val->port_vlan >= MT7530_NUM_VLANS)
3139 + return -EINVAL;
3140 +
3141 + mt7530_vtcr(priv, 0, val->port_vlan);
3142 +
3143 + member = mt7530_r32(priv, REG_ESW_VLAN_VAWD1);
3144 + member >>= 16;
3145 + member &= 0xff;
3146 +
3147 + etags = mt7530_r32(priv, REG_ESW_VLAN_VAWD2);
3148 +
3149 + for (i = 0; i < MT7530_NUM_PORTS; i++) {
3150 + struct switch_port *p;
3151 + int etag;
3152 +
3153 + if (!(member & BIT(i)))
3154 + continue;
3155 +
3156 + p = &val->value.ports[val->len++];
3157 + p->id = i;
3158 +
3159 + etag = (etags >> (i * 2)) & 0x3;
3160 +
3161 + if (etag == ETAG_CTRL_TAG)
3162 + p->flags |= BIT(SWITCH_PORT_FLAG_TAGGED);
3163 + else if (etag != ETAG_CTRL_UNTAG)
3164 + printk("vlan egress tag control neither untag nor tag.\n");
3165 + }
3166 +
3167 + return 0;
3168 +}
3169 +
3170 +static int
3171 +mt7530_set_vlan_ports(struct switch_dev *dev, struct switch_val *val)
3172 +{
3173 + struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
3174 + u8 member = 0;
3175 + u8 etags = 0;
3176 + int i;
3177 +
3178 + if (val->port_vlan < 0 || val->port_vlan >= MT7530_NUM_VLANS ||
3179 + val->len > MT7530_NUM_PORTS)
3180 + return -EINVAL;
3181 +
3182 + for (i = 0; i < val->len; i++) {
3183 + struct switch_port *p = &val->value.ports[i];
3184 +
3185 + if (p->id >= MT7530_NUM_PORTS)
3186 + return -EINVAL;
3187 +
3188 + member |= BIT(p->id);
3189 +
3190 + if (p->flags & BIT(SWITCH_PORT_FLAG_TAGGED))
3191 + etags |= BIT(p->id);
3192 + }
3193 + priv->vlan_entries[val->port_vlan].member = member;
3194 + priv->vlan_entries[val->port_vlan].etags = etags;
3195 +
3196 + return 0;
3197 +}
3198 +
3199 +static int
3200 +mt7530_set_vid(struct switch_dev *dev, const struct switch_attr *attr,
3201 + struct switch_val *val)
3202 +{
3203 + struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
3204 + int vlan;
3205 + u16 vid;
3206 +
3207 + vlan = val->port_vlan;
3208 + vid = (u16)val->value.i;
3209 +
3210 + if (vlan < 0 || vlan >= MT7530_NUM_VLANS)
3211 + return -EINVAL;
3212 +
3213 + if (vid < MT7530_MIN_VID || vid > MT7530_MAX_VID)
3214 + return -EINVAL;
3215 +
3216 + priv->vlan_entries[vlan].vid = vid;
3217 + return 0;
3218 +}
3219 +
3220 +static int
3221 +mt7530_get_vid(struct switch_dev *dev, const struct switch_attr *attr,
3222 + struct switch_val *val)
3223 +{
3224 + struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
3225 + u32 vid;
3226 + int vlan;
3227 +
3228 + vlan = val->port_vlan;
3229 +
3230 + vid = mt7530_r32(priv, REG_ESW_VLAN_VTIM(vlan));
3231 + if (vlan & 1)
3232 + vid = vid >> 12;
3233 + vid &= 0xfff;
3234 +
3235 + val->value.i = vid;
3236 + return 0;
3237 +}
3238 +
3239 +static int
3240 +mt7530_apply_config(struct switch_dev *dev)
3241 +{
3242 + struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
3243 + int i, j;
3244 +
3245 + if (!priv->global_vlan_enable) {
3246 + for (i = 0; i < MT7530_NUM_PORTS; i++)
3247 + mt7530_w32(priv, REG_ESW_PORT_PCR(i), 0x00ff0000);
3248 +
3249 + for (i = 0; i < MT7530_NUM_PORTS; i++)
3250 + mt7530_w32(priv, REG_ESW_PORT_PVC(i), 0x8100000c);
3251 +
3252 + return 0;
3253 + }
3254 +
3255 + /* set all ports as security mode */
3256 + for (i = 0; i < MT7530_NUM_PORTS; i++)
3257 + mt7530_w32(priv, REG_ESW_PORT_PCR(i), 0x00ff0003);
3258 +
3259 + /* set all ports as user port */
3260 + for (i = 0; i < MT7530_NUM_PORTS; i++)
3261 + mt7530_w32(priv, REG_ESW_PORT_PVC(i), 0x81000000);
3262 +
3263 + for (i = 0; i < MT7530_NUM_VLANS; i++) {
3264 + u16 vid = priv->vlan_entries[i].vid;
3265 + u8 member = priv->vlan_entries[i].member;
3266 + u8 etags = priv->vlan_entries[i].etags;
3267 + u32 val;
3268 +
3269 + /* vid of vlan */
3270 + val = mt7530_r32(priv, REG_ESW_VLAN_VTIM(i));
3271 + if (i % 2 == 0) {
3272 + val &= 0xfff000;
3273 + val |= vid;
3274 + } else {
3275 + val &= 0xfff;
3276 + val |= (vid << 12);
3277 + }
3278 + mt7530_w32(priv, REG_ESW_VLAN_VTIM(i), val);
3279 +
3280 + /* vlan port membership */
3281 + if (member)
3282 + mt7530_w32(priv, REG_ESW_VLAN_VAWD1, REG_ESW_VLAN_VAWD1_IVL_MAC |
3283 + REG_ESW_VLAN_VAWD1_VTAG_EN | (member << 16) |
3284 + REG_ESW_VLAN_VAWD1_VALID);
3285 + else
3286 + mt7530_w32(priv, REG_ESW_VLAN_VAWD1, 0);
3287 +
3288 + /* egress mode */
3289 + val = 0;
3290 + for (j = 0; j < MT7530_NUM_PORTS; j++) {
3291 + if (etags & BIT(j))
3292 + val |= ETAG_CTRL_TAG << (j * 2);
3293 + else
3294 + val |= ETAG_CTRL_UNTAG << (j * 2);
3295 + }
3296 + mt7530_w32(priv, REG_ESW_VLAN_VAWD2, val);
3297 +
3298 + /* write to vlan table */
3299 + mt7530_vtcr(priv, 1, i);
3300 + }
3301 +
3302 + /* Port Default PVID */
3303 + for (i = 0; i < MT7530_NUM_PORTS; i++) {
3304 + u32 val;
3305 + val = mt7530_r32(priv, REG_ESW_PORT_PPBV1(i));
3306 + val &= ~0xfff;
3307 + val |= priv->port_entries[i].pvid;
3308 + mt7530_w32(priv, REG_ESW_PORT_PPBV1(i), val);
3309 + }
3310 +
3311 + return 0;
3312 +}
3313 +
3314 +static int
3315 +mt7530_get_port_link(struct switch_dev *dev, int port,
3316 + struct switch_port_link *link)
3317 +{
3318 + struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
3319 + u32 speed, pmsr;
3320 +
3321 + if (port < 0 || port >= MT7530_NUM_PORTS)
3322 + return -EINVAL;
3323 +
3324 + pmsr = mt7530_r32(priv, 0x3008 + (0x100 * port));
3325 +
3326 + link->link = pmsr & 1;
3327 + link->duplex = (pmsr >> 1) & 1;
3328 + speed = (pmsr >> 2) & 3;
3329 +
3330 + switch (speed) {
3331 + case 0:
3332 + link->speed = SWITCH_PORT_SPEED_10;
3333 + break;
3334 + case 1:
3335 + link->speed = SWITCH_PORT_SPEED_100;
3336 + break;
3337 + case 2:
3338 + case 3: /* forced gige speed can be 2 or 3 */
3339 + link->speed = SWITCH_PORT_SPEED_1000;
3340 + break;
3341 + default:
3342 + link->speed = SWITCH_PORT_SPEED_UNKNOWN;
3343 + break;
3344 + }
3345 +
3346 + return 0;
3347 +}
3348 +
3349 +static const struct switch_attr mt7530_global[] = {
3350 + {
3351 + .type = SWITCH_TYPE_INT,
3352 + .name = "enable_vlan",
3353 + .description = "VLAN mode (1:enabled)",
3354 + .max = 1,
3355 + .id = MT7530_ATTR_ENABLE_VLAN,
3356 + .get = mt7530_get_vlan_enable,
3357 + .set = mt7530_set_vlan_enable,
3358 + },
3359 +};
3360 +
3361 +static const struct switch_attr mt7530_port[] = {
3362 +};
3363 +
3364 +static const struct switch_attr mt7530_vlan[] = {
3365 + {
3366 + .type = SWITCH_TYPE_INT,
3367 + .name = "vid",
3368 + .description = "VLAN ID (0-4094)",
3369 + .set = mt7530_set_vid,
3370 + .get = mt7530_get_vid,
3371 + .max = 4094,
3372 + },
3373 +};
3374 +
3375 +static const struct switch_dev_ops mt7530_ops = {
3376 + .attr_global = {
3377 + .attr = mt7530_global,
3378 + .n_attr = ARRAY_SIZE(mt7530_global),
3379 + },
3380 + .attr_port = {
3381 + .attr = mt7530_port,
3382 + .n_attr = ARRAY_SIZE(mt7530_port),
3383 + },
3384 + .attr_vlan = {
3385 + .attr = mt7530_vlan,
3386 + .n_attr = ARRAY_SIZE(mt7530_vlan),
3387 + },
3388 + .get_vlan_ports = mt7530_get_vlan_ports,
3389 + .set_vlan_ports = mt7530_set_vlan_ports,
3390 + .get_port_pvid = mt7530_get_port_pvid,
3391 + .set_port_pvid = mt7530_set_port_pvid,
3392 + .get_port_link = mt7530_get_port_link,
3393 + .apply_config = mt7530_apply_config,
3394 + .reset_switch = mt7530_reset_switch,
3395 +};
3396 +
3397 +int
3398 +mt7530_probe(struct device *dev, void __iomem *base, struct mii_bus *bus)
3399 +{
3400 + struct switch_dev *swdev;
3401 + struct mt7530_priv *mt7530;
3402 + struct mt7530_mapping *map;
3403 + int ret;
3404 +
3405 + if (bus && bus->phy_map[0x1f]->phy_id != 0x1beef)
3406 + return 0;
3407 +
3408 + mt7530 = devm_kzalloc(dev, sizeof(struct mt7530_priv), GFP_KERNEL);
3409 + if (!mt7530)
3410 + return -ENOMEM;
3411 +
3412 + mt7530->base = base;
3413 + mt7530->bus = bus;
3414 + mt7530->global_vlan_enable = 1;
3415 +
3416 + swdev = &mt7530->swdev;
3417 + swdev->name = "mt7530";
3418 + swdev->alias = "mt7530";
3419 + swdev->cpu_port = MT7530_CPU_PORT;
3420 + swdev->ports = MT7530_NUM_PORTS;
3421 + swdev->vlans = MT7530_NUM_VLANS;
3422 + swdev->ops = &mt7530_ops;
3423 +
3424 + ret = register_switch(swdev, NULL);
3425 + if (ret) {
3426 + dev_err(dev, "failed to register mt7530\n");
3427 + return ret;
3428 + }
3429 +
3430 + dev_info(dev, "loaded mt7530 driver\n");
3431 +
3432 + map = mt7530_find_mapping(dev->of_node);
3433 + if (map)
3434 + mt7530_apply_mapping(mt7530, map);
3435 + mt7530_apply_config(swdev);
3436 +
3437 + return 0;
3438 +}
3439 diff --git a/drivers/net/ethernet/ralink/mt7530.h b/drivers/net/ethernet/ralink/mt7530.h
3440 new file mode 100644
3441 index 0000000..169b888
3442 --- /dev/null
3443 +++ b/drivers/net/ethernet/ralink/mt7530.h
3444 @@ -0,0 +1,20 @@
3445 +/*
3446 + * This program is free software; you can redistribute it and/or
3447 + * modify it under the terms of the GNU General Public License
3448 + * as published by the Free Software Foundation; either version 2
3449 + * of the License, or (at your option) any later version.
3450 + *
3451 + * This program is distributed in the hope that it will be useful,
3452 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
3453 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
3454 + * GNU General Public License for more details.
3455 + *
3456 + * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
3457 + */
3458 +
3459 +#ifndef _MT7530_H__
3460 +#define _MT7530_H__
3461 +
3462 +int mt7530_probe(struct device *dev, void __iomem *base, struct mii_bus *bus);
3463 +
3464 +#endif
3465 diff --git a/drivers/net/ethernet/ralink/ralink_soc_eth.c b/drivers/net/ethernet/ralink/ralink_soc_eth.c
3466 new file mode 100644
3467 index 0000000..f3abab7
3468 --- /dev/null
3469 +++ b/drivers/net/ethernet/ralink/ralink_soc_eth.c
3470 @@ -0,0 +1,844 @@
3471 +/*
3472 + * This program is free software; you can redistribute it and/or modify
3473 + * it under the terms of the GNU General Public License as published by
3474 + * the Free Software Foundation; version 2 of the License
3475 + *
3476 + * This program is distributed in the hope that it will be useful,
3477 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
3478 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
3479 + * GNU General Public License for more details.
3480 + *
3481 + * You should have received a copy of the GNU General Public License
3482 + * along with this program; if not, write to the Free Software
3483 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
3484 + *
3485 + * Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
3486 + */
3487 +
3488 +#include <linux/module.h>
3489 +#include <linux/kernel.h>
3490 +#include <linux/types.h>
3491 +#include <linux/dma-mapping.h>
3492 +#include <linux/init.h>
3493 +#include <linux/skbuff.h>
3494 +#include <linux/etherdevice.h>
3495 +#include <linux/ethtool.h>
3496 +#include <linux/platform_device.h>
3497 +#include <linux/of_device.h>
3498 +#include <linux/clk.h>
3499 +#include <linux/of_net.h>
3500 +#include <linux/of_mdio.h>
3501 +#include <linux/if_vlan.h>
3502 +#include <linux/reset.h>
3503 +
3504 +#include <asm/mach-ralink/ralink_regs.h>
3505 +
3506 +#include "ralink_soc_eth.h"
3507 +#include "esw_rt3052.h"
3508 +#include "mdio.h"
3509 +
3510 +#define TX_TIMEOUT (2 * HZ)
3511 +#define MAX_RX_LENGTH 1536
3512 +#define DMA_DUMMY_DESC 0xffffffff
3513 +
3514 +static const u32 fe_reg_table_default[FE_REG_COUNT] = {
3515 + [FE_REG_PDMA_GLO_CFG] = FE_PDMA_GLO_CFG,
3516 + [FE_REG_PDMA_RST_CFG] = FE_PDMA_RST_CFG,
3517 + [FE_REG_DLY_INT_CFG] = FE_DLY_INT_CFG,
3518 + [FE_REG_TX_BASE_PTR0] = FE_TX_BASE_PTR0,
3519 + [FE_REG_TX_MAX_CNT0] = FE_TX_MAX_CNT0,
3520 + [FE_REG_TX_CTX_IDX0] = FE_TX_CTX_IDX0,
3521 + [FE_REG_RX_BASE_PTR0] = FE_RX_BASE_PTR0,
3522 + [FE_REG_RX_MAX_CNT0] = FE_RX_MAX_CNT0,
3523 + [FE_REG_RX_CALC_IDX0] = FE_RX_CALC_IDX0,
3524 + [FE_REG_FE_INT_ENABLE] = FE_FE_INT_ENABLE,
3525 + [FE_REG_FE_INT_STATUS] = FE_FE_INT_STATUS,
3526 +};
3527 +
3528 +static const u32 *fe_reg_table = fe_reg_table_default;
3529 +
3530 +static void __iomem *fe_base = 0;
3531 +
3532 +void fe_w32(u32 val, unsigned reg)
3533 +{
3534 + __raw_writel(val, fe_base + reg);
3535 +}
3536 +
3537 +u32 fe_r32(unsigned reg)
3538 +{
3539 + return __raw_readl(fe_base + reg);
3540 +}
3541 +
3542 +static inline void fe_reg_w32(u32 val, enum fe_reg reg)
3543 +{
3544 + fe_w32(val, fe_reg_table[reg]);
3545 +}
3546 +
3547 +static inline u32 fe_reg_r32(enum fe_reg reg)
3548 +{
3549 + return fe_r32(fe_reg_table[reg]);
3550 +}
3551 +
3552 +static inline void fe_int_disable(u32 mask)
3553 +{
3554 + fe_reg_w32(fe_reg_r32(FE_REG_FE_INT_ENABLE) & ~mask,
3555 + FE_REG_FE_INT_ENABLE);
3556 + /* flush write */
3557 + fe_reg_r32(FE_REG_FE_INT_ENABLE);
3558 +}
3559 +
3560 +static inline void fe_int_enable(u32 mask)
3561 +{
3562 + fe_reg_w32(fe_reg_r32(FE_REG_FE_INT_ENABLE) | mask,
3563 + FE_REG_FE_INT_ENABLE);
3564 + /* flush write */
3565 + fe_reg_r32(FE_REG_FE_INT_ENABLE);
3566 +}
3567 +
3568 +static inline void fe_hw_set_macaddr(struct fe_priv *priv, unsigned char *mac)
3569 +{
3570 + unsigned long flags;
3571 +
3572 + spin_lock_irqsave(&priv->page_lock, flags);
3573 + fe_w32((mac[0] << 8) | mac[1], FE_GDMA1_MAC_ADRH);
3574 + fe_w32((mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5],
3575 + FE_GDMA1_MAC_ADRL);
3576 + spin_unlock_irqrestore(&priv->page_lock, flags);
3577 +}
3578 +
3579 +static int fe_set_mac_address(struct net_device *dev, void *p)
3580 +{
3581 + int ret = eth_mac_addr(dev, p);
3582 +
3583 + if (!ret) {
3584 + struct fe_priv *priv = netdev_priv(dev);
3585 +
3586 + if (priv->soc->set_mac)
3587 + priv->soc->set_mac(priv, dev->dev_addr);
3588 + else
3589 + fe_hw_set_macaddr(priv, p);
3590 + }
3591 +
3592 + return ret;
3593 +}
3594 +
3595 +static struct sk_buff* fe_alloc_skb(struct fe_priv *priv)
3596 +{
3597 + struct sk_buff *skb;
3598 +
3599 + skb = netdev_alloc_skb(priv->netdev, MAX_RX_LENGTH + NET_IP_ALIGN);
3600 + if (!skb)
3601 + return NULL;
3602 +
3603 + skb_reserve(skb, NET_IP_ALIGN);
3604 +
3605 + return skb;
3606 +}
3607 +
3608 +static int fe_alloc_rx(struct fe_priv *priv)
3609 +{
3610 + int size = NUM_DMA_DESC * sizeof(struct fe_rx_dma);
3611 + int i;
3612 +
3613 + priv->rx_dma = dma_alloc_coherent(&priv->netdev->dev, size,
3614 + &priv->rx_phys, GFP_ATOMIC);
3615 + if (!priv->rx_dma)
3616 + return -ENOMEM;
3617 +
3618 + memset(priv->rx_dma, 0, size);
3619 +
3620 + for (i = 0; i < NUM_DMA_DESC; i++) {
3621 + priv->rx_skb[i] = fe_alloc_skb(priv);
3622 + if (!priv->rx_skb[i])
3623 + return -ENOMEM;
3624 + }
3625 +
3626 + for (i = 0; i < NUM_DMA_DESC; i++) {
3627 + dma_addr_t dma_addr = dma_map_single(&priv->netdev->dev,
3628 + priv->rx_skb[i]->data,
3629 + MAX_RX_LENGTH,
3630 + DMA_FROM_DEVICE);
3631 + priv->rx_dma[i].rxd1 = (unsigned int) dma_addr;
3632 +
3633 + if (priv->soc->rx_dma)
3634 + priv->soc->rx_dma(priv, i, MAX_RX_LENGTH);
3635 + else
3636 + priv->rx_dma[i].rxd2 = RX_DMA_LSO;
3637 + }
3638 + wmb();
3639 +
3640 + fe_reg_w32(priv->rx_phys, FE_REG_RX_BASE_PTR0);
3641 + fe_reg_w32(NUM_DMA_DESC, FE_REG_RX_MAX_CNT0);
3642 + fe_reg_w32((NUM_DMA_DESC - 1), FE_REG_RX_CALC_IDX0);
3643 + fe_reg_w32(FE_PST_DRX_IDX0, FE_REG_PDMA_RST_CFG);
3644 +
3645 + return 0;
3646 +}
3647 +
3648 +static int fe_alloc_tx(struct fe_priv *priv)
3649 +{
3650 + int size = NUM_DMA_DESC * sizeof(struct fe_tx_dma);
3651 + int i;
3652 +
3653 + priv->tx_free_idx = 0;
3654 +
3655 + priv->tx_dma = dma_alloc_coherent(&priv->netdev->dev, size,
3656 + &priv->tx_phys, GFP_ATOMIC);
3657 + if (!priv->tx_dma)
3658 + return -ENOMEM;
3659 +
3660 + memset(priv->tx_dma, 0, size);
3661 +
3662 + for (i = 0; i < NUM_DMA_DESC; i++) {
3663 + if (priv->soc->tx_dma) {
3664 + priv->soc->tx_dma(priv, i, NULL);
3665 + continue;
3666 + }
3667 +
3668 + priv->tx_dma[i].txd2 = TX_DMA_LSO | TX_DMA_DONE;
3669 + priv->tx_dma[i].txd4 = TX_DMA_QN(3) | TX_DMA_PN(1);
3670 + }
3671 +
3672 + fe_reg_w32(priv->tx_phys, FE_REG_TX_BASE_PTR0);
3673 + fe_reg_w32(NUM_DMA_DESC, FE_REG_TX_MAX_CNT0);
3674 + fe_reg_w32(0, FE_REG_TX_CTX_IDX0);
3675 + fe_reg_w32(FE_PST_DTX_IDX0, FE_REG_PDMA_RST_CFG);
3676 +
3677 + return 0;
3678 +}
3679 +
3680 +static void fe_free_dma(struct fe_priv *priv)
3681 +{
3682 + int i;
3683 +
3684 + for (i = 0; i < NUM_DMA_DESC; i++) {
3685 + if (priv->rx_skb[i]) {
3686 + dma_unmap_single(&priv->netdev->dev, priv->rx_dma[i].rxd1,
3687 + MAX_RX_LENGTH, DMA_FROM_DEVICE);
3688 + dev_kfree_skb_any(priv->rx_skb[i]);
3689 + priv->rx_skb[i] = NULL;
3690 + }
3691 +
3692 + if (priv->tx_skb[i]) {
3693 + dev_kfree_skb_any(priv->tx_skb[i]);
3694 + priv->tx_skb[i] = NULL;
3695 + }
3696 + }
3697 +
3698 + if (priv->rx_dma) {
3699 + int size = NUM_DMA_DESC * sizeof(struct fe_rx_dma);
3700 + dma_free_coherent(&priv->netdev->dev, size, priv->rx_dma,
3701 + priv->rx_phys);
3702 + }
3703 +
3704 + if (priv->tx_dma) {
3705 + int size = NUM_DMA_DESC * sizeof(struct fe_tx_dma);
3706 + dma_free_coherent(&priv->netdev->dev, size, priv->tx_dma,
3707 + priv->tx_phys);
3708 + }
3709 +
3710 + netdev_reset_queue(priv->netdev);
3711 +}
3712 +
3713 +static void fe_start_tso(struct sk_buff *skb, struct net_device *dev, unsigned int nr_frags, int idx)
3714 +{
3715 + struct fe_priv *priv = netdev_priv(dev);
3716 + struct skb_frag_struct *frag;
3717 + int i;
3718 +
3719 + for (i = 0; i < nr_frags; i++) {
3720 + dma_addr_t mapped_addr;
3721 +
3722 + frag = &skb_shinfo(skb)->frags[i];
3723 + mapped_addr = skb_frag_dma_map(&dev->dev, frag, 0, skb_frag_size(frag), DMA_TO_DEVICE);
3724 + if (i % 2) {
3725 + idx = (idx + 1) % NUM_DMA_DESC;
3726 + priv->tx_dma[idx].txd1 = mapped_addr;
3727 + if (i == nr_frags - 1)
3728 + priv->tx_dma[idx].txd2 = TX_DMA_LSO | TX_DMA_PLEN0(frag->size);
3729 + else
3730 + priv->tx_dma[idx].txd2 = TX_DMA_PLEN0(frag->size);
3731 + } else {
3732 + priv->tx_dma[idx].txd3 = mapped_addr;
3733 + if (i == nr_frags - 1)
3734 + priv->tx_dma[idx].txd2 |= TX_DMA_LS1 | TX_DMA_PLEN1(frag->size);
3735 + else
3736 + priv->tx_dma[idx].txd2 |= TX_DMA_PLEN1(frag->size);
3737 + }
3738 + }
3739 +}
3740 +
3741 +static int fe_start_xmit(struct sk_buff *skb, struct net_device *dev)
3742 +{
3743 + unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
3744 + struct fe_priv *priv = netdev_priv(dev);
3745 + dma_addr_t mapped_addr;
3746 + u32 tx_next, tx, tx_num = 1;
3747 + int i;
3748 +
3749 + if (priv->soc->min_pkt_len) {
3750 + if (skb->len < priv->soc->min_pkt_len) {
3751 + if (skb_padto(skb, priv->soc->min_pkt_len)) {
3752 + printk(KERN_ERR
3753 + "fe_eth: skb_padto failed\n");
3754 + kfree_skb(skb);
3755 + return 0;
3756 + }
3757 + skb_put(skb, priv->soc->min_pkt_len - skb->len);
3758 + }
3759 + }
3760 +
3761 + dev->trans_start = jiffies;
3762 + mapped_addr = dma_map_single(&priv->netdev->dev, skb->data,
3763 + skb->len, DMA_TO_DEVICE);
3764 +
3765 + spin_lock(&priv->page_lock);
3766 +
3767 + tx = fe_reg_r32(FE_REG_TX_CTX_IDX0);
3768 + if (priv->soc->tso && nr_frags)
3769 + tx_num += nr_frags >> 1;
3770 + tx_next = (tx + tx_num) % NUM_DMA_DESC;
3771 + if ((priv->tx_skb[tx]) || (priv->tx_skb[tx_next]) ||
3772 + !(priv->tx_dma[tx].txd2 & TX_DMA_DONE) ||
3773 + !(priv->tx_dma[tx_next].txd2 & TX_DMA_DONE))
3774 + {
3775 + spin_unlock(&priv->page_lock);
3776 + dev->stats.tx_dropped++;
3777 + kfree_skb(skb);
3778 +
3779 + return NETDEV_TX_OK;
3780 + }
3781 +
3782 + if (priv->soc->tso) {
3783 + int t = tx_num;
3784 +
3785 + priv->tx_skb[(tx + t - 1) % NUM_DMA_DESC] = skb;
3786 + while (--t)
3787 + priv->tx_skb[(tx + t - 1) % NUM_DMA_DESC] = (struct sk_buff *) DMA_DUMMY_DESC;
3788 + } else {
3789 + priv->tx_skb[tx] = skb;
3790 + }
3791 + priv->tx_dma[tx].txd1 = (unsigned int) mapped_addr;
3792 + wmb();
3793 +
3794 + priv->tx_dma[tx].txd4 &= ~0x80;
3795 + if (priv->soc->tx_dma)
3796 + priv->soc->tx_dma(priv, tx, skb);
3797 + else
3798 + priv->tx_dma[tx].txd2 = TX_DMA_LSO | TX_DMA_PLEN0(skb->len);
3799 +
3800 + if (skb->ip_summed == CHECKSUM_PARTIAL)
3801 + priv->tx_dma[tx].txd4 |= TX_DMA_CHKSUM;
3802 + else
3803 + priv->tx_dma[tx].txd4 &= ~TX_DMA_CHKSUM;
3804 +
3805 + if (priv->soc->tso)
3806 + fe_start_tso(skb, dev, nr_frags, tx);
3807 +
3808 + if (priv->soc->tso && (skb_shinfo(skb)->gso_segs > 1)) {
3809 + struct iphdr *iph = NULL;
3810 + struct tcphdr *th = NULL;
3811 + struct ipv6hdr *ip6h = NULL;
3812 +
3813 + ip6h = (struct ipv6hdr *) skb_network_header(skb);
3814 + iph = (struct iphdr *) skb_network_header(skb);
3815 + if ((iph->version == 4) && (iph->protocol == IPPROTO_TCP)) {
3816 + th = (struct tcphdr *)skb_transport_header(skb);
3817 + priv->tx_dma[tx].txd4 |= BIT(28);
3818 + th->check = htons(skb_shinfo(skb)->gso_size);
3819 + dma_cache_sync(NULL, th, sizeof(struct tcphdr), DMA_TO_DEVICE);
3820 + } else if ((ip6h->version == 6) && (ip6h->nexthdr == NEXTHDR_TCP)) {
3821 + th = (struct tcphdr *)skb_transport_header(skb);
3822 + priv->tx_dma[tx].txd4 |= BIT(28);
3823 + th->check = htons(skb_shinfo(skb)->gso_size);
3824 + dma_cache_sync(NULL, th, sizeof(struct tcphdr), DMA_TO_DEVICE);
3825 + }
3826 + }
3827 +
3828 + for (i = 0; i < tx_num; i++)
3829 + dma_cache_sync(NULL, &priv->tx_dma[tx + i], sizeof(struct fe_tx_dma), DMA_TO_DEVICE);
3830 +
3831 + dev->stats.tx_packets++;
3832 + dev->stats.tx_bytes += skb->len;
3833 +
3834 + wmb();
3835 + fe_reg_w32(tx_next, FE_REG_TX_CTX_IDX0);
3836 + netdev_sent_queue(dev, skb->len);
3837 +
3838 + spin_unlock(&priv->page_lock);
3839 +
3840 + return NETDEV_TX_OK;
3841 +}
3842 +
3843 +static int fe_poll_rx(struct napi_struct *napi, int budget)
3844 +{
3845 + struct fe_priv *priv = container_of(napi, struct fe_priv, rx_napi);
3846 + int idx = fe_reg_r32(FE_REG_RX_CALC_IDX0);
3847 + int complete = 0;
3848 + int rx = 0;
3849 +
3850 + while ((rx < budget) && !complete) {
3851 + idx = (idx + 1) % NUM_DMA_DESC;
3852 +
3853 + if (priv->rx_dma[idx].rxd2 & RX_DMA_DONE) {
3854 + struct sk_buff *new_skb = fe_alloc_skb(priv);
3855 +
3856 + if (new_skb) {
3857 + int pktlen = RX_DMA_PLEN0(priv->rx_dma[idx].rxd2);
3858 + dma_addr_t dma_addr;
3859 +
3860 + dma_unmap_single(&priv->netdev->dev, priv->rx_dma[idx].rxd1,
3861 + MAX_RX_LENGTH, DMA_FROM_DEVICE);
3862 +
3863 + skb_put(priv->rx_skb[idx], pktlen);
3864 + priv->rx_skb[idx]->dev = priv->netdev;
3865 + priv->rx_skb[idx]->protocol = eth_type_trans(priv->rx_skb[idx], priv->netdev);
3866 + if (priv->rx_dma[idx].rxd4 & priv->soc->checksum_bit)
3867 + priv->rx_skb[idx]->ip_summed = CHECKSUM_UNNECESSARY;
3868 + else
3869 + priv->rx_skb[idx]->ip_summed = CHECKSUM_NONE;
3870 + priv->netdev->stats.rx_packets++;
3871 + priv->netdev->stats.rx_bytes += pktlen;
3872 +
3873 +#ifdef CONFIG_INET_LRO
3874 + if (priv->soc->get_skb_header && priv->rx_skb[idx]->ip_summed == CHECKSUM_UNNECESSARY)
3875 + lro_receive_skb(&priv->lro_mgr, priv->rx_skb[idx], NULL);
3876 + else
3877 +#endif
3878 + netif_receive_skb(priv->rx_skb[idx]);
3879 +
3880 + priv->rx_skb[idx] = new_skb;
3881 +
3882 + dma_addr = dma_map_single(&priv->netdev->dev,
3883 + new_skb->data,
3884 + MAX_RX_LENGTH,
3885 + DMA_FROM_DEVICE);
3886 + priv->rx_dma[idx].rxd1 = (unsigned int) dma_addr;
3887 + wmb();
3888 + } else {
3889 + priv->netdev->stats.rx_dropped++;
3890 + }
3891 +
3892 + if (priv->soc->rx_dma)
3893 + priv->soc->rx_dma(priv, idx, MAX_RX_LENGTH);
3894 + else
3895 + priv->rx_dma[idx].rxd2 = RX_DMA_LSO;
3896 + fe_reg_w32(idx, FE_REG_RX_CALC_IDX0);
3897 +
3898 + rx++;
3899 + } else {
3900 + complete = 1;
3901 + }
3902 + }
3903 +
3904 +#ifdef CONFIG_INET_LRO
3905 + if (priv->soc->get_skb_header)
3906 + lro_flush_all(&priv->lro_mgr);
3907 +#endif
3908 + if (complete) {
3909 + napi_complete(&priv->rx_napi);
3910 + fe_int_enable(priv->soc->rx_dly_int);
3911 + }
3912 +
3913 + return rx;
3914 +}
3915 +
3916 +static void fe_tx_housekeeping(unsigned long ptr)
3917 +{
3918 + struct net_device *dev = (struct net_device*)ptr;
3919 + struct fe_priv *priv = netdev_priv(dev);
3920 + unsigned int bytes_compl = 0;
3921 + unsigned int pkts_compl = 0;
3922 +
3923 + spin_lock(&priv->page_lock);
3924 + while (1) {
3925 + struct fe_tx_dma *txd;
3926 +
3927 + txd = &priv->tx_dma[priv->tx_free_idx];
3928 +
3929 + if (!(txd->txd2 & TX_DMA_DONE) || !(priv->tx_skb[priv->tx_free_idx]))
3930 + break;
3931 +
3932 + if (priv->tx_skb[priv->tx_free_idx] != (struct sk_buff *) DMA_DUMMY_DESC) {
3933 + bytes_compl += priv->tx_skb[priv->tx_free_idx]->len;
3934 + dev_kfree_skb_irq(priv->tx_skb[priv->tx_free_idx]);
3935 + }
3936 + pkts_compl++;
3937 + priv->tx_skb[priv->tx_free_idx] = NULL;
3938 + priv->tx_free_idx++;
3939 + if (priv->tx_free_idx >= NUM_DMA_DESC)
3940 + priv->tx_free_idx = 0;
3941 + }
3942 +
3943 + netdev_completed_queue(priv->netdev, pkts_compl, bytes_compl);
3944 + spin_unlock(&priv->page_lock);
3945 +
3946 + fe_int_enable(priv->soc->tx_dly_int);
3947 +}
3948 +
3949 +static void fe_tx_timeout(struct net_device *dev)
3950 +{
3951 + struct fe_priv *priv = netdev_priv(dev);
3952 +
3953 + tasklet_schedule(&priv->tx_tasklet);
3954 + priv->netdev->stats.tx_errors++;
3955 + netdev_err(dev, "transmit timed out, waking up the queue\n");
3956 + netif_wake_queue(dev);
3957 +}
3958 +
3959 +static irqreturn_t fe_handle_irq(int irq, void *dev)
3960 +{
3961 + struct fe_priv *priv = netdev_priv(dev);
3962 + unsigned int status;
3963 + unsigned int mask;
3964 +
3965 + status = fe_reg_r32(FE_REG_FE_INT_STATUS);
3966 + mask = fe_reg_r32(FE_REG_FE_INT_ENABLE);
3967 +
3968 + if (!(status & mask))
3969 + return IRQ_NONE;
3970 +
3971 + if (status & priv->soc->rx_dly_int) {
3972 + fe_int_disable(priv->soc->rx_dly_int);
3973 + napi_schedule(&priv->rx_napi);
3974 + }
3975 +
3976 + if (status & priv->soc->tx_dly_int) {
3977 + fe_int_disable(priv->soc->tx_dly_int);
3978 + tasklet_schedule(&priv->tx_tasklet);
3979 + }
3980 +
3981 + fe_reg_w32(status, FE_REG_FE_INT_STATUS);
3982 +
3983 + return IRQ_HANDLED;
3984 +}
3985 +
3986 +static int fe_hw_init(struct net_device *dev)
3987 +{
3988 + struct fe_priv *priv = netdev_priv(dev);
3989 + int err;
3990 +
3991 + err = devm_request_irq(priv->device, dev->irq, fe_handle_irq, 0,
3992 + dev_name(priv->device), dev);
3993 + if (err)
3994 + return err;
3995 +
3996 + err = fe_alloc_rx(priv);
3997 + if (!err)
3998 + err = fe_alloc_tx(priv);
3999 + if (err)
4000 + return err;
4001 +
4002 + if (priv->soc->set_mac)
4003 + priv->soc->set_mac(priv, dev->dev_addr);
4004 + else
4005 + fe_hw_set_macaddr(priv, dev->dev_addr);
4006 +
4007 + fe_reg_w32(FE_DELAY_INIT, FE_REG_DLY_INT_CFG);
4008 +
4009 + fe_int_disable(priv->soc->tx_dly_int | priv->soc->rx_dly_int);
4010 +
4011 + tasklet_init(&priv->tx_tasklet, fe_tx_housekeeping, (unsigned long)dev);
4012 +
4013 + if (priv->soc->fwd_config) {
4014 + priv->soc->fwd_config(priv);
4015 + } else {
4016 + unsigned long sysclk = priv->sysclk;
4017 +
4018 + if (!sysclk) {
4019 + netdev_err(dev, "unable to get clock\n");
4020 + return -EINVAL;
4021 + }
4022 +
4023 + sysclk /= FE_US_CYC_CNT_DIVISOR;
4024 + sysclk <<= FE_US_CYC_CNT_SHIFT;
4025 +
4026 + fe_w32((fe_r32(FE_FE_GLO_CFG) &
4027 + ~(FE_US_CYC_CNT_MASK << FE_US_CYC_CNT_SHIFT)) | sysclk,
4028 + FE_FE_GLO_CFG);
4029 +
4030 + fe_w32(fe_r32(FE_GDMA1_FWD_CFG) & ~0xffff, FE_GDMA1_FWD_CFG);
4031 + fe_w32(fe_r32(FE_GDMA1_FWD_CFG) | (FE_GDM1_ICS_EN | FE_GDM1_TCS_EN | FE_GDM1_UCS_EN),
4032 + FE_GDMA1_FWD_CFG);
4033 + fe_w32(fe_r32(FE_CDMA_CSG_CFG) | (FE_ICS_GEN_EN | FE_TCS_GEN_EN | FE_UCS_GEN_EN),
4034 + FE_CDMA_CSG_CFG);
4035 + fe_w32(FE_PSE_FQFC_CFG_INIT, FE_PSE_FQ_CFG);
4036 + }
4037 +
4038 + fe_w32(1, FE_FE_RST_GL);
4039 + fe_w32(0, FE_FE_RST_GL);
4040 +
4041 + return 0;
4042 +}
4043 +
4044 +static int fe_open(struct net_device *dev)
4045 +{
4046 + struct fe_priv *priv = netdev_priv(dev);
4047 + unsigned long flags;
4048 + u32 val;
4049 +
4050 + spin_lock_irqsave(&priv->page_lock, flags);
4051 + napi_enable(&priv->rx_napi);
4052 +
4053 + val = FE_TX_WB_DDONE | FE_RX_DMA_EN | FE_TX_DMA_EN;
4054 + val |= priv->soc->pdma_glo_cfg;
4055 + fe_reg_w32(val, FE_REG_PDMA_GLO_CFG);
4056 +
4057 + spin_unlock_irqrestore(&priv->page_lock, flags);
4058 +
4059 + if (priv->phy)
4060 + priv->phy->start(priv);
4061 +
4062 + if (priv->soc->has_carrier && priv->soc->has_carrier(priv))
4063 + netif_carrier_on(dev);
4064 +
4065 + netif_start_queue(dev);
4066 + fe_int_enable(priv->soc->tx_dly_int | priv->soc->rx_dly_int);
4067 +
4068 + return 0;
4069 +}
4070 +
4071 +static int fe_stop(struct net_device *dev)
4072 +{
4073 + struct fe_priv *priv = netdev_priv(dev);
4074 + unsigned long flags;
4075 +
4076 + fe_int_disable(priv->soc->tx_dly_int | priv->soc->rx_dly_int);
4077 +
4078 + netif_stop_queue(dev);
4079 +
4080 + if (priv->phy)
4081 + priv->phy->stop(priv);
4082 +
4083 + spin_lock_irqsave(&priv->page_lock, flags);
4084 + napi_disable(&priv->rx_napi);
4085 +
4086 + fe_reg_w32(fe_reg_r32(FE_REG_PDMA_GLO_CFG) &
4087 + ~(FE_TX_WB_DDONE | FE_RX_DMA_EN | FE_TX_DMA_EN),
4088 + FE_REG_PDMA_GLO_CFG);
4089 + spin_unlock_irqrestore(&priv->page_lock, flags);
4090 +
4091 + return 0;
4092 +}
4093 +
4094 +static int __init fe_init(struct net_device *dev)
4095 +{
4096 + struct fe_priv *priv = netdev_priv(dev);
4097 + struct device_node *port;
4098 + int err;
4099 +
4100 + BUG_ON(!priv->soc->reset_fe);
4101 + priv->soc->reset_fe();
4102 +
4103 + if (priv->soc->switch_init)
4104 + priv->soc->switch_init(priv);
4105 +
4106 + memcpy(dev->dev_addr, priv->soc->mac, ETH_ALEN);
4107 + of_get_mac_address_mtd(priv->device->of_node, dev->dev_addr);
4108 +
4109 + err = fe_mdio_init(priv);
4110 + if (err)
4111 + return err;
4112 +
4113 + if (priv->phy) {
4114 + err = priv->phy->connect(priv);
4115 + if (err)
4116 + goto err_mdio_cleanup;
4117 + }
4118 +
4119 + if (priv->soc->port_init)
4120 + for_each_child_of_node(priv->device->of_node, port)
4121 + if (of_device_is_compatible(port, "ralink,eth-port") && of_device_is_available(port))
4122 + priv->soc->port_init(priv, port);
4123 +
4124 + err = fe_hw_init(dev);
4125 + if (err)
4126 + goto err_phy_disconnect;
4127 +
4128 + if (priv->soc->switch_config)
4129 + priv->soc->switch_config(priv);
4130 +
4131 + return 0;
4132 +
4133 +err_phy_disconnect:
4134 + if (priv->phy)
4135 + priv->phy->disconnect(priv);
4136 +err_mdio_cleanup:
4137 + fe_mdio_cleanup(priv);
4138 +
4139 + return err;
4140 +}
4141 +
4142 +static void fe_uninit(struct net_device *dev)
4143 +{
4144 + struct fe_priv *priv = netdev_priv(dev);
4145 +
4146 + tasklet_kill(&priv->tx_tasklet);
4147 +
4148 + if (priv->phy)
4149 + priv->phy->disconnect(priv);
4150 + fe_mdio_cleanup(priv);
4151 +
4152 + fe_reg_w32(0, FE_REG_FE_INT_ENABLE);
4153 + free_irq(dev->irq, dev);
4154 +
4155 + fe_free_dma(priv);
4156 +}
4157 +
4158 +static const struct net_device_ops fe_netdev_ops = {
4159 + .ndo_init = fe_init,
4160 + .ndo_uninit = fe_uninit,
4161 + .ndo_open = fe_open,
4162 + .ndo_stop = fe_stop,
4163 + .ndo_start_xmit = fe_start_xmit,
4164 + .ndo_tx_timeout = fe_tx_timeout,
4165 + .ndo_set_mac_address = fe_set_mac_address,
4166 + .ndo_change_mtu = eth_change_mtu,
4167 + .ndo_validate_addr = eth_validate_addr,
4168 +};
4169 +
4170 +static int fe_probe(struct platform_device *pdev)
4171 +{
4172 + struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
4173 + const struct of_device_id *match;
4174 + struct fe_soc_data *soc = NULL;
4175 + struct net_device *netdev;
4176 + struct fe_priv *priv;
4177 + struct clk *sysclk;
4178 + int err;
4179 +
4180 + device_reset(&pdev->dev);
4181 +
4182 + match = of_match_device(of_fe_match, &pdev->dev);
4183 + soc = (struct fe_soc_data *) match->data;
4184 +
4185 + if (soc->init_data)
4186 + soc->init_data(soc);
4187 + if (soc->reg_table)
4188 + fe_reg_table = soc->reg_table;
4189 +
4190 + fe_base = devm_request_and_ioremap(&pdev->dev, res);
4191 + if (!fe_base)
4192 + return -ENOMEM;
4193 +
4194 + netdev = alloc_etherdev(sizeof(struct fe_priv));
4195 + if (!netdev) {
4196 + dev_err(&pdev->dev, "alloc_etherdev failed\n");
4197 + return -ENOMEM;
4198 + }
4199 +
4200 + strcpy(netdev->name, "eth%d");
4201 + netdev->netdev_ops = &fe_netdev_ops;
4202 + netdev->base_addr = (unsigned long) fe_base;
4203 + netdev->watchdog_timeo = TX_TIMEOUT;
4204 + netdev->features |= NETIF_F_IP_CSUM | NETIF_F_RXCSUM;
4205 +
4206 + if (fe_reg_table[FE_REG_FE_DMA_VID_BASE])
4207 + netdev->features |= NETIF_F_HW_VLAN_CTAG_TX;
4208 +
4209 + if (soc->tso) {
4210 + dev_info(&pdev->dev, "Enabling TSO\n");
4211 + netdev->features |= NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_IPV6_CSUM;
4212 + }
4213 + netdev->hw_features = netdev->features;
4214 +
4215 + netdev->irq = platform_get_irq(pdev, 0);
4216 + if (netdev->irq < 0) {
4217 + dev_err(&pdev->dev, "no IRQ resource found\n");
4218 + kfree(netdev);
4219 + return -ENXIO;
4220 + }
4221 +
4222 + priv = netdev_priv(netdev);
4223 + memset(priv, 0, sizeof(struct fe_priv));
4224 + spin_lock_init(&priv->page_lock);
4225 +
4226 + sysclk = devm_clk_get(&pdev->dev, NULL);
4227 + if (!IS_ERR(sysclk))
4228 + priv->sysclk = clk_get_rate(sysclk);
4229 +
4230 + priv->netdev = netdev;
4231 + priv->device = &pdev->dev;
4232 + priv->soc = soc;
4233 +
4234 + err = register_netdev(netdev);
4235 + if (err) {
4236 + dev_err(&pdev->dev, "error bringing up device\n");
4237 + kfree(netdev);
4238 + return err;
4239 + }
4240 + netif_napi_add(netdev, &priv->rx_napi, fe_poll_rx, 32);
4241 +
4242 +#ifdef CONFIG_INET_LRO
4243 + if (priv->soc->get_skb_header) {
4244 + priv->lro_mgr.dev = netdev;
4245 + memset(&priv->lro_mgr.stats, 0, sizeof(priv->lro_mgr.stats));
4246 + priv->lro_mgr.features = LRO_F_NAPI;
4247 + priv->lro_mgr.ip_summed = CHECKSUM_UNNECESSARY;
4248 + priv->lro_mgr.ip_summed_aggr = CHECKSUM_UNNECESSARY;
4249 + priv->lro_mgr.max_desc = ARRAY_SIZE(priv->lro_arr);
4250 + priv->lro_mgr.max_aggr = 64;
4251 + priv->lro_mgr.frag_align_pad = 0;
4252 + priv->lro_mgr.lro_arr = priv->lro_arr;
4253 + priv->lro_mgr.get_skb_header = priv->soc->get_skb_header;
4254 + }
4255 +#endif
4256 +
4257 + platform_set_drvdata(pdev, netdev);
4258 +
4259 + netdev_info(netdev, "done loading\n");
4260 +
4261 + return 0;
4262 +}
4263 +
4264 +static int fe_remove(struct platform_device *pdev)
4265 +{
4266 + struct net_device *dev = platform_get_drvdata(pdev);
4267 + struct fe_priv *priv = netdev_priv(dev);
4268 +
4269 + netif_stop_queue(dev);
4270 + netif_napi_del(&priv->rx_napi);
4271 +
4272 + unregister_netdev(dev);
4273 + free_netdev(dev);
4274 +
4275 + return 0;
4276 +}
4277 +
4278 +static struct platform_driver fe_driver = {
4279 + .probe = fe_probe,
4280 + .remove = fe_remove,
4281 + .driver = {
4282 + .name = "ralink_soc_eth",
4283 + .owner = THIS_MODULE,
4284 + .of_match_table = of_fe_match,
4285 + },
4286 +};
4287 +
4288 +static int __init init_rtfe(void)
4289 +{
4290 + int ret;
4291 +
4292 + ret = rtesw_init();
4293 + if (ret)
4294 + return ret;
4295 +
4296 + ret = platform_driver_register(&fe_driver);
4297 + if (ret)
4298 + rtesw_exit();
4299 +
4300 + return ret;
4301 +}
4302 +
4303 +static void __exit exit_rtfe(void)
4304 +{
4305 + platform_driver_unregister(&fe_driver);
4306 + rtesw_exit();
4307 +}
4308 +
4309 +module_init(init_rtfe);
4310 +module_exit(exit_rtfe);
4311 +
4312 +MODULE_LICENSE("GPL");
4313 +MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
4314 +MODULE_DESCRIPTION("Ethernet driver for Ralink SoC");
4315 diff --git a/drivers/net/ethernet/ralink/ralink_soc_eth.h b/drivers/net/ethernet/ralink/ralink_soc_eth.h
4316 new file mode 100644
4317 index 0000000..ca16788
4318 --- /dev/null
4319 +++ b/drivers/net/ethernet/ralink/ralink_soc_eth.h
4320 @@ -0,0 +1,384 @@
4321 +/*
4322 + * This program is free software; you can redistribute it and/or modify
4323 + * it under the terms of the GNU General Public License as published by
4324 + * the Free Software Foundation; version 2 of the License
4325 + *
4326 + * This program is distributed in the hope that it will be useful,
4327 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
4328 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
4329 + * GNU General Public License for more details.
4330 + *
4331 + * You should have received a copy of the GNU General Public License
4332 + * along with this program; if not, write to the Free Software
4333 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
4334 + *
4335 + * based on Ralink SDK3.3
4336 + * Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
4337 + */
4338 +
4339 +#ifndef FE_ETH_H
4340 +#define FE_ETH_H
4341 +
4342 +#include <linux/mii.h>
4343 +#include <linux/interrupt.h>
4344 +#include <linux/netdevice.h>
4345 +#include <linux/dma-mapping.h>
4346 +#include <linux/phy.h>
4347 +#include <linux/inet_lro.h>
4348 +
4349 +
4350 +enum fe_reg {
4351 + FE_REG_PDMA_GLO_CFG = 0,
4352 + FE_REG_PDMA_RST_CFG,
4353 + FE_REG_DLY_INT_CFG,
4354 + FE_REG_TX_BASE_PTR0,
4355 + FE_REG_TX_MAX_CNT0,
4356 + FE_REG_TX_CTX_IDX0,
4357 + FE_REG_RX_BASE_PTR0,
4358 + FE_REG_RX_MAX_CNT0,
4359 + FE_REG_RX_CALC_IDX0,
4360 + FE_REG_FE_INT_ENABLE,
4361 + FE_REG_FE_INT_STATUS,
4362 + FE_REG_FE_DMA_VID_BASE,
4363 + FE_REG_COUNT
4364 +};
4365 +
4366 +#define NUM_DMA_DESC 0x100
4367 +
4368 +#define FE_DELAY_EN_INT 0x80
4369 +#define FE_DELAY_MAX_INT 0x04
4370 +#define FE_DELAY_MAX_TOUT 0x04
4371 +#define FE_DELAY_CHAN (((FE_DELAY_EN_INT | FE_DELAY_MAX_INT) << 8) | FE_DELAY_MAX_TOUT)
4372 +#define FE_DELAY_INIT ((FE_DELAY_CHAN << 16) | FE_DELAY_CHAN)
4373 +#define FE_PSE_FQFC_CFG_INIT 0x80504000
4374 +
4375 +/* interrupt bits */
4376 +#define FE_CNT_PPE_AF BIT(31)
4377 +#define FE_CNT_GDM_AF BIT(29)
4378 +#define FE_PSE_P2_FC BIT(26)
4379 +#define FE_PSE_BUF_DROP BIT(24)
4380 +#define FE_GDM_OTHER_DROP BIT(23)
4381 +#define FE_PSE_P1_FC BIT(22)
4382 +#define FE_PSE_P0_FC BIT(21)
4383 +#define FE_PSE_FQ_EMPTY BIT(20)
4384 +#define FE_GE1_STA_CHG BIT(18)
4385 +#define FE_TX_COHERENT BIT(17)
4386 +#define FE_RX_COHERENT BIT(16)
4387 +#define FE_TX_DONE_INT3 BIT(11)
4388 +#define FE_TX_DONE_INT2 BIT(10)
4389 +#define FE_TX_DONE_INT1 BIT(9)
4390 +#define FE_TX_DONE_INT0 BIT(8)
4391 +#define FE_RX_DONE_INT0 BIT(2)
4392 +#define FE_TX_DLY_INT BIT(1)
4393 +#define FE_RX_DLY_INT BIT(0)
4394 +
4395 +#define RT5350_RX_DLY_INT BIT(30)
4396 +#define RT5350_TX_DLY_INT BIT(28)
4397 +
4398 +/* registers */
4399 +#define FE_FE_OFFSET 0x0000
4400 +#define FE_GDMA_OFFSET 0x0020
4401 +#define FE_PSE_OFFSET 0x0040
4402 +#define FE_GDMA2_OFFSET 0x0060
4403 +#define FE_CDMA_OFFSET 0x0080
4404 +#define FE_DMA_VID0 0x00a8
4405 +#define FE_PDMA_OFFSET 0x0100
4406 +#define FE_PPE_OFFSET 0x0200
4407 +#define FE_CMTABLE_OFFSET 0x0400
4408 +#define FE_POLICYTABLE_OFFSET 0x1000
4409 +
4410 +#define RT5350_PDMA_OFFSET 0x0800
4411 +#define RT5350_SDM_OFFSET 0x0c00
4412 +
4413 +#define FE_MDIO_ACCESS (FE_FE_OFFSET + 0x00)
4414 +#define FE_MDIO_CFG (FE_FE_OFFSET + 0x04)
4415 +#define FE_FE_GLO_CFG (FE_FE_OFFSET + 0x08)
4416 +#define FE_FE_RST_GL (FE_FE_OFFSET + 0x0C)
4417 +#define FE_FE_INT_STATUS (FE_FE_OFFSET + 0x10)
4418 +#define FE_FE_INT_ENABLE (FE_FE_OFFSET + 0x14)
4419 +#define FE_MDIO_CFG2 (FE_FE_OFFSET + 0x18)
4420 +#define FE_FOC_TS_T (FE_FE_OFFSET + 0x1C)
4421 +
4422 +#define FE_GDMA1_FWD_CFG (FE_GDMA_OFFSET + 0x00)
4423 +#define FE_GDMA1_SCH_CFG (FE_GDMA_OFFSET + 0x04)
4424 +#define FE_GDMA1_SHPR_CFG (FE_GDMA_OFFSET + 0x08)
4425 +#define FE_GDMA1_MAC_ADRL (FE_GDMA_OFFSET + 0x0C)
4426 +#define FE_GDMA1_MAC_ADRH (FE_GDMA_OFFSET + 0x10)
4427 +
4428 +#define FE_GDMA2_FWD_CFG (FE_GDMA2_OFFSET + 0x00)
4429 +#define FE_GDMA2_SCH_CFG (FE_GDMA2_OFFSET + 0x04)
4430 +#define FE_GDMA2_SHPR_CFG (FE_GDMA2_OFFSET + 0x08)
4431 +#define FE_GDMA2_MAC_ADRL (FE_GDMA2_OFFSET + 0x0C)
4432 +#define FE_GDMA2_MAC_ADRH (FE_GDMA2_OFFSET + 0x10)
4433 +
4434 +#define FE_PSE_FQ_CFG (FE_PSE_OFFSET + 0x00)
4435 +#define FE_CDMA_FC_CFG (FE_PSE_OFFSET + 0x04)
4436 +#define FE_GDMA1_FC_CFG (FE_PSE_OFFSET + 0x08)
4437 +#define FE_GDMA2_FC_CFG (FE_PSE_OFFSET + 0x0C)
4438 +
4439 +#define FE_CDMA_CSG_CFG (FE_CDMA_OFFSET + 0x00)
4440 +#define FE_CDMA_SCH_CFG (FE_CDMA_OFFSET + 0x04)
4441 +
4442 +#define MT7620A_GDMA_OFFSET 0x0600
4443 +#define MT7620A_GDMA1_FWD_CFG (MT7620A_GDMA_OFFSET + 0x00)
4444 +#define MT7620A_FE_GDMA1_SCH_CFG (MT7620A_GDMA_OFFSET + 0x04)
4445 +#define MT7620A_FE_GDMA1_SHPR_CFG (MT7620A_GDMA_OFFSET + 0x08)
4446 +#define MT7620A_FE_GDMA1_MAC_ADRL (MT7620A_GDMA_OFFSET + 0x0C)
4447 +#define MT7620A_FE_GDMA1_MAC_ADRH (MT7620A_GDMA_OFFSET + 0x10)
4448 +
4449 +#define RT5350_TX_BASE_PTR0 (RT5350_PDMA_OFFSET + 0x00)
4450 +#define RT5350_TX_MAX_CNT0 (RT5350_PDMA_OFFSET + 0x04)
4451 +#define RT5350_TX_CTX_IDX0 (RT5350_PDMA_OFFSET + 0x08)
4452 +#define RT5350_TX_DTX_IDX0 (RT5350_PDMA_OFFSET + 0x0C)
4453 +#define RT5350_TX_BASE_PTR1 (RT5350_PDMA_OFFSET + 0x10)
4454 +#define RT5350_TX_MAX_CNT1 (RT5350_PDMA_OFFSET + 0x14)
4455 +#define RT5350_TX_CTX_IDX1 (RT5350_PDMA_OFFSET + 0x18)
4456 +#define RT5350_TX_DTX_IDX1 (RT5350_PDMA_OFFSET + 0x1C)
4457 +#define RT5350_TX_BASE_PTR2 (RT5350_PDMA_OFFSET + 0x20)
4458 +#define RT5350_TX_MAX_CNT2 (RT5350_PDMA_OFFSET + 0x24)
4459 +#define RT5350_TX_CTX_IDX2 (RT5350_PDMA_OFFSET + 0x28)
4460 +#define RT5350_TX_DTX_IDX2 (RT5350_PDMA_OFFSET + 0x2C)
4461 +#define RT5350_TX_BASE_PTR3 (RT5350_PDMA_OFFSET + 0x30)
4462 +#define RT5350_TX_MAX_CNT3 (RT5350_PDMA_OFFSET + 0x34)
4463 +#define RT5350_TX_CTX_IDX3 (RT5350_PDMA_OFFSET + 0x38)
4464 +#define RT5350_TX_DTX_IDX3 (RT5350_PDMA_OFFSET + 0x3C)
4465 +#define RT5350_RX_BASE_PTR0 (RT5350_PDMA_OFFSET + 0x100)
4466 +#define RT5350_RX_MAX_CNT0 (RT5350_PDMA_OFFSET + 0x104)
4467 +#define RT5350_RX_CALC_IDX0 (RT5350_PDMA_OFFSET + 0x108)
4468 +#define RT5350_RX_DRX_IDX0 (RT5350_PDMA_OFFSET + 0x10C)
4469 +#define RT5350_RX_BASE_PTR1 (RT5350_PDMA_OFFSET + 0x110)
4470 +#define RT5350_RX_MAX_CNT1 (RT5350_PDMA_OFFSET + 0x114)
4471 +#define RT5350_RX_CALC_IDX1 (RT5350_PDMA_OFFSET + 0x118)
4472 +#define RT5350_RX_DRX_IDX1 (RT5350_PDMA_OFFSET + 0x11C)
4473 +#define RT5350_PDMA_GLO_CFG (RT5350_PDMA_OFFSET + 0x204)
4474 +#define RT5350_PDMA_RST_CFG (RT5350_PDMA_OFFSET + 0x208)
4475 +#define RT5350_DLY_INT_CFG (RT5350_PDMA_OFFSET + 0x20c)
4476 +#define RT5350_FE_INT_STATUS (RT5350_PDMA_OFFSET + 0x220)
4477 +#define RT5350_FE_INT_ENABLE (RT5350_PDMA_OFFSET + 0x228)
4478 +#define RT5350_PDMA_SCH_CFG (RT5350_PDMA_OFFSET + 0x280)
4479 +
4480 +#define FE_PDMA_GLO_CFG (FE_PDMA_OFFSET + 0x00)
4481 +#define FE_PDMA_RST_CFG (FE_PDMA_OFFSET + 0x04)
4482 +#define FE_PDMA_SCH_CFG (FE_PDMA_OFFSET + 0x08)
4483 +#define FE_DLY_INT_CFG (FE_PDMA_OFFSET + 0x0C)
4484 +#define FE_TX_BASE_PTR0 (FE_PDMA_OFFSET + 0x10)
4485 +#define FE_TX_MAX_CNT0 (FE_PDMA_OFFSET + 0x14)
4486 +#define FE_TX_CTX_IDX0 (FE_PDMA_OFFSET + 0x18)
4487 +#define FE_TX_DTX_IDX0 (FE_PDMA_OFFSET + 0x1C)
4488 +#define FE_TX_BASE_PTR1 (FE_PDMA_OFFSET + 0x20)
4489 +#define FE_TX_MAX_CNT1 (FE_PDMA_OFFSET + 0x24)
4490 +#define FE_TX_CTX_IDX1 (FE_PDMA_OFFSET + 0x28)
4491 +#define FE_TX_DTX_IDX1 (FE_PDMA_OFFSET + 0x2C)
4492 +#define FE_RX_BASE_PTR0 (FE_PDMA_OFFSET + 0x30)
4493 +#define FE_RX_MAX_CNT0 (FE_PDMA_OFFSET + 0x34)
4494 +#define FE_RX_CALC_IDX0 (FE_PDMA_OFFSET + 0x38)
4495 +#define FE_RX_DRX_IDX0 (FE_PDMA_OFFSET + 0x3C)
4496 +#define FE_TX_BASE_PTR2 (FE_PDMA_OFFSET + 0x40)
4497 +#define FE_TX_MAX_CNT2 (FE_PDMA_OFFSET + 0x44)
4498 +#define FE_TX_CTX_IDX2 (FE_PDMA_OFFSET + 0x48)
4499 +#define FE_TX_DTX_IDX2 (FE_PDMA_OFFSET + 0x4C)
4500 +#define FE_TX_BASE_PTR3 (FE_PDMA_OFFSET + 0x50)
4501 +#define FE_TX_MAX_CNT3 (FE_PDMA_OFFSET + 0x54)
4502 +#define FE_TX_CTX_IDX3 (FE_PDMA_OFFSET + 0x58)
4503 +#define FE_TX_DTX_IDX3 (FE_PDMA_OFFSET + 0x5C)
4504 +#define FE_RX_BASE_PTR1 (FE_PDMA_OFFSET + 0x60)
4505 +#define FE_RX_MAX_CNT1 (FE_PDMA_OFFSET + 0x64)
4506 +#define FE_RX_CALC_IDX1 (FE_PDMA_OFFSET + 0x68)
4507 +#define FE_RX_DRX_IDX1 (FE_PDMA_OFFSET + 0x6C)
4508 +
4509 +#define RT5350_SDM_CFG (RT5350_SDM_OFFSET + 0x00) //Switch DMA configuration
4510 +#define RT5350_SDM_RRING (RT5350_SDM_OFFSET + 0x04) //Switch DMA Rx Ring
4511 +#define RT5350_SDM_TRING (RT5350_SDM_OFFSET + 0x08) //Switch DMA Tx Ring
4512 +#define RT5350_SDM_MAC_ADRL (RT5350_SDM_OFFSET + 0x0C) //Switch MAC address LSB
4513 +#define RT5350_SDM_MAC_ADRH (RT5350_SDM_OFFSET + 0x10) //Switch MAC Address MSB
4514 +#define RT5350_SDM_TPCNT (RT5350_SDM_OFFSET + 0x100) //Switch DMA Tx packet count
4515 +#define RT5350_SDM_TBCNT (RT5350_SDM_OFFSET + 0x104) //Switch DMA Tx byte count
4516 +#define RT5350_SDM_RPCNT (RT5350_SDM_OFFSET + 0x108) //Switch DMA rx packet count
4517 +#define RT5350_SDM_RBCNT (RT5350_SDM_OFFSET + 0x10C) //Switch DMA rx byte count
4518 +#define RT5350_SDM_CS_ERR (RT5350_SDM_OFFSET + 0x110) //Switch DMA rx checksum error count
4519 +
4520 +#define RT5350_SDM_ICS_EN BIT(16)
4521 +#define RT5350_SDM_TCS_EN BIT(17)
4522 +#define RT5350_SDM_UCS_EN BIT(18)
4523 +
4524 +
4525 +/* MDIO_CFG register bits */
4526 +#define FE_MDIO_CFG_AUTO_POLL_EN BIT(29)
4527 +#define FE_MDIO_CFG_GP1_BP_EN BIT(16)
4528 +#define FE_MDIO_CFG_GP1_FRC_EN BIT(15)
4529 +#define FE_MDIO_CFG_GP1_SPEED_10 (0 << 13)
4530 +#define FE_MDIO_CFG_GP1_SPEED_100 (1 << 13)
4531 +#define FE_MDIO_CFG_GP1_SPEED_1000 (2 << 13)
4532 +#define FE_MDIO_CFG_GP1_DUPLEX BIT(12)
4533 +#define FE_MDIO_CFG_GP1_FC_TX BIT(11)
4534 +#define FE_MDIO_CFG_GP1_FC_RX BIT(10)
4535 +#define FE_MDIO_CFG_GP1_LNK_DWN BIT(9)
4536 +#define FE_MDIO_CFG_GP1_AN_FAIL BIT(8)
4537 +#define FE_MDIO_CFG_MDC_CLK_DIV_1 (0 << 6)
4538 +#define FE_MDIO_CFG_MDC_CLK_DIV_2 (1 << 6)
4539 +#define FE_MDIO_CFG_MDC_CLK_DIV_4 (2 << 6)
4540 +#define FE_MDIO_CFG_MDC_CLK_DIV_8 (3 << 6)
4541 +#define FE_MDIO_CFG_TURBO_MII_FREQ BIT(5)
4542 +#define FE_MDIO_CFG_TURBO_MII_MODE BIT(4)
4543 +#define FE_MDIO_CFG_RX_CLK_SKEW_0 (0 << 2)
4544 +#define FE_MDIO_CFG_RX_CLK_SKEW_200 (1 << 2)
4545 +#define FE_MDIO_CFG_RX_CLK_SKEW_400 (2 << 2)
4546 +#define FE_MDIO_CFG_RX_CLK_SKEW_INV (3 << 2)
4547 +#define FE_MDIO_CFG_TX_CLK_SKEW_0 0
4548 +#define FE_MDIO_CFG_TX_CLK_SKEW_200 1
4549 +#define FE_MDIO_CFG_TX_CLK_SKEW_400 2
4550 +#define FE_MDIO_CFG_TX_CLK_SKEW_INV 3
4551 +
4552 +/* uni-cast port */
4553 +#define FE_GDM1_ICS_EN BIT(22)
4554 +#define FE_GDM1_TCS_EN BIT(21)
4555 +#define FE_GDM1_UCS_EN BIT(20)
4556 +#define FE_GDM1_JMB_EN BIT(19)
4557 +#define FE_GDM1_STRPCRC BIT(16)
4558 +#define FE_GDM1_UFRC_P_CPU (0 << 12)
4559 +#define FE_GDM1_UFRC_P_GDMA1 (1 << 12)
4560 +#define FE_GDM1_UFRC_P_PPE (6 << 12)
4561 +
4562 +/* checksums */
4563 +#define FE_ICS_GEN_EN BIT(2)
4564 +#define FE_UCS_GEN_EN BIT(1)
4565 +#define FE_TCS_GEN_EN BIT(0)
4566 +
4567 +/* dma ring */
4568 +#define FE_PST_DRX_IDX0 BIT(16)
4569 +#define FE_PST_DTX_IDX3 BIT(3)
4570 +#define FE_PST_DTX_IDX2 BIT(2)
4571 +#define FE_PST_DTX_IDX1 BIT(1)
4572 +#define FE_PST_DTX_IDX0 BIT(0)
4573 +
4574 +#define FE_TX_WB_DDONE BIT(6)
4575 +#define FE_RX_DMA_BUSY BIT(3)
4576 +#define FE_TX_DMA_BUSY BIT(1)
4577 +#define FE_RX_DMA_EN BIT(2)
4578 +#define FE_TX_DMA_EN BIT(0)
4579 +
4580 +#define FE_PDMA_SIZE_4DWORDS (0 << 4)
4581 +#define FE_PDMA_SIZE_8DWORDS (1 << 4)
4582 +#define FE_PDMA_SIZE_16DWORDS (2 << 4)
4583 +
4584 +#define FE_US_CYC_CNT_MASK 0xff
4585 +#define FE_US_CYC_CNT_SHIFT 0x8
4586 +#define FE_US_CYC_CNT_DIVISOR 1000000
4587 +
4588 +#define RX_DMA_PLEN0(_x) (((_x) >> 16) & 0x3fff)
4589 +#define RX_DMA_LSO BIT(30)
4590 +#define RX_DMA_DONE BIT(31)
4591 +#define RX_DMA_L4VALID BIT(30)
4592 +
4593 +struct fe_rx_dma {
4594 + unsigned int rxd1;
4595 + unsigned int rxd2;
4596 + unsigned int rxd3;
4597 + unsigned int rxd4;
4598 +} __packed __aligned(4);
4599 +
4600 +#define TX_DMA_PLEN0_MASK ((0x3fff) << 16)
4601 +#define TX_DMA_PLEN0(_x) (((_x) & 0x3fff) << 16)
4602 +#define TX_DMA_PLEN1(_x) ((_x) & 0x3fff)
4603 +#define TX_DMA_LS1 BIT(14)
4604 +#define TX_DMA_LSO BIT(30)
4605 +#define TX_DMA_DONE BIT(31)
4606 +#define TX_DMA_QN(_x) ((_x) << 16)
4607 +#define TX_DMA_PN(_x) ((_x) << 24)
4608 +#define TX_DMA_QN_MASK TX_DMA_QN(0x7)
4609 +#define TX_DMA_PN_MASK TX_DMA_PN(0x7)
4610 +#define TX_DMA_CHKSUM (0x7 << 29)
4611 +
4612 +struct fe_tx_dma {
4613 + unsigned int txd1;
4614 + unsigned int txd2;
4615 + unsigned int txd3;
4616 + unsigned int txd4;
4617 +} __packed __aligned(4);
4618 +
4619 +struct fe_priv;
4620 +
4621 +struct fe_phy {
4622 + struct phy_device *phy[8];
4623 + struct device_node *phy_node[8];
4624 + const __be32 *phy_fixed[8];
4625 + int duplex[8];
4626 + int speed[8];
4627 + int tx_fc[8];
4628 + int rx_fc[8];
4629 + spinlock_t lock;
4630 +
4631 + int (*connect)(struct fe_priv *priv);
4632 + void (*disconnect)(struct fe_priv *priv);
4633 + void (*start)(struct fe_priv *priv);
4634 + void (*stop)(struct fe_priv *priv);
4635 +};
4636 +
4637 +struct fe_soc_data
4638 +{
4639 + unsigned char mac[6];
4640 + const u32 *reg_table;
4641 +
4642 + void (*init_data)(struct fe_soc_data *data);
4643 + void (*reset_fe)(void);
4644 + void (*set_mac)(struct fe_priv *priv, unsigned char *mac);
4645 + void (*fwd_config)(struct fe_priv *priv);
4646 + void (*tx_dma)(struct fe_priv *priv, int idx, struct sk_buff *skb);
4647 + void (*rx_dma)(struct fe_priv *priv, int idx, int len);
4648 + int (*switch_init)(struct fe_priv *priv);
4649 + int (*switch_config)(struct fe_priv *priv);
4650 + void (*port_init)(struct fe_priv *priv, struct device_node *port);
4651 + int (*has_carrier)(struct fe_priv *priv);
4652 + int (*mdio_init)(struct fe_priv *priv);
4653 + void (*mdio_cleanup)(struct fe_priv *priv);
4654 + int (*mdio_write)(struct mii_bus *bus, int phy_addr, int phy_reg, u16 val);
4655 + int (*mdio_read)(struct mii_bus *bus, int phy_addr, int phy_reg);
4656 + void (*mdio_adjust_link)(struct fe_priv *priv, int port);
4657 + int (*get_skb_header)(struct sk_buff *skb, void **iphdr, void **tcph, u64 *hdr_flags, void *priv);
4658 +
4659 + void *swpriv;
4660 + u32 pdma_glo_cfg;
4661 + u32 rx_dly_int;
4662 + u32 tx_dly_int;
4663 + u32 checksum_bit;
4664 + u32 tso;
4665 +
4666 + int min_pkt_len;
4667 +};
4668 +
4669 +struct fe_priv
4670 +{
4671 + spinlock_t page_lock;
4672 +
4673 + struct fe_soc_data *soc;
4674 + struct net_device *netdev;
4675 + struct device *device;
4676 + unsigned long sysclk;
4677 +
4678 + struct fe_rx_dma *rx_dma;
4679 + struct napi_struct rx_napi;
4680 + struct sk_buff *rx_skb[NUM_DMA_DESC];
4681 + dma_addr_t rx_phys;
4682 +
4683 + struct fe_tx_dma *tx_dma;
4684 + struct tasklet_struct tx_tasklet;
4685 + struct sk_buff *tx_skb[NUM_DMA_DESC];
4686 + dma_addr_t tx_phys;
4687 + unsigned int tx_free_idx;
4688 +
4689 + struct fe_phy *phy;
4690 + struct mii_bus *mii_bus;
4691 + int mii_irq[PHY_MAX_ADDR];
4692 +
4693 + int link[8];
4694 +
4695 + struct net_lro_mgr lro_mgr;
4696 + struct net_lro_desc lro_arr[8];
4697 +};
4698 +
4699 +extern const struct of_device_id of_fe_match[];
4700 +
4701 +void fe_w32(u32 val, unsigned reg);
4702 +u32 fe_r32(unsigned reg);
4703 +
4704 +#endif /* FE_ETH_H */
4705 diff --git a/drivers/net/ethernet/ralink/soc_mt7620.c b/drivers/net/ethernet/ralink/soc_mt7620.c
4706 new file mode 100644
4707 index 0000000..79b7b85
4708 --- /dev/null
4709 +++ b/drivers/net/ethernet/ralink/soc_mt7620.c
4710 @@ -0,0 +1,172 @@
4711 +/*
4712 + * This program is free software; you can redistribute it and/or modify
4713 + * it under the terms of the GNU General Public License as published by
4714 + * the Free Software Foundation; version 2 of the License
4715 + *
4716 + * This program is distributed in the hope that it will be useful,
4717 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
4718 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
4719 + * GNU General Public License for more details.
4720 + *
4721 + * You should have received a copy of the GNU General Public License
4722 + * along with this program; if not, write to the Free Software
4723 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
4724 + *
4725 + * Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
4726 + */
4727 +
4728 +#include <linux/module.h>
4729 +#include <linux/platform_device.h>
4730 +#include <linux/if_vlan.h>
4731 +
4732 +#include <asm/mach-ralink/ralink_regs.h>
4733 +
4734 +#include <mt7620.h>
4735 +#include "ralink_soc_eth.h"
4736 +#include "gsw_mt7620a.h"
4737 +
4738 +#define MT7620A_CDMA_CSG_CFG 0x400
4739 +#define MT7620_DMA_VID (MT7620A_CDMA_CSG_CFG | 0x30)
4740 +#define MT7620A_DMA_2B_OFFSET BIT(31)
4741 +#define MT7620A_RESET_FE BIT(21)
4742 +#define MT7620A_RESET_ESW BIT(23)
4743 +#define MT7620_L4_VALID BIT(23)
4744 +
4745 +#define SYSC_REG_RESET_CTRL 0x34
4746 +#define MAX_RX_LENGTH 1536
4747 +
4748 +#define CDMA_ICS_EN BIT(2)
4749 +#define CDMA_UCS_EN BIT(1)
4750 +#define CDMA_TCS_EN BIT(0)
4751 +
4752 +#define GDMA_ICS_EN BIT(22)
4753 +#define GDMA_TCS_EN BIT(21)
4754 +#define GDMA_UCS_EN BIT(20)
4755 +
4756 +static const u32 rt5350_reg_table[FE_REG_COUNT] = {
4757 + [FE_REG_PDMA_GLO_CFG] = RT5350_PDMA_GLO_CFG,
4758 + [FE_REG_PDMA_RST_CFG] = RT5350_PDMA_RST_CFG,
4759 + [FE_REG_DLY_INT_CFG] = RT5350_DLY_INT_CFG,
4760 + [FE_REG_TX_BASE_PTR0] = RT5350_TX_BASE_PTR0,
4761 + [FE_REG_TX_MAX_CNT0] = RT5350_TX_MAX_CNT0,
4762 + [FE_REG_TX_CTX_IDX0] = RT5350_TX_CTX_IDX0,
4763 + [FE_REG_RX_BASE_PTR0] = RT5350_RX_BASE_PTR0,
4764 + [FE_REG_RX_MAX_CNT0] = RT5350_RX_MAX_CNT0,
4765 + [FE_REG_RX_CALC_IDX0] = RT5350_RX_CALC_IDX0,
4766 + [FE_REG_FE_INT_ENABLE] = RT5350_FE_INT_ENABLE,
4767 + [FE_REG_FE_INT_STATUS] = RT5350_FE_INT_STATUS,
4768 + [FE_REG_FE_DMA_VID_BASE] = MT7620_DMA_VID,
4769 +};
4770 +
4771 +static void mt7620_fe_reset(void)
4772 +{
4773 + rt_sysc_w32(MT7620A_RESET_FE | MT7620A_RESET_ESW, SYSC_REG_RESET_CTRL);
4774 + rt_sysc_w32(0, SYSC_REG_RESET_CTRL);
4775 +}
4776 +
4777 +static void mt7620_fwd_config(struct fe_priv *priv)
4778 +{
4779 + int i;
4780 +
4781 + /* frame engine will push VLAN tag regarding to VIDX feild in Tx desc. */
4782 + for (i = 0; i < 16; i += 2)
4783 + fe_w32(((i + 1) << 16) + i, MT7620_DMA_VID + (i * 2));
4784 +
4785 + fe_w32(fe_r32(MT7620A_GDMA1_FWD_CFG) & ~7, MT7620A_GDMA1_FWD_CFG);
4786 + fe_w32(fe_r32(MT7620A_GDMA1_FWD_CFG) | (GDMA_ICS_EN | GDMA_TCS_EN | GDMA_UCS_EN), MT7620A_GDMA1_FWD_CFG);
4787 + fe_w32(fe_r32(MT7620A_CDMA_CSG_CFG) | (CDMA_ICS_EN | CDMA_UCS_EN | CDMA_TCS_EN), MT7620A_CDMA_CSG_CFG);
4788 +}
4789 +
4790 +static void mt7620_tx_dma(struct fe_priv *priv, int idx, struct sk_buff *skb)
4791 +{
4792 + unsigned int nr_frags = 0;
4793 + unsigned int len = 0;
4794 +
4795 + if (skb) {
4796 + nr_frags = skb_shinfo(skb)->nr_frags;
4797 + len = skb->len - skb->data_len;
4798 + }
4799 +
4800 + if (!skb)
4801 + priv->tx_dma[idx].txd2 = TX_DMA_LSO | TX_DMA_DONE;
4802 + else if (!nr_frags)
4803 + priv->tx_dma[idx].txd2 = TX_DMA_LSO | TX_DMA_PLEN0(len);
4804 + else
4805 + priv->tx_dma[idx].txd2 = TX_DMA_PLEN0(len);
4806 +
4807 + if(skb && vlan_tx_tag_present(skb))
4808 + priv->tx_dma[idx].txd4 = 0x80 | (vlan_tx_tag_get(skb) >> 13) << 4 | (vlan_tx_tag_get(skb) & 0xF);
4809 + else
4810 + priv->tx_dma[idx].txd4 = 0;
4811 +}
4812 +
4813 +static void mt7620_rx_dma(struct fe_priv *priv, int idx, int len)
4814 +{
4815 + priv->rx_dma[idx].rxd2 = RX_DMA_PLEN0(len);
4816 +}
4817 +
4818 +#ifdef CONFIG_INET_LRO
4819 +static int
4820 +mt7620_get_skb_header(struct sk_buff *skb, void **iphdr, void **tcph,
4821 + u64 *hdr_flags, void *_priv)
4822 +{
4823 + struct iphdr *iph = NULL;
4824 + int vhdr_len = 0;
4825 +
4826 + /*
4827 + * Make sure that this packet is Ethernet II, is not VLAN
4828 + * tagged, is IPv4, has a valid IP header, and is TCP.
4829 + */
4830 + if (skb->protocol == 0x0081)
4831 + vhdr_len = VLAN_HLEN;
4832 +
4833 + iph = (struct iphdr *)(skb->data + vhdr_len);
4834 + if(iph->protocol != IPPROTO_TCP)
4835 + return -1;
4836 +
4837 + *iphdr = iph;
4838 + *tcph = skb->data + (iph->ihl << 2) + vhdr_len;
4839 + *hdr_flags = LRO_IPV4 | LRO_TCP;
4840 +
4841 + return 0;
4842 +}
4843 +#endif
4844 +
4845 +static void mt7620_init_data(struct fe_soc_data *data)
4846 +{
4847 + if (mt7620_get_eco() >= 5)
4848 + data->tso = 1;
4849 +}
4850 +
4851 +static struct fe_soc_data mt7620_data = {
4852 + .mac = { 0x00, 0x11, 0x22, 0x33, 0x44, 0x55 },
4853 + .init_data = mt7620_init_data,
4854 + .reset_fe = mt7620_fe_reset,
4855 + .set_mac = mt7620_set_mac,
4856 + .fwd_config = mt7620_fwd_config,
4857 + .tx_dma = mt7620_tx_dma,
4858 + .rx_dma = mt7620_rx_dma,
4859 + .switch_init = mt7620_gsw_probe,
4860 + .switch_config = mt7620_gsw_config,
4861 + .port_init = mt7620_port_init,
4862 + .min_pkt_len = 0,
4863 + .reg_table = rt5350_reg_table,
4864 + .pdma_glo_cfg = FE_PDMA_SIZE_16DWORDS | MT7620A_DMA_2B_OFFSET,
4865 + .rx_dly_int = RT5350_RX_DLY_INT,
4866 + .tx_dly_int = RT5350_TX_DLY_INT,
4867 + .checksum_bit = MT7620_L4_VALID,
4868 + .has_carrier = mt7620a_has_carrier,
4869 + .mdio_read = mt7620_mdio_read,
4870 + .mdio_write = mt7620_mdio_write,
4871 + .mdio_adjust_link = mt7620_mdio_link_adjust,
4872 +#ifdef CONFIG_INET_LRO
4873 + .get_skb_header = mt7620_get_skb_header,
4874 +#endif
4875 +};
4876 +
4877 +const struct of_device_id of_fe_match[] = {
4878 + { .compatible = "ralink,mt7620a-eth", .data = &mt7620_data },
4879 + {},
4880 +};
4881 +
4882 +MODULE_DEVICE_TABLE(of, of_fe_match);
4883 diff --git a/drivers/net/ethernet/ralink/soc_rt2880.c b/drivers/net/ethernet/ralink/soc_rt2880.c
4884 new file mode 100644
4885 index 0000000..e0c418b
4886 --- /dev/null
4887 +++ b/drivers/net/ethernet/ralink/soc_rt2880.c
4888 @@ -0,0 +1,52 @@
4889 +/*
4890 + * This program is free software; you can redistribute it and/or modify
4891 + * it under the terms of the GNU General Public License as published by
4892 + * the Free Software Foundation; version 2 of the License
4893 + *
4894 + * This program is distributed in the hope that it will be useful,
4895 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
4896 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
4897 + * GNU General Public License for more details.
4898 + *
4899 + * You should have received a copy of the GNU General Public License
4900 + * along with this program; if not, write to the Free Software
4901 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
4902 + *
4903 + * Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
4904 + */
4905 +
4906 +#include <linux/module.h>
4907 +
4908 +#include <asm/mach-ralink/ralink_regs.h>
4909 +
4910 +#include "ralink_soc_eth.h"
4911 +#include "mdio_rt2880.h"
4912 +
4913 +#define SYSC_REG_RESET_CTRL 0x034
4914 +#define RT2880_RESET_FE BIT(18)
4915 +
4916 +void rt2880_fe_reset(void)
4917 +{
4918 + rt_sysc_w32(RT2880_RESET_FE, SYSC_REG_RESET_CTRL);
4919 +}
4920 +
4921 +struct fe_soc_data rt2880_data = {
4922 + .mac = { 0x00, 0x11, 0x22, 0x33, 0x44, 0x55 },
4923 + .reset_fe = rt2880_fe_reset,
4924 + .min_pkt_len = 64,
4925 + .pdma_glo_cfg = FE_PDMA_SIZE_4DWORDS,
4926 + .checksum_bit = RX_DMA_L4VALID,
4927 + .rx_dly_int = FE_RX_DLY_INT,
4928 + .tx_dly_int = FE_TX_DLY_INT,
4929 + .mdio_read = rt2880_mdio_read,
4930 + .mdio_write = rt2880_mdio_write,
4931 + .mdio_adjust_link = rt2880_mdio_link_adjust,
4932 + .port_init = rt2880_port_init,
4933 +};
4934 +
4935 +const struct of_device_id of_fe_match[] = {
4936 + { .compatible = "ralink,rt2880-eth", .data = &rt2880_data },
4937 + {},
4938 +};
4939 +
4940 +MODULE_DEVICE_TABLE(of, of_fe_match);
4941 diff --git a/drivers/net/ethernet/ralink/soc_rt305x.c b/drivers/net/ethernet/ralink/soc_rt305x.c
4942 new file mode 100644
4943 index 0000000..482ca1f
4944 --- /dev/null
4945 +++ b/drivers/net/ethernet/ralink/soc_rt305x.c
4946 @@ -0,0 +1,113 @@
4947 +/*
4948 + * This program is free software; you can redistribute it and/or modify
4949 + * it under the terms of the GNU General Public License as published by
4950 + * the Free Software Foundation; version 2 of the License
4951 + *
4952 + * This program is distributed in the hope that it will be useful,
4953 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
4954 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
4955 + * GNU General Public License for more details.
4956 + *
4957 + * You should have received a copy of the GNU General Public License
4958 + * along with this program; if not, write to the Free Software
4959 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
4960 + *
4961 + * Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
4962 + */
4963 +
4964 +#include <linux/module.h>
4965 +
4966 +#include <asm/mach-ralink/ralink_regs.h>
4967 +
4968 +#include "ralink_soc_eth.h"
4969 +
4970 +#define RT305X_RESET_FE BIT(21)
4971 +#define RT305X_RESET_ESW BIT(23)
4972 +#define SYSC_REG_RESET_CTRL 0x034
4973 +
4974 +static const u32 rt5350_reg_table[FE_REG_COUNT] = {
4975 + [FE_REG_PDMA_GLO_CFG] = RT5350_PDMA_GLO_CFG,
4976 + [FE_REG_PDMA_RST_CFG] = RT5350_PDMA_RST_CFG,
4977 + [FE_REG_DLY_INT_CFG] = RT5350_DLY_INT_CFG,
4978 + [FE_REG_TX_BASE_PTR0] = RT5350_TX_BASE_PTR0,
4979 + [FE_REG_TX_MAX_CNT0] = RT5350_TX_MAX_CNT0,
4980 + [FE_REG_TX_CTX_IDX0] = RT5350_TX_CTX_IDX0,
4981 + [FE_REG_RX_BASE_PTR0] = RT5350_RX_BASE_PTR0,
4982 + [FE_REG_RX_MAX_CNT0] = RT5350_RX_MAX_CNT0,
4983 + [FE_REG_RX_CALC_IDX0] = RT5350_RX_CALC_IDX0,
4984 + [FE_REG_FE_INT_ENABLE] = RT5350_FE_INT_ENABLE,
4985 + [FE_REG_FE_INT_STATUS] = RT5350_FE_INT_STATUS,
4986 + [FE_REG_FE_DMA_VID_BASE] = 0,
4987 +};
4988 +
4989 +static void rt305x_fe_reset(void)
4990 +{
4991 + rt_sysc_w32(RT305X_RESET_FE, SYSC_REG_RESET_CTRL);
4992 + rt_sysc_w32(0, SYSC_REG_RESET_CTRL);
4993 +}
4994 +
4995 +static void rt5350_set_mac(struct fe_priv *priv, unsigned char *mac)
4996 +{
4997 + unsigned long flags;
4998 +
4999 + spin_lock_irqsave(&priv->page_lock, flags);
5000 + fe_w32((mac[0] << 8) | mac[1], RT5350_SDM_MAC_ADRH);
5001 + fe_w32((mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5],
5002 + RT5350_SDM_MAC_ADRL);
5003 + spin_unlock_irqrestore(&priv->page_lock, flags);
5004 +}
5005 +
5006 +static void rt5350_fwd_config(struct fe_priv *priv)
5007 +{
5008 + unsigned long sysclk = priv->sysclk;
5009 +
5010 + if (sysclk) {
5011 + sysclk /= FE_US_CYC_CNT_DIVISOR;
5012 + sysclk <<= FE_US_CYC_CNT_SHIFT;
5013 +
5014 + fe_w32((fe_r32(FE_FE_GLO_CFG) &
5015 + ~(FE_US_CYC_CNT_MASK << FE_US_CYC_CNT_SHIFT)) | sysclk,
5016 + FE_FE_GLO_CFG);
5017 + }
5018 +
5019 + fe_w32(fe_r32(RT5350_SDM_CFG) & ~0xffff, RT5350_SDM_CFG);
5020 + fe_w32(fe_r32(RT5350_SDM_CFG) | RT5350_SDM_ICS_EN | RT5350_SDM_TCS_EN | RT5350_SDM_UCS_EN,
5021 + RT5350_SDM_CFG);
5022 +}
5023 +
5024 +static void rt5350_fe_reset(void)
5025 +{
5026 + rt_sysc_w32(RT305X_RESET_FE | RT305X_RESET_ESW, SYSC_REG_RESET_CTRL);
5027 + rt_sysc_w32(0, SYSC_REG_RESET_CTRL);
5028 +}
5029 +
5030 +static struct fe_soc_data rt3050_data = {
5031 + .mac = { 0x00, 0x11, 0x22, 0x33, 0x44, 0x55 },
5032 + .reset_fe = rt305x_fe_reset,
5033 + .min_pkt_len = 64,
5034 + .pdma_glo_cfg = FE_PDMA_SIZE_4DWORDS,
5035 + .checksum_bit = RX_DMA_L4VALID,
5036 + .rx_dly_int = FE_RX_DLY_INT,
5037 + .tx_dly_int = FE_TX_DLY_INT,
5038 +};
5039 +
5040 +static struct fe_soc_data rt5350_data = {
5041 + .mac = { 0x00, 0x11, 0x22, 0x33, 0x44, 0x55 },
5042 + .reg_table = rt5350_reg_table,
5043 + .reset_fe = rt5350_fe_reset,
5044 + .set_mac = rt5350_set_mac,
5045 + .fwd_config = rt5350_fwd_config,
5046 + .min_pkt_len = 64,
5047 + .pdma_glo_cfg = FE_PDMA_SIZE_4DWORDS,
5048 + .checksum_bit = RX_DMA_L4VALID,
5049 + .rx_dly_int = RT5350_RX_DLY_INT,
5050 + .tx_dly_int = RT5350_TX_DLY_INT,
5051 +};
5052 +
5053 +const struct of_device_id of_fe_match[] = {
5054 + { .compatible = "ralink,rt3050-eth", .data = &rt3050_data },
5055 + { .compatible = "ralink,rt5350-eth", .data = &rt5350_data },
5056 + {},
5057 +};
5058 +
5059 +MODULE_DEVICE_TABLE(of, of_fe_match);
5060 diff --git a/drivers/net/ethernet/ralink/soc_rt3883.c b/drivers/net/ethernet/ralink/soc_rt3883.c
5061 new file mode 100644
5062 index 0000000..c660529c
5063 --- /dev/null
5064 +++ b/drivers/net/ethernet/ralink/soc_rt3883.c
5065 @@ -0,0 +1,60 @@
5066 +/*
5067 + * This program is free software; you can redistribute it and/or modify
5068 + * it under the terms of the GNU General Public License as published by
5069 + * the Free Software Foundation; version 2 of the License
5070 + *
5071 + * This program is distributed in the hope that it will be useful,
5072 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
5073 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
5074 + * GNU General Public License for more details.
5075 + *
5076 + * You should have received a copy of the GNU General Public License
5077 + * along with this program; if not, write to the Free Software
5078 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
5079 + *
5080 + * Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
5081 + */
5082 +
5083 +#include <linux/module.h>
5084 +
5085 +#include <asm/mach-ralink/ralink_regs.h>
5086 +
5087 +#include "ralink_soc_eth.h"
5088 +#include "mdio_rt2880.h"
5089 +
5090 +#define RT3883_SYSC_REG_RSTCTRL 0x34
5091 +#define RT3883_RSTCTRL_FE BIT(21)
5092 +
5093 +static void rt3883_fe_reset(void)
5094 +{
5095 + u32 t;
5096 +
5097 + t = rt_sysc_r32(RT3883_SYSC_REG_RSTCTRL);
5098 + t |= RT3883_RSTCTRL_FE;
5099 + rt_sysc_w32(t , RT3883_SYSC_REG_RSTCTRL);
5100 +
5101 + t &= ~RT3883_RSTCTRL_FE;
5102 + rt_sysc_w32(t, RT3883_SYSC_REG_RSTCTRL);
5103 +}
5104 +
5105 +static struct fe_soc_data rt3883_data = {
5106 + .mac = { 0x00, 0x11, 0x22, 0x33, 0x44, 0x55 },
5107 + .reset_fe = rt3883_fe_reset,
5108 + .min_pkt_len = 64,
5109 + .pdma_glo_cfg = FE_PDMA_SIZE_4DWORDS,
5110 + .rx_dly_int = FE_RX_DLY_INT,
5111 + .tx_dly_int = FE_TX_DLY_INT,
5112 + .checksum_bit = RX_DMA_L4VALID,
5113 + .mdio_read = rt2880_mdio_read,
5114 + .mdio_write = rt2880_mdio_write,
5115 + .mdio_adjust_link = rt2880_mdio_link_adjust,
5116 + .port_init = rt2880_port_init,
5117 +};
5118 +
5119 +const struct of_device_id of_fe_match[] = {
5120 + { .compatible = "ralink,rt3883-eth", .data = &rt3883_data },
5121 + {},
5122 +};
5123 +
5124 +MODULE_DEVICE_TABLE(of, of_fe_match);
5125 +
5126 --
5127 1.7.10.4
5128
OpenWrt Source Repository