1 From b915fe7cd934160bfaf2cd52f03c118abcae2419 Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Sun, 17 Nov 2013 17:41:46 +0100
4 Subject: [PATCH 43/57] mtd: ralink: add mt7620 nand driver
6 Signed-off-by: John Crispin <blogic@openwrt.org>
8 drivers/mtd/maps/Kconfig | 4 +
9 drivers/mtd/maps/Makefile | 2 +
10 drivers/mtd/maps/ralink_nand.c | 2136 ++++++++++++++++++++++++++++++++++++++++
11 drivers/mtd/maps/ralink_nand.h | 232 +++++
12 4 files changed, 2374 insertions(+)
13 create mode 100644 drivers/mtd/maps/ralink_nand.c
14 create mode 100644 drivers/mtd/maps/ralink_nand.h
16 --- a/drivers/mtd/maps/Kconfig
17 +++ b/drivers/mtd/maps/Kconfig
18 @@ -399,4 +399,8 @@ config MTD_LATCH_ADDR
20 If compiled as a module, it will be called latch-addr-flash.
22 +config MTD_NAND_MT7620
23 + tristate "Support for NAND on Mediatek MT7620"
24 + depends on RALINK && SOC_MT7620
27 --- a/drivers/mtd/maps/Makefile
28 +++ b/drivers/mtd/maps/Makefile
29 @@ -43,3 +43,5 @@ obj-$(CONFIG_MTD_VMU) += vmu-flash.o
30 obj-$(CONFIG_MTD_GPIO_ADDR) += gpio-addr-flash.o
31 obj-$(CONFIG_MTD_LATCH_ADDR) += latch-addr-flash.o
32 obj-$(CONFIG_MTD_LANTIQ) += lantiq-flash.o
33 +obj-$(CONFIG_MTD_NAND_MT7620) += ralink_nand.o
36 +++ b/drivers/mtd/maps/ralink_nand.c
39 +#include <linux/device.h>
41 +#include <linux/slab.h>
42 +#include <linux/mtd/mtd.h>
43 +#include <linux/delay.h>
44 +#include <linux/module.h>
45 +#include <linux/interrupt.h>
46 +#include <linux/dma-mapping.h>
47 +#include <linux/mtd/partitions.h>
49 +#include <linux/delay.h>
50 +#include <linux/sched.h>
51 +#include <linux/of.h>
52 +#include <linux/platform_device.h>
54 +#include "ralink_nand.h"
55 +#ifdef RANDOM_GEN_BAD_BLOCK
56 +#include <linux/random.h>
59 +#define LARGE_MTD_BOOT_PART_SIZE (CFG_BLOCKSIZE<<2)
60 +#define LARGE_MTD_CONFIG_PART_SIZE (CFG_BLOCKSIZE<<2)
61 +#define LARGE_MTD_FACTORY_PART_SIZE (CFG_BLOCKSIZE<<1)
64 +#define BLOCK_ALIGNED(a) ((a) & (CFG_BLOCKSIZE - 1))
66 +#define READ_STATUS_RETRY 1000
68 +struct mtd_info *ranfc_mtd = NULL;
72 +static int ranfc_bbt = 1;
73 +#if defined (WORKAROUND_RX_BUF_OV)
74 +static int ranfc_verify = 1;
76 +static u32 nand_addrlen;
79 +module_param(ranfc_debug, int, 0644);
80 +module_param(ranfc_bbt, int, 0644);
81 +module_param(ranfc_verify, int, 0644);
85 +#define ra_dbg(args...) do { if (ranfc_debug) printk(args); } while(0)
87 +#define ra_dbg(args...)
90 +#define CLEAR_INT_STATUS() ra_outl(NFC_INT_ST, ra_inl(NFC_INT_ST))
91 +#define NFC_TRANS_DONE() (ra_inl(NFC_INT_ST) & INT_ST_ND_DONE)
93 +int is_nand_page_2048 = 0;
94 +const unsigned int nand_size_map[2][3] = {{25, 30, 30}, {20, 27, 30}};
96 +static int nfc_wait_ready(int snooze_ms);
98 +static const char * const mtk_probe_types[] = { "cmdlinepart", "ofpart", NULL };
103 +static int nfc_chip_reset(void)
107 + //ra_dbg("%s:\n", __func__);
109 + // reset nand flash
110 + ra_outl(NFC_CMD1, 0x0);
111 + ra_outl(NFC_CMD2, 0xff);
112 + ra_outl(NFC_ADDR, 0x0);
113 + ra_outl(NFC_CONF, 0x0411);
115 + status = nfc_wait_ready(5); //erase wait 5us
116 + if (status & NAND_STATUS_FAIL) {
117 + printk("%s: fail \n", __func__);
120 + return (int)(status & NAND_STATUS_FAIL);
127 + * clear NFC and flash chip.
129 +static int nfc_all_reset(void)
133 + ra_dbg("%s: \n", __func__);
135 + // reset controller
136 + ra_outl(NFC_CTRL, ra_inl(NFC_CTRL) | 0x02); //clear data buffer
137 + ra_outl(NFC_CTRL, ra_inl(NFC_CTRL) & ~0x02); //clear data buffer
139 + CLEAR_INT_STATUS();
141 + retry = READ_STATUS_RETRY;
142 + while ((ra_inl(NFC_INT_ST) & 0x02) != 0x02 && retry--);
144 + printk("nfc_all_reset: clean buffer fail \n");
148 + retry = READ_STATUS_RETRY;
149 + while ((ra_inl(NFC_STATUS) & 0x1) != 0x0 && retry--) { //fixme, controller is busy ?
158 +/** NOTICE: only called by nfc_wait_ready().
159 + * @return -1, nfc can not get transction done
162 +static int _nfc_read_status(char *status)
164 + unsigned long cmd1, conf;
165 + int int_st, nfc_st;
169 + conf = 0x000101 | (1 << 20);
171 + //fixme, should we check nfc status?
172 + CLEAR_INT_STATUS();
174 + ra_outl(NFC_CMD1, cmd1);
175 + ra_outl(NFC_CONF, conf);
178 + * 1. since we have no wired ready signal, directly
179 + * calling this function is not gurantee to read right status under ready state.
180 + * 2. the other side, we can not determine how long to become ready, this timeout retry is nonsense.
181 + * 3. SUGGESTION: call nfc_read_status() from nfc_wait_ready(),
182 + * that is aware about caller (in sementics) and has snooze plused nfc ND_DONE.
184 + retry = READ_STATUS_RETRY;
186 + nfc_st = ra_inl(NFC_STATUS);
187 + int_st = ra_inl(NFC_INT_ST);
190 + } while (!(int_st & INT_ST_RX_BUF_RDY) && retry--);
192 + if (!(int_st & INT_ST_RX_BUF_RDY)) {
193 + printk("nfc_read_status: NFC fail, int_st(%x), retry:%x. nfc:%x, reset nfc and flash. \n",
194 + int_st, retry, nfc_st);
196 + *status = NAND_STATUS_FAIL;
200 + *status = (char)(le32_to_cpu(ra_inl(NFC_DATA)) & 0x0ff);
205 + * @return !0, chip protect.
206 + * @return 0, chip not protected.
208 +static int nfc_check_wp(void)
210 + /* Check the WP bit */
211 +#if !defined CONFIG_NOT_SUPPORT_WP
212 + return !!(ra_inl(NFC_CTRL) & 0x01);
217 + ret = _nfc_read_status(&result);
218 + //FIXME, if ret < 0
220 + return !(result & NAND_STATUS_WP);
224 +#if !defined CONFIG_NOT_SUPPORT_RB
226 + * @return !0, chip ready.
227 + * @return 0, chip busy.
229 +static int nfc_device_ready(void)
231 + /* Check the ready */
232 + return !!(ra_inl(NFC_STATUS) & 0x04);
238 + * generic function to get data from flash.
239 + * @return data length reading from flash.
241 +static int _ra_nand_pull_data(char *buf, int len, int use_gdma)
243 +#ifdef RW_DATA_BY_BYTE
246 + __u32 *p = (__u32 *)buf;
249 + unsigned int ret_data;
252 + // receive data by use_gdma
254 + //if (_ra_nand_dma_pull((unsigned long)p, len)) {
256 + printk("%s: fail \n", __func__);
257 + len = -1; //return error
263 + //fixme: retry count size?
264 + retry = READ_STATUS_RETRY;
267 + int_st = ra_inl(NFC_INT_ST);
268 + if (int_st & INT_ST_RX_BUF_RDY) {
270 + ret_data = ra_inl(NFC_DATA);
271 + ra_outl(NFC_INT_ST, INT_ST_RX_BUF_RDY);
272 +#ifdef RW_DATA_BY_BYTE
273 + ret_size = sizeof(unsigned int);
274 + ret_size = min(ret_size, len);
276 + while (ret_size-- > 0) {
277 + //nfc is little endian
278 + *p++ = ret_data & 0x0ff;
282 + ret_size = min(len, 4);
287 + __u8 *q = (__u8 *)p;
288 + while (ret_size-- > 0) {
289 + *q++ = ret_data & 0x0ff;
295 + retry = READ_STATUS_RETRY;
297 + else if (int_st & INT_ST_ND_DONE) {
307 +#ifdef RW_DATA_BY_BYTE
308 + return (int)(p - buf);
310 + return ((int)p - (int)buf);
315 + * generic function to put data into flash.
316 + * @return data length writing into flash.
318 +static int _ra_nand_push_data(char *buf, int len, int use_gdma)
320 +#ifdef RW_DATA_BY_BYTE
323 + __u32 *p = (__u32 *)buf;
326 + unsigned int tx_data = 0;
327 + int tx_size, iter = 0;
329 + // receive data by use_gdma
331 + //if (_ra_nand_dma_push((unsigned long)p, len))
334 + printk("%s: fail \n", __func__);
339 + retry = READ_STATUS_RETRY;
341 + int_st = ra_inl(NFC_INT_ST);
342 + if (int_st & INT_ST_TX_BUF_RDY) {
343 +#ifdef RW_DATA_BY_BYTE
344 + tx_size = min(len, (int)sizeof(unsigned long));
345 + for (iter = 0; iter < tx_size; iter++) {
346 + tx_data |= (*p++ << (8*iter));
349 + tx_size = min(len, 4);
353 + __u8 *q = (__u8 *)p;
354 + for (iter = 0; iter < tx_size; iter++)
355 + tx_data |= (*q++ << (8*iter));
359 + ra_outl(NFC_INT_ST, INT_ST_TX_BUF_RDY);
360 + ra_outl(NFC_DATA, tx_data);
362 + retry = READ_STATUS_RETRY;
364 + else if (int_st & INT_ST_ND_DONE) {
370 + ra_dbg("%s p:%p buf:%p \n", __func__, p, buf);
377 +#ifdef RW_DATA_BY_BYTE
378 + return (int)(p - buf);
380 + return ((int)p - (int)buf);
385 +static int nfc_select_chip(struct ra_nand_chip *ra, int chipnr)
387 +#if (CONFIG_NUMCHIPS == 1)
388 + if (!(chipnr < CONFIG_NUMCHIPS))
396 +/** @return -1: chip_select fail
397 + * 0 : both CE and WP==0 are OK
398 + * 1 : CE OK and WP==1
400 +static int nfc_enable_chip(struct ra_nand_chip *ra, unsigned int offs, int read_only)
402 + int chipnr = offs >> ra->chip_shift;
404 + ra_dbg("%s: offs:%x read_only:%x \n", __func__, offs, read_only);
406 + chipnr = nfc_select_chip(ra, chipnr);
408 + printk("%s: chip select error, offs(%x)\n", __func__, offs);
413 + return nfc_check_wp();
418 +/** wait nand chip becomeing ready and return queried status.
419 + * @param snooze: sleep time in ms unit before polling device ready.
420 + * @return status of nand chip
421 + * @return NAN_STATUS_FAIL if something unexpected.
423 +static int nfc_wait_ready(int snooze_ms)
429 + if (snooze_ms == 0)
432 + schedule_timeout(snooze_ms * HZ / 1000);
434 + snooze_ms = retry = snooze_ms *1000000 / 100 ; // ndelay(100)
436 + while (!NFC_TRANS_DONE() && retry--) {
437 + if (!cond_resched())
441 + if (!NFC_TRANS_DONE()) {
442 + printk("nfc_wait_ready: no transaction done \n");
443 + return NAND_STATUS_FAIL;
446 +#if !defined (CONFIG_NOT_SUPPORT_RB)
448 + while(!(status = nfc_device_ready()) && retry--) {
453 + printk("nfc_wait_ready: no device ready. \n");
454 + return NAND_STATUS_FAIL;
457 + _nfc_read_status(&status);
462 + _nfc_read_status(&status);
463 + if (status & NAND_STATUS_READY)
468 + printk("nfc_wait_ready 2: no device ready, status(%x). \n", status);
475 + * return 0: erase OK
476 + * return -EIO: fail
478 +int nfc_erase_block(struct ra_nand_chip *ra, int row_addr)
480 + unsigned long cmd1, cmd2, bus_addr, conf;
485 + bus_addr = row_addr;
486 + conf = 0x00511 | ((CFG_ROW_ADDR_CYCLE)<<16);
489 + ra_dbg("%s: cmd1: %lx, cmd2:%lx bus_addr: %lx, conf: %lx \n",
490 + __func__, cmd1, cmd2, bus_addr, conf);
492 + //fixme, should we check nfc status?
493 + CLEAR_INT_STATUS();
495 + ra_outl(NFC_CMD1, cmd1);
496 + ra_outl(NFC_CMD2, cmd2);
497 + ra_outl(NFC_ADDR, bus_addr);
498 + ra_outl(NFC_CONF, conf);
500 + status = nfc_wait_ready(3); //erase wait 3ms
501 + if (status & NAND_STATUS_FAIL) {
502 + printk("%s: fail \n", __func__);
510 +static inline int _nfc_read_raw_data(int cmd1, int cmd2, int bus_addr, int bus_addr2, int conf, char *buf, int len, int flags)
514 + CLEAR_INT_STATUS();
515 + ra_outl(NFC_CMD1, cmd1);
516 + ra_outl(NFC_CMD2, cmd2);
517 + ra_outl(NFC_ADDR, bus_addr);
518 +#if defined (CONFIG_RALINK_RT6855) || defined (CONFIG_RALINK_RT6855A) || \
519 + defined (CONFIG_RALINK_MT7620) || defined (CONFIG_RALINK_MT7621)
520 + ra_outl(NFC_ADDR2, bus_addr2);
522 + ra_outl(NFC_CONF, conf);
524 + ret = _ra_nand_pull_data(buf, len, 0);
526 + ra_dbg("%s: ret:%x (%x) \n", __func__, ret, len);
527 + return NAND_STATUS_FAIL;
530 + //FIXME, this section is not necessary
531 + ret = nfc_wait_ready(0); //wait ready
532 + /* to prevent the DATA FIFO 's old data from next operation */
533 + ra_outl(NFC_CTRL, ra_inl(NFC_CTRL) | 0x02); //clear data buffer
534 + ra_outl(NFC_CTRL, ra_inl(NFC_CTRL) & ~0x02); //clear data buffer
536 + if (ret & NAND_STATUS_FAIL) {
537 + printk("%s: fail \n", __func__);
538 + return NAND_STATUS_FAIL;
544 +static inline int _nfc_write_raw_data(int cmd1, int cmd3, int bus_addr, int bus_addr2, int conf, char *buf, int len, int flags)
548 + CLEAR_INT_STATUS();
549 + ra_outl(NFC_CMD1, cmd1);
550 + ra_outl(NFC_CMD3, cmd3);
551 + ra_outl(NFC_ADDR, bus_addr);
552 +#if defined (CONFIG_RALINK_RT6855) || defined (CONFIG_RALINK_RT6855A) || \
553 + defined (CONFIG_RALINK_MT7620) || defined (CONFIG_RALINK_MT7621)
554 + ra_outl(NFC_ADDR2, bus_addr2);
556 + ra_outl(NFC_CONF, conf);
558 + ret = _ra_nand_push_data(buf, len, 0);
560 + ra_dbg("%s: ret:%x (%x) \n", __func__, ret, len);
561 + return NAND_STATUS_FAIL;
564 + ret = nfc_wait_ready(1); //write wait 1ms
565 + /* to prevent the DATA FIFO 's old data from next operation */
566 + ra_outl(NFC_CTRL, ra_inl(NFC_CTRL) | 0x02); //clear data buffer
567 + ra_outl(NFC_CTRL, ra_inl(NFC_CTRL) & ~0x02); //clear data buffer
569 + if (ret & NAND_STATUS_FAIL) {
570 + printk("%s: fail \n", __func__);
571 + return NAND_STATUS_FAIL;
581 +int nfc_read_oob(struct ra_nand_chip *ra, int page, unsigned int offs, char *buf, int len, int flags)
583 + unsigned int cmd1 = 0, cmd2 = 0, conf = 0;
584 + unsigned int bus_addr = 0, bus_addr2 = 0;
585 + unsigned int ecc_en;
589 + int pages_perblock = 1<<(ra->erase_shift - ra->page_shift);
590 + // constrain of nfc read function
592 +#if defined (WORKAROUND_RX_BUF_OV)
593 + BUG_ON (len > 60); //problem of rx-buffer overrun
595 + BUG_ON (offs >> ra->oob_shift); //page boundry
596 + BUG_ON ((unsigned int)(((offs + len) >> ra->oob_shift) + page) >
597 + ((page + pages_perblock) & ~(pages_perblock-1))); //block boundry
599 + use_gdma = flags & FLAG_USE_GDMA;
600 + ecc_en = flags & FLAG_ECC_EN;
601 + bus_addr = (page << (CFG_COLUMN_ADDR_CYCLE*8)) | (offs & ((1<<CFG_COLUMN_ADDR_CYCLE*8) - 1));
603 + if (is_nand_page_2048) {
604 + bus_addr += CFG_PAGESIZE;
605 + bus_addr2 = page >> (CFG_COLUMN_ADDR_CYCLE*8);
608 + conf = 0x000511| ((CFG_ADDR_CYCLE)<<16) | (len << 20);
612 + conf = 0x000141| ((CFG_ADDR_CYCLE)<<16) | (len << 20);
619 + ra_dbg("%s: cmd1:%x, bus_addr:%x, conf:%x, len:%x, flag:%x\n",
620 + __func__, cmd1, bus_addr, conf, len, flags);
622 + status = _nfc_read_raw_data(cmd1, cmd2, bus_addr, bus_addr2, conf, buf, len, flags);
623 + if (status & NAND_STATUS_FAIL) {
624 + printk("%s: fail\n", __func__);
635 +int nfc_write_oob(struct ra_nand_chip *ra, int page, unsigned int offs, char *buf, int len, int flags)
637 + unsigned int cmd1 = 0, cmd3=0, conf = 0;
638 + unsigned int bus_addr = 0, bus_addr2 = 0;
642 + int pages_perblock = 1<<(ra->erase_shift - ra->page_shift);
643 + // constrain of nfc read function
645 + BUG_ON (offs >> ra->oob_shift); //page boundry
646 + BUG_ON ((unsigned int)(((offs + len) >> ra->oob_shift) + page) >
647 + ((page + pages_perblock) & ~(pages_perblock-1))); //block boundry
649 + use_gdma = flags & FLAG_USE_GDMA;
650 + bus_addr = (page << (CFG_COLUMN_ADDR_CYCLE*8)) | (offs & ((1<<CFG_COLUMN_ADDR_CYCLE*8) - 1));
652 + if (is_nand_page_2048) {
655 + bus_addr += CFG_PAGESIZE;
656 + bus_addr2 = page >> (CFG_COLUMN_ADDR_CYCLE*8);
657 + conf = 0x001123 | ((CFG_ADDR_CYCLE)<<16) | ((len) << 20);
662 + conf = 0x001223 | ((CFG_ADDR_CYCLE)<<16) | ((len) << 20);
668 + ra_dbg("%s: cmd1: %x, cmd3: %x bus_addr: %x, conf: %x, len:%x\n",
669 + __func__, cmd1, cmd3, bus_addr, conf, len);
671 + status = _nfc_write_raw_data(cmd1, cmd3, bus_addr, bus_addr2, conf, buf, len, flags);
672 + if (status & NAND_STATUS_FAIL) {
673 + printk("%s: fail \n", __func__);
681 +int nfc_read_page(struct ra_nand_chip *ra, char *buf, int page, int flags);
682 +int nfc_write_page(struct ra_nand_chip *ra, char *buf, int page, int flags);
685 +#if !defined (WORKAROUND_RX_BUF_OV)
686 +static int one_bit_correction(char *ecc, char *expected, int *bytes, int *bits);
687 +int nfc_ecc_verify(struct ra_nand_chip *ra, char *buf, int page, int mode)
693 + //ra_dbg("%s, page:%x mode:%d\n", __func__, page, mode);
695 + if (mode == FL_WRITING) {
696 + int len = CFG_PAGESIZE + CFG_PAGE_OOBSIZE;
697 + int conf = 0x000141| ((CFG_ADDR_CYCLE)<<16) | (len << 20);
698 + conf |= (1<<3); //(ecc_en)
699 + //conf |= (1<<2); // (use_gdma)
701 + p = ra->readback_buffers;
702 + ret = nfc_read_page(ra, ra->readback_buffers, page, FLAG_ECC_EN);
706 + //FIXME, double comfirm
707 + printk("%s: read back fail, try again \n",__func__);
708 + ret = nfc_read_page(ra, ra->readback_buffers, page, FLAG_ECC_EN);
710 + printk("\t%s: read back fail agian \n",__func__);
714 + else if (mode == FL_READING) {
722 + if (!is_nand_page_2048) {
723 + ecc = ra_inl(NFC_ECC);
724 + if (ecc == 0) //clean page.
727 + for (i=0; i<CONFIG_ECC_BYTES; i++) {
728 + int eccpos = CONFIG_ECC_OFFSET + i;
729 + if (*(p + eccpos) != (char)0xff)
731 + if (i == CONFIG_ECC_BYTES - 1) {
732 + printk("skip ecc 0xff at page %x\n", page);
736 + for (i=0; i<CONFIG_ECC_BYTES; i++) {
737 + int eccpos = CONFIG_ECC_OFFSET + i;
738 + if (*(p + eccpos) != *(e + i)) {
739 + printk("%s mode:%s, invalid ecc, page: %x read:%x %x %x, ecc:%x \n",
740 + __func__, (mode == FL_READING)?"read":"write", page,
741 + *(p+ CONFIG_ECC_OFFSET), *(p+ CONFIG_ECC_OFFSET+1), *(p+ CONFIG_ECC_OFFSET +2), ecc);
746 +#if defined (CONFIG_RALINK_RT6855) || defined (CONFIG_RALINK_RT6855A) || \
747 + defined (CONFIG_RALINK_MT7620) || defined (CONFIG_RALINK_MT7621)
749 + int ecc2, ecc3, ecc4, qsz;
750 + char *e2, *e3, *e4;
751 + int correction_flag = 0;
752 + ecc = ra_inl(NFC_ECC_P1);
753 + ecc2 = ra_inl(NFC_ECC_P2);
754 + ecc3 = ra_inl(NFC_ECC_P3);
755 + ecc4 = ra_inl(NFC_ECC_P4);
760 + qsz = CFG_PAGE_OOBSIZE / 4;
761 + if (ecc == 0 && ecc2 == 0 && ecc3 == 0 && ecc4 == 0)
763 + for (i=0; i<CONFIG_ECC_BYTES; i++) {
764 + int eccpos = CONFIG_ECC_OFFSET + i;
765 + if (*(p + eccpos) != (char)0xff)
767 + else if (*(p + eccpos + qsz) != (char)0xff)
769 + else if (*(p + eccpos + qsz*2) != (char)0xff)
771 + else if (*(p + eccpos + qsz*3) != (char)0xff)
773 + if (i == CONFIG_ECC_BYTES - 1) {
774 + printk("skip ecc 0xff at page %x\n", page);
778 + for (i=0; i<CONFIG_ECC_BYTES; i++) {
779 + int eccpos = CONFIG_ECC_OFFSET + i;
780 + if (*(p + eccpos) != *(e + i)) {
781 + printk("%s mode:%s, invalid ecc, page: %x read:%x %x %x, ecc:%x \n",
782 + __func__, (mode == FL_READING)?"read":"write", page,
783 + *(p+ CONFIG_ECC_OFFSET), *(p+ CONFIG_ECC_OFFSET+1), *(p+ CONFIG_ECC_OFFSET +2), ecc);
784 + correction_flag |= 0x1;
786 + if (*(p + eccpos + qsz) != *(e2 + i)) {
787 + printk("%s mode:%s, invalid ecc2, page: %x read:%x %x %x, ecc2:%x \n",
788 + __func__, (mode == FL_READING)?"read":"write", page,
789 + *(p+CONFIG_ECC_OFFSET+qsz), *(p+ CONFIG_ECC_OFFSET+1+qsz), *(p+ CONFIG_ECC_OFFSET+2+qsz), ecc2);
790 + correction_flag |= 0x2;
792 + if (*(p + eccpos + qsz*2) != *(e3 + i)) {
793 + printk("%s mode:%s, invalid ecc3, page: %x read:%x %x %x, ecc3:%x \n",
794 + __func__, (mode == FL_READING)?"read":"write", page,
795 + *(p+CONFIG_ECC_OFFSET+qsz*2), *(p+ CONFIG_ECC_OFFSET+1+qsz*2), *(p+ CONFIG_ECC_OFFSET+2+qsz*2), ecc3);
796 + correction_flag |= 0x4;
798 + if (*(p + eccpos + qsz*3) != *(e4 + i)) {
799 + printk("%s mode:%s, invalid ecc4, page: %x read:%x %x %x, ecc4:%x \n",
800 + __func__, (mode == FL_READING)?"read":"write", page,
801 + *(p+CONFIG_ECC_OFFSET+qsz*3), *(p+ CONFIG_ECC_OFFSET+1+qsz*3), *(p+ CONFIG_ECC_OFFSET+2+qsz*3), ecc4);
802 + correction_flag |= 0x8;
806 + if (correction_flag)
808 + printk("trying to do correction!\n");
809 + if (correction_flag & 0x1)
812 + char *pBuf = p - CFG_PAGESIZE;
814 + if (one_bit_correction(p + CONFIG_ECC_OFFSET, e, &bytes, &bits) == 0)
816 + pBuf[bytes] = pBuf[bytes] ^ (1 << bits);
817 + printk("1. correct byte %d, bit %d!\n", bytes, bits);
821 + printk("failed to correct!\n");
826 + if (correction_flag & 0x2)
829 + char *pBuf = (p - CFG_PAGESIZE) + CFG_PAGESIZE/4;
831 + if (one_bit_correction((p + CONFIG_ECC_OFFSET + qsz), e2, &bytes, &bits) == 0)
833 + pBuf[bytes] = pBuf[bytes] ^ (1 << bits);
834 + printk("2. correct byte %d, bit %d!\n", bytes, bits);
838 + printk("failed to correct!\n");
842 + if (correction_flag & 0x4)
845 + char *pBuf = (p - CFG_PAGESIZE) + CFG_PAGESIZE/2;
847 + if (one_bit_correction((p + CONFIG_ECC_OFFSET + qsz * 2), e3, &bytes, &bits) == 0)
849 + pBuf[bytes] = pBuf[bytes] ^ (1 << bits);
850 + printk("3. correct byte %d, bit %d!\n", bytes, bits);
854 + printk("failed to correct!\n");
858 + if (correction_flag & 0x8)
861 + char *pBuf = (p - CFG_PAGESIZE) + CFG_PAGESIZE*3/4;
863 + if (one_bit_correction((p + CONFIG_ECC_OFFSET + qsz * 3), e4, &bytes, &bits) == 0)
865 + pBuf[bytes] = pBuf[bytes] ^ (1 << bits);
866 + printk("4. correct byte %d, bit %d!\n", bytes, bits);
870 + printk("failed to correct!\n");
886 +void ranfc_dump(void)
889 + for (i=0; i<11; i++) {
892 + printk("%x: %x \n", NFC_BASE + i*4, ra_inl(NFC_BASE + i*4));
897 + * @return 0, ecc OK or corrected.
898 + * @return NAND_STATUS_FAIL, ecc fail.
901 +int nfc_ecc_verify(struct ra_nand_chip *ra, char *buf, int page, int mode)
907 + if (ranfc_verify == 0)
910 + ra_dbg("%s, page:%x mode:%d\n", __func__, page, mode);
912 + if (mode == FL_WRITING) { // read back and memcmp
913 + ret = nfc_read_page(ra, ra->readback_buffers, page, FLAG_NONE);
914 + if (ret != 0) //double comfirm
915 + ret = nfc_read_page(ra, ra->readback_buffers, page, FLAG_NONE);
918 + printk("%s: mode:%x read back fail \n", __func__, mode);
921 + return memcmp(buf, ra->readback_buffers, 1<<ra->page_shift);
924 + if (mode == FL_READING) {
926 + if (ra->sandbox_page == 0)
929 + ret = nfc_write_page(ra, buf, ra->sandbox_page, FLAG_USE_GDMA | FLAG_ECC_EN);
931 + printk("%s, fail write sandbox_page \n", __func__);
936 + * The following command is actually not 'write' command to drive NFC to write flash.
937 + * However, it can make NFC to calculate ECC, that will be used to compare with original ones.
940 + unsigned int conf = 0x001223| (CFG_ADDR_CYCLE<<16) | (0x200 << 20) | (1<<3) | (1<<2);
941 + _nfc_write_raw_data(0xff, 0xff, ra->sandbox_page<<ra->page_shift, conf, buf, 0x200, FLAG_USE_GDMA);
944 + ecc = ra_inl(NFC_ECC);
945 + if (ecc == 0) //clean page.
948 + p = buf + (1<<ra->page_shift);
949 + for (i=0; i<CONFIG_ECC_BYTES; i++) {
950 + int eccpos = CONFIG_ECC_OFFSET + i;
951 + if (*(p + eccpos) != *(e + i)) {
952 + printk("%s mode:%s, invalid ecc, page: %x read:%x %x %x, write:%x \n",
953 + __func__, (mode == FL_READING)?"read":"write", page,
954 + *(p+ CONFIG_ECC_OFFSET), *(p+ CONFIG_ECC_OFFSET+1), *(p+ CONFIG_ECC_OFFSET +2), ecc);
956 + for (i=0; i<528; i++)
957 + printk("%-2x \n", *(buf + i));
972 + * @return -EIO, writing size is less than a page
975 +int nfc_read_page(struct ra_nand_chip *ra, char *buf, int page, int flags)
977 + unsigned int cmd1 = 0, cmd2 = 0, conf = 0;
978 + unsigned int bus_addr = 0, bus_addr2 = 0;
979 + unsigned int ecc_en;
984 + use_gdma = flags & FLAG_USE_GDMA;
985 + ecc_en = flags & FLAG_ECC_EN;
987 + page = page & (CFG_CHIPSIZE - 1); // chip boundary
988 + size = CFG_PAGESIZE + CFG_PAGE_OOBSIZE; //add oobsize
993 +#if defined (WORKAROUND_RX_BUF_OV)
994 + len = min(60, size);
998 + bus_addr = (page << (CFG_COLUMN_ADDR_CYCLE*8)) | (offs & ((1<<CFG_COLUMN_ADDR_CYCLE*8)-1));
999 + if (is_nand_page_2048) {
1000 + bus_addr2 = page >> (CFG_COLUMN_ADDR_CYCLE*8);
1003 + conf = 0x000511| ((CFG_ADDR_CYCLE)<<16) | (len << 20);
1006 + if (offs & ~(CFG_PAGESIZE-1))
1008 + else if (offs & ~((1<<CFG_COLUMN_ADDR_CYCLE*8)-1))
1013 + conf = 0x000141| ((CFG_ADDR_CYCLE)<<16) | (len << 20);
1015 +#if !defined (WORKAROUND_RX_BUF_OV)
1022 + status = _nfc_read_raw_data(cmd1, cmd2, bus_addr, bus_addr2, conf, buf+offs, len, flags);
1023 + if (status & NAND_STATUS_FAIL) {
1024 + printk("%s: fail \n", __func__);
1032 + // verify and correct ecc
1033 + if ((flags & (FLAG_VERIFY | FLAG_ECC_EN)) == (FLAG_VERIFY | FLAG_ECC_EN)) {
1034 + status = nfc_ecc_verify(ra, buf, page, FL_READING);
1035 + if (status != 0) {
1036 + printk("%s: fail, buf:%x, page:%x, flag:%x\n",
1037 + __func__, (unsigned int)buf, page, flags);
1042 + // fix,e not yet support
1043 + ra->buffers_page = -1; //cached
1051 + * @return -EIO, fail to write
1054 +int nfc_write_page(struct ra_nand_chip *ra, char *buf, int page, int flags)
1056 + unsigned int cmd1 = 0, cmd3, conf = 0;
1057 + unsigned int bus_addr = 0, bus_addr2 = 0;
1058 + unsigned int ecc_en;
1062 + uint8_t *oob = buf + (1<<ra->page_shift);
1064 + use_gdma = flags & FLAG_USE_GDMA;
1065 + ecc_en = flags & FLAG_ECC_EN;
1067 + oob[ra->badblockpos] = 0xff; //tag as good block.
1068 + ra->buffers_page = -1; //cached
1070 + page = page & (CFG_CHIPSIZE-1); //chip boundary
1071 + size = CFG_PAGESIZE + CFG_PAGE_OOBSIZE; //add oobsize
1072 + bus_addr = (page << (CFG_COLUMN_ADDR_CYCLE*8)); //write_page always write from offset 0.
1074 + if (is_nand_page_2048) {
1075 + bus_addr2 = page >> (CFG_COLUMN_ADDR_CYCLE*8);
1078 + conf = 0x001123| ((CFG_ADDR_CYCLE)<<16) | (size << 20);
1083 + conf = 0x001223| ((CFG_ADDR_CYCLE)<<16) | (size << 20);
1086 + conf |= (1<<3); //enable ecc
1091 + ra_dbg("nfc_write_page: cmd1: %x, cmd3: %x bus_addr: %x, conf: %x, len:%x\n",
1092 + cmd1, cmd3, bus_addr, conf, size);
1094 + status = _nfc_write_raw_data(cmd1, cmd3, bus_addr, bus_addr2, conf, buf, size, flags);
1095 + if (status & NAND_STATUS_FAIL) {
1096 + printk("%s: fail \n", __func__);
1101 + if (flags & FLAG_VERIFY) { // verify and correct ecc
1102 + status = nfc_ecc_verify(ra, buf, page, FL_WRITING);
1104 +#ifdef RANDOM_GEN_BAD_BLOCK
1105 + if (((random32() & 0x1ff) == 0x0) && (page >= 0x100)) // randomly create bad block
1107 + printk("hmm... create a bad block at page %x\n", (bus_addr >> 16));
1112 + if (status != 0) {
1113 + printk("%s: ecc_verify fail: ret:%x \n", __func__, status);
1114 + oob[ra->badblockpos] = 0x33;
1115 + page -= page % (CFG_BLOCKSIZE/CFG_PAGESIZE);
1116 + printk("create a bad block at page %x\n", page);
1117 + if (!is_nand_page_2048)
1118 + status = nfc_write_oob(ra, page, ra->badblockpos, oob+ra->badblockpos, 1, flags);
1121 + status = _nfc_write_raw_data(cmd1, cmd3, bus_addr, bus_addr2, conf, buf, size, flags);
1122 + nfc_write_oob(ra, page, 0, oob, 16, FLAG_NONE);
1129 + ra->buffers_page = page; //cached
1135 +/*************************************************************
1136 + * nand internal process
1137 + *************************************************************/
1140 + * nand_release_device - [GENERIC] release chip
1141 + * @mtd: MTD device structure
1143 + * Deselect, release chip lock and wake up anyone waiting on the device
1145 +static void nand_release_device(struct ra_nand_chip *ra)
1147 + /* De-select the NAND device */
1148 + nfc_select_chip(ra, -1);
1150 + /* Release the controller and the chip */
1151 + ra->state = FL_READY;
1153 + mutex_unlock(ra->controller);
1157 + * nand_get_device - [GENERIC] Get chip for selected access
1158 + * @chip: the nand chip descriptor
1159 + * @mtd: MTD device structure
1160 + * @new_state: the state which is requested
1162 + * Get the device and lock it for exclusive access
1165 +nand_get_device(struct ra_nand_chip *ra, int new_state)
1169 + ret = mutex_lock_interruptible(ra->controller);
1171 + ra->state = new_state;
1179 +/*************************************************************
1180 + * nand internal process
1181 + *************************************************************/
1183 +int nand_bbt_get(struct ra_nand_chip *ra, int block)
1186 + bits = block * BBTTAG_BITS;
1191 + return (ra->bbt[byte] >> bits) & BBTTAG_BITS_MASK;
1194 +int nand_bbt_set(struct ra_nand_chip *ra, int block, int tag)
1197 + bits = block * BBTTAG_BITS;
1202 + // If previous tag is bad, dont overwrite it
1203 + if (((ra->bbt[byte] >> bits) & BBTTAG_BITS_MASK) == BBT_TAG_BAD)
1205 + return BBT_TAG_BAD;
1208 + ra->bbt[byte] = (ra->bbt[byte] & ~(BBTTAG_BITS_MASK << bits)) | ((tag & BBTTAG_BITS_MASK) << bits);
1214 + * nand_block_checkbad - [GENERIC] Check if a block is marked bad
1215 + * @mtd: MTD device structure
1216 + * @ofs: offset from device start
1218 + * Check, if the block is bad. Either by reading the bad block table or
1219 + * calling of the scan function.
1221 +int nand_block_checkbad(struct ra_nand_chip *ra, loff_t offs)
1226 + char *str[]= {"UNK", "RES", "BAD", "GOOD"};
1228 + if (ranfc_bbt == 0)
1232 + // align with chip
1234 + offs = offs & ((1<<ra->chip_shift) -1);
1236 + page = offs >> ra->page_shift;
1237 + block = offs >> ra->erase_shift;
1240 + tag = nand_bbt_get(ra, block);
1242 + if (tag == BBT_TAG_UNKNOWN) {
1243 + ret = nfc_read_oob(ra, page, ra->badblockpos, (char*)&tag, 1, FLAG_NONE);
1245 + tag = ((le32_to_cpu(tag) & 0x0ff) == 0x0ff) ? BBT_TAG_GOOD : BBT_TAG_BAD;
1247 + tag = BBT_TAG_BAD;
1249 + nand_bbt_set(ra, block, tag);
1252 + if (tag != BBT_TAG_GOOD) {
1253 + printk("%s: offs:%x tag: %s \n", __func__, (unsigned int)offs, str[tag]);
1264 + * nand_block_markbad -
1266 +int nand_block_markbad(struct ra_nand_chip *ra, loff_t offs)
1273 + // align with chip
1274 + ra_dbg("%s offs: %x \n", __func__, (int)offs);
1276 + offs = offs & ((1<<ra->chip_shift) -1);
1278 + page = offs >> ra->page_shift;
1279 + block = offs >> ra->erase_shift;
1281 + tag = nand_bbt_get(ra, block);
1283 + if (tag == BBT_TAG_BAD) {
1284 + printk("%s: mark repeatedly \n", __func__);
1290 + ret = nfc_read_page(ra, ra->buffers, page, FLAG_NONE);
1292 + printk("%s: fail to read bad block tag \n", __func__);
1296 + ecc = &ra->buffers[(1<<ra->page_shift)+ra->badblockpos];
1297 + if (*ecc == (char)0x0ff) {
1300 + ret = nfc_write_page(ra, ra->buffers, page, FLAG_USE_GDMA);
1302 + printk("%s: fail to write bad block tag \n", __func__);
1308 + nand_bbt_set(ra, block, tag);
1314 +#if defined (WORKAROUND_RX_BUF_OV)
1316 + * to find a bad block for ecc verify of read_page
1318 +unsigned int nand_bbt_find_sandbox(struct ra_nand_chip *ra)
1321 + int chipsize = 1 << ra->chip_shift;
1322 + int blocksize = 1 << ra->erase_shift;
1325 + while (offs < chipsize) {
1326 + if (nand_block_checkbad(ra, offs)) //scan and verify the unknown tag
1328 + offs += blocksize;
1331 + if (offs >= chipsize) {
1332 + offs = chipsize - blocksize;
1335 + nand_bbt_set(ra, (unsigned int)offs>>ra->erase_shift, BBT_TAG_RES); // tag bbt only, instead of update badblockpos of flash.
1336 + return (offs >> ra->page_shift);
1343 + * nand_erase_nand - [Internal] erase block(s)
1344 + * @mtd: MTD device structure
1345 + * @instr: erase instruction
1346 + * @allowbbt: allow erasing the bbt area
1348 + * Erase one ore more blocks
1350 +int _nand_erase_nand(struct ra_nand_chip *ra, struct erase_info *instr)
1352 + int page, len, status, ret;
1353 + unsigned int addr, blocksize = 1<<ra->erase_shift;
1355 + ra_dbg("%s: start:%x, len:%x \n", __func__,
1356 + (unsigned int)instr->addr, (unsigned int)instr->len);
1358 +//#define BLOCK_ALIGNED(a) ((a) & (blocksize - 1)) // already defined
1360 + if (BLOCK_ALIGNED(instr->addr) || BLOCK_ALIGNED(instr->len)) {
1361 + ra_dbg("%s: erase block not aligned, addr:%x len:%x\n", __func__, instr->addr, instr->len);
1365 + instr->fail_addr = 0xffffffff;
1368 + addr = instr->addr;
1369 + instr->state = MTD_ERASING;
1373 + page = (int)(addr >> ra->page_shift);
1375 + /* select device and check wp */
1376 + if (nfc_enable_chip(ra, addr, 0)) {
1377 + printk("%s: nand is write protected \n", __func__);
1378 + instr->state = MTD_ERASE_FAILED;
1382 + /* if we have a bad block, we do not erase bad blocks */
1383 + if (nand_block_checkbad(ra, addr)) {
1384 + printk(KERN_WARNING "nand_erase: attempt to erase a "
1385 + "bad block at 0x%08x\n", addr);
1386 + instr->state = MTD_ERASE_FAILED;
1391 + * Invalidate the page cache, if we erase the block which
1392 + * contains the current cached page
1394 + if (BLOCK_ALIGNED(addr) == BLOCK_ALIGNED(ra->buffers_page << ra->page_shift))
1395 + ra->buffers_page = -1;
1397 + status = nfc_erase_block(ra, page);
1398 + /* See if block erase succeeded */
1400 + printk("%s: failed erase, page 0x%08x\n", __func__, page);
1401 + instr->state = MTD_ERASE_FAILED;
1402 + instr->fail_addr = (page << ra->page_shift);
1407 + /* Increment page address and decrement length */
1409 + addr += blocksize;
1412 + instr->state = MTD_ERASE_DONE;
1416 + ret = ((instr->state == MTD_ERASE_DONE) ? 0 : -EIO);
1417 + /* Do call back function */
1419 + mtd_erase_callback(instr);
1422 + nand_bbt_set(ra, addr >> ra->erase_shift, BBT_TAG_BAD);
1425 + /* Return more or less happy */
1430 +nand_write_oob_buf(struct ra_nand_chip *ra, uint8_t *buf, uint8_t *oob, size_t size,
1431 + int mode, int ooboffs)
1433 + size_t oobsize = 1<<ra->oob_shift;
1434 + struct nand_oobfree *free;
1435 + uint32_t woffs = ooboffs;
1438 + ra_dbg("%s: size:%x, mode:%x, offs:%x \n", __func__, size, mode, ooboffs);
1441 + case MTD_OPS_PLACE_OOB:
1443 + if (ooboffs > oobsize)
1446 + size = min(size, oobsize - ooboffs);
1447 + memcpy(buf + ooboffs, oob, size);
1451 + case MTD_OPS_AUTO_OOB:
1452 + if (ooboffs > ra->oob->oobavail)
1456 + for(free = ra->oob->oobfree; free->length && size; free++) {
1457 + int wlen = free->length - woffs;
1460 + /* Write request not from offset 0 ? */
1466 + bytes = min_t(size_t, size, wlen);
1467 + memcpy (buf + free->offset + woffs, oob, bytes);
1484 +static int nand_read_oob_buf(struct ra_nand_chip *ra, uint8_t *oob, size_t size,
1485 + int mode, int ooboffs)
1487 + size_t oobsize = 1<<ra->oob_shift;
1488 + uint8_t *buf = ra->buffers + (1<<ra->page_shift);
1491 + ra_dbg("%s: size:%x, mode:%x, offs:%x \n", __func__, size, mode, ooboffs);
1494 + case MTD_OPS_PLACE_OOB:
1496 + if (ooboffs > oobsize)
1499 + size = min(size, oobsize - ooboffs);
1500 + memcpy(oob, buf + ooboffs, size);
1503 + case MTD_OPS_AUTO_OOB: {
1504 + struct nand_oobfree *free;
1505 + uint32_t woffs = ooboffs;
1507 + if (ooboffs > ra->oob->oobavail)
1510 + size = min(size, ra->oob->oobavail - ooboffs);
1511 + for(free = ra->oob->oobfree; free->length && size; free++) {
1512 + int wlen = free->length - woffs;
1515 + /* Write request not from offset 0 ? */
1521 + bytes = min_t(size_t, size, wlen);
1522 + memcpy (oob, buf + free->offset + woffs, bytes);
1538 + * nand_do_write_ops - [Internal] NAND write with ECC
1539 + * @mtd: MTD device structure
1540 + * @to: offset to write to
1541 + * @ops: oob operations description structure
1543 + * NAND write with ECC
1545 +static int nand_do_write_ops(struct ra_nand_chip *ra, loff_t to,
1546 + struct mtd_oob_ops *ops)
1549 + uint32_t datalen = ops->len;
1550 + uint32_t ooblen = ops->ooblen;
1551 + uint8_t *oob = ops->oobbuf;
1552 + uint8_t *data = ops->datbuf;
1553 + int pagesize = (1<<ra->page_shift);
1554 + int pagemask = (pagesize -1);
1555 + int oobsize = 1<<ra->oob_shift;
1557 + //int i = 0; //for ra_dbg only
1559 + ra_dbg("%s: to:%x, ops data:%p, oob:%p datalen:%x ooblen:%x, ooboffs:%x oobmode:%x \n",
1560 + __func__, (unsigned int)to, data, oob, datalen, ooblen, ops->ooboffs, ops->mode);
1563 + ops->oobretlen = 0;
1566 + /* Invalidate the page cache, when we write to the cached page */
1567 + ra->buffers_page = -1;
1573 + // oob sequential (burst) write
1574 + if (datalen == 0 && ooblen) {
1575 + int len = ((ooblen + ops->ooboffs) + (ra->oob->oobavail - 1)) / ra->oob->oobavail * oobsize;
1577 + /* select chip, and check if it is write protected */
1578 + if (nfc_enable_chip(ra, addr, 0))
1581 + //FIXME, need sanity check of block boundary
1582 + page = (int)((to & ((1<<ra->chip_shift)-1)) >> ra->page_shift); //chip boundary
1583 + memset(ra->buffers, 0x0ff, pagesize);
1584 + //fixme, should we reserve the original content?
1585 + if (ops->mode == MTD_OPS_AUTO_OOB) {
1586 + nfc_read_oob(ra, page, 0, ra->buffers, len, FLAG_NONE);
1591 + nand_write_oob_buf(ra, ra->buffers, oob, ooblen, ops->mode, ops->ooboffs);
1592 + // write out buffer to chip
1593 + nfc_write_oob(ra, page, 0, ra->buffers, len, FLAG_USE_GDMA);
1596 + ops->oobretlen = ooblen;
1600 + // data sequential (burst) write
1601 + if (datalen && ooblen == 0) {
1602 + // ranfc can not support write_data_burst, since hw-ecc and fifo constraints..
1606 + while(datalen || ooblen) {
1612 + ra_dbg("%s (%d): addr:%x, ops data:%p, oob:%p datalen:%x ooblen:%x, ooboffs:%x \n",
1613 + __func__, i++, (unsigned int)addr, data, oob, datalen, ooblen, ops->ooboffs);
1615 + page = (int)((addr & ((1<<ra->chip_shift)-1)) >> ra->page_shift); //chip boundary
1617 + /* select chip, and check if it is write protected */
1618 + if (nfc_enable_chip(ra, addr, 0))
1622 + if (ops->mode == MTD_OPS_AUTO_OOB) {
1623 + //fixme, this path is not yet varified
1624 + nfc_read_oob(ra, page, 0, ra->buffers + pagesize, oobsize, FLAG_NONE);
1626 + if (oob && ooblen > 0) {
1627 + len = nand_write_oob_buf(ra, ra->buffers + pagesize, oob, ooblen, ops->mode, ops->ooboffs);
1632 + ops->oobretlen += len;
1637 + offs = addr & pagemask;
1638 + len = min_t(size_t, datalen, pagesize - offs);
1639 + if (data && len > 0) {
1640 + memcpy(ra->buffers + offs, data, len); // we can not sure ops->buf wether is DMA-able.
1644 + ops->retlen += len;
1646 + ecc_en = FLAG_ECC_EN;
1648 + ret = nfc_write_page(ra, ra->buffers, page, FLAG_USE_GDMA | FLAG_VERIFY |
1649 + ((ops->mode == MTD_OPS_RAW || ops->mode == MTD_OPS_PLACE_OOB) ? 0 : ecc_en ));
1651 + nand_bbt_set(ra, addr >> ra->erase_shift, BBT_TAG_BAD);
1655 + nand_bbt_set(ra, addr >> ra->erase_shift, BBT_TAG_GOOD);
1657 + addr = (page+1) << ra->page_shift;
1664 + * nand_do_read_ops - [Internal] Read data with ECC
1666 + * @mtd: MTD device structure
1667 + * @from: offset to read from
1668 + * @ops: oob ops structure
1670 + * Internal function. Called with chip held.
1672 +static int nand_do_read_ops(struct ra_nand_chip *ra, loff_t from,
1673 + struct mtd_oob_ops *ops)
1676 + uint32_t datalen = ops->len;
1677 + uint32_t ooblen = ops->ooblen;
1678 + uint8_t *oob = ops->oobbuf;
1679 + uint8_t *data = ops->datbuf;
1680 + int pagesize = (1<<ra->page_shift);
1681 + int pagemask = (pagesize -1);
1682 + loff_t addr = from;
1683 + //int i = 0; //for ra_dbg only
1685 + ra_dbg("%s: addr:%x, ops data:%p, oob:%p datalen:%x ooblen:%x, ooboffs:%x \n",
1686 + __func__, (unsigned int)addr, data, oob, datalen, ooblen, ops->ooboffs);
1689 + ops->oobretlen = 0;
1694 + while(datalen || ooblen) {
1699 + ra_dbg("%s (%d): addr:%x, ops data:%p, oob:%p datalen:%x ooblen:%x, ooboffs:%x \n",
1700 + __func__, i++, (unsigned int)addr, data, oob, datalen, ooblen, ops->ooboffs);
1702 + if (nfc_enable_chip(ra, addr, 1) < 0)
1705 + page = (int)((addr & ((1<<ra->chip_shift)-1)) >> ra->page_shift);
1707 + ret = nfc_read_page(ra, ra->buffers, page, FLAG_VERIFY |
1708 + ((ops->mode == MTD_OPS_RAW || ops->mode == MTD_OPS_PLACE_OOB) ? 0: FLAG_ECC_EN ));
1709 + //FIXME, something strange here, some page needs 2 more tries to guarantee read success.
1711 + printk("read again:\n");
1712 + ret = nfc_read_page(ra, ra->buffers, page, FLAG_VERIFY |
1713 + ((ops->mode == MTD_OPS_RAW || ops->mode == MTD_OPS_PLACE_OOB) ? 0: FLAG_ECC_EN ));
1716 + printk("read again fail \n");
1717 + nand_bbt_set(ra, addr >> ra->erase_shift, BBT_TAG_BAD);
1718 + if ((ret != -EUCLEAN) && (ret != -EBADMSG)) {
1722 + /* ecc verification fail, but data need to be returned. */
1726 + printk(" read agian susccess \n");
1731 + if (oob && ooblen > 0) {
1732 + len = nand_read_oob_buf(ra, oob, ooblen, ops->mode, ops->ooboffs);
1734 + printk("nand_read_oob_buf: fail return %x \n", len);
1739 + ops->oobretlen += len;
1744 + offs = addr & pagemask;
1745 + len = min_t(size_t, datalen, pagesize - offs);
1746 + if (data && len > 0) {
1747 + memcpy(data, ra->buffers + offs, len); // we can not sure ops->buf wether is DMA-able.
1751 + ops->retlen += len;
1757 + nand_bbt_set(ra, addr >> ra->erase_shift, BBT_TAG_GOOD);
1758 + // address go further to next page, instead of increasing of length of write. This avoids some special cases wrong.
1759 + addr = (page+1) << ra->page_shift;
1765 +ramtd_nand_erase(struct mtd_info *mtd, struct erase_info *instr)
1767 + struct ra_nand_chip *ra = (struct ra_nand_chip *)mtd->priv;
1770 + ra_dbg("%s: start:%x, len:%x \n", __func__,
1771 + (unsigned int)instr->addr, (unsigned int)instr->len);
1773 + nand_get_device(ra, FL_ERASING);
1774 + ret = _nand_erase_nand((struct ra_nand_chip *)mtd->priv, instr);
1775 + nand_release_device(ra);
1781 +ramtd_nand_write(struct mtd_info *mtd, loff_t to, size_t len,
1782 + size_t *retlen, const uint8_t *buf)
1784 + struct ra_nand_chip *ra = mtd->priv;
1785 + struct mtd_oob_ops ops;
1788 + ra_dbg("%s: to 0x%x len=0x%x\n", __func__, to, len);
1790 + if ((to + len) > mtd->size)
1796 + nand_get_device(ra, FL_WRITING);
1798 + memset(&ops, 0, sizeof(ops));
1800 + ops.datbuf = (uint8_t *)buf;
1801 + ops.oobbuf = NULL;
1802 + ops.mode = MTD_OPS_AUTO_OOB;
1804 + ret = nand_do_write_ops(ra, to, &ops);
1806 + *retlen = ops.retlen;
1808 + nand_release_device(ra);
1814 +ramtd_nand_read(struct mtd_info *mtd, loff_t from, size_t len,
1815 + size_t *retlen, uint8_t *buf)
1818 + struct ra_nand_chip *ra = mtd->priv;
1820 + struct mtd_oob_ops ops;
1822 + ra_dbg("%s: mtd:%p from:%x, len:%x, buf:%p \n", __func__, mtd, (unsigned int)from, len, buf);
1824 + /* Do not allow reads past end of device */
1825 + if ((from + len) > mtd->size)
1830 + nand_get_device(ra, FL_READING);
1832 + memset(&ops, 0, sizeof(ops));
1835 + ops.oobbuf = NULL;
1836 + ops.mode = MTD_OPS_AUTO_OOB;
1838 + ret = nand_do_read_ops(ra, from, &ops);
1840 + *retlen = ops.retlen;
1842 + nand_release_device(ra);
1849 +ramtd_nand_readoob(struct mtd_info *mtd, loff_t from,
1850 + struct mtd_oob_ops *ops)
1852 + struct ra_nand_chip *ra = mtd->priv;
1855 + ra_dbg("%s: \n", __func__);
1857 + nand_get_device(ra, FL_READING);
1859 + ret = nand_do_read_ops(ra, from, ops);
1861 + nand_release_device(ra);
1867 +ramtd_nand_writeoob(struct mtd_info *mtd, loff_t to,
1868 + struct mtd_oob_ops *ops)
1870 + struct ra_nand_chip *ra = mtd->priv;
1873 + nand_get_device(ra, FL_READING);
1874 + ret = nand_do_write_ops(ra, to, ops);
1875 + nand_release_device(ra);
1881 +ramtd_nand_block_isbad(struct mtd_info *mtd, loff_t offs)
1883 + if (offs > mtd->size)
1886 + return nand_block_checkbad((struct ra_nand_chip *)mtd->priv, offs);
1890 +ramtd_nand_block_markbad(struct mtd_info *mtd, loff_t ofs)
1892 + struct ra_nand_chip *ra = mtd->priv;
1895 + ra_dbg("%s: \n", __func__);
1896 + nand_get_device(ra, FL_WRITING);
1897 + ret = nand_block_markbad(ra, ofs);
1898 + nand_release_device(ra);
1903 +// 1-bit error detection
1904 +static int one_bit_correction(char *ecc1, char *ecc2, int *bytes, int *bits)
1906 + // check if ecc and expected are all valid
1907 + char *p, nibble, crumb;
1908 + int i, xor, iecc1 = 0, iecc2 = 0;
1910 + printk("correction : %x %x %x\n", ecc1[0], ecc1[1], ecc1[2]);
1911 + printk("correction : %x %x %x\n", ecc2[0], ecc2[1], ecc2[2]);
1914 + for (i = 0; i < CONFIG_ECC_BYTES; i++)
1916 + nibble = *(p+i) & 0xf;
1917 + if ((nibble != 0x0) && (nibble != 0xf) && (nibble != 0x3) && (nibble != 0xc) &&
1918 + (nibble != 0x5) && (nibble != 0xa) && (nibble != 0x6) && (nibble != 0x9))
1920 + nibble = ((*(p+i)) >> 4) & 0xf;
1921 + if ((nibble != 0x0) && (nibble != 0xf) && (nibble != 0x3) && (nibble != 0xc) &&
1922 + (nibble != 0x5) && (nibble != 0xa) && (nibble != 0x6) && (nibble != 0x9))
1927 + for (i = 0; i < CONFIG_ECC_BYTES; i++)
1929 + nibble = *(p+i) & 0xf;
1930 + if ((nibble != 0x0) && (nibble != 0xf) && (nibble != 0x3) && (nibble != 0xc) &&
1931 + (nibble != 0x5) && (nibble != 0xa) && (nibble != 0x6) && (nibble != 0x9))
1933 + nibble = ((*(p+i)) >> 4) & 0xf;
1934 + if ((nibble != 0x0) && (nibble != 0xf) && (nibble != 0x3) && (nibble != 0xc) &&
1935 + (nibble != 0x5) && (nibble != 0xa) && (nibble != 0x6) && (nibble != 0x9))
1939 + memcpy(&iecc1, ecc1, 3);
1940 + memcpy(&iecc2, ecc2, 3);
1942 + xor = iecc1 ^ iecc2;
1943 + printk("xor = %x (%x %x)\n", xor, iecc1, iecc2);
1946 + for (i = 0; i < 9; i++)
1948 + crumb = (xor >> (2*i)) & 0x3;
1949 + if ((crumb == 0x0) || (crumb == 0x3))
1952 + *bytes += (1 << i);
1956 + for (i = 0; i < 3; i++)
1958 + crumb = (xor >> (18 + 2*i)) & 0x3;
1959 + if ((crumb == 0x0) || (crumb == 0x3))
1962 + *bits += (1 << i);
1970 +/************************************************************
1971 + * the init/exit section.
1974 +static struct nand_ecclayout ra_oob_layout = {
1975 + .eccbytes = CONFIG_ECC_BYTES,
1976 + .eccpos = {5, 6, 7},
1978 + {.offset = 0, .length = 4},
1979 + {.offset = 8, .length = 8},
1980 + {.offset = 0, .length = 0}
1982 +#define RA_CHIP_OOB_AVAIL (4+8)
1983 + .oobavail = RA_CHIP_OOB_AVAIL,
1984 + // 5th byte is bad-block flag.
1988 +mtk_nand_probe(struct platform_device *pdev)
1990 + struct mtd_part_parser_data ppdata;
1991 + struct ra_nand_chip *ra;
1992 + int alloc_size, bbt_size, buffers_size, reg, err;
1993 + unsigned char chip_mode = 12;
1995 +/* if(ra_check_flash_type()!=BOOT_FROM_NAND) {
1999 + //FIXME: config 512 or 2048-byte page according to HWCONF
2000 +#if defined (CONFIG_RALINK_RT6855A)
2001 + reg = ra_inl(RALINK_SYSCTL_BASE+0x8c);
2002 + chip_mode = ((reg>>28) & 0x3)|(((reg>>22) & 0x3)<<2);
2003 + if (chip_mode == 1) {
2004 + printk("! nand 2048\n");
2005 + ra_or(NFC_CONF1, 1);
2006 + is_nand_page_2048 = 1;
2010 + printk("! nand 512\n");
2011 + ra_and(NFC_CONF1, ~1);
2012 + is_nand_page_2048 = 0;
2015 +#elif (defined (CONFIG_RALINK_MT7620) || defined (CONFIG_RALINK_RT6855))
2016 + ra_outl(RALINK_SYSCTL_BASE+0x60, ra_inl(RALINK_SYSCTL_BASE+0x60) & ~(0x3<<18));
2017 + reg = ra_inl(RALINK_SYSCTL_BASE+0x10);
2018 + chip_mode = (reg & 0x0F);
2019 + if((chip_mode==1)||(chip_mode==11)) {
2020 + ra_or(NFC_CONF1, 1);
2021 + is_nand_page_2048 = 1;
2022 + nand_addrlen = ((chip_mode!=11) ? 4 : 5);
2023 + printk("!!! nand page size = 2048, addr len=%d\n", nand_addrlen);
2026 + ra_and(NFC_CONF1, ~1);
2027 + is_nand_page_2048 = 0;
2028 + nand_addrlen = ((chip_mode!=10) ? 3 : 4);
2029 + printk("!!! nand page size = 512, addr len=%d\n", nand_addrlen);
2032 + is_nand_page_2048 = 0;
2034 + printk("!!! nand page size = 512, addr len=%d\n", nand_addrlen);
2037 +#if defined (CONFIG_RALINK_RT6855A) || defined (CONFIG_RALINK_MT7620) || defined (CONFIG_RALINK_RT6855)
2038 + //config ECC location
2039 + ra_and(NFC_CONF1, 0xfff000ff);
2040 + ra_or(NFC_CONF1, ((CONFIG_ECC_OFFSET + 2) << 16) +
2041 + ((CONFIG_ECC_OFFSET + 1) << 12) +
2042 + (CONFIG_ECC_OFFSET << 8));
2045 +#define ALIGNE_16(a) (((unsigned long)(a)+15) & ~15)
2046 + buffers_size = ALIGNE_16((1<<CONFIG_PAGE_SIZE_BIT) + (1<<CONFIG_OOBSIZE_PER_PAGE_BIT)); //ra->buffers
2047 + bbt_size = BBTTAG_BITS * (1<<(CONFIG_CHIP_SIZE_BIT - (CONFIG_PAGE_SIZE_BIT + CONFIG_NUMPAGE_PER_BLOCK_BIT))) / 8; //ra->bbt
2048 + bbt_size = ALIGNE_16(bbt_size);
2050 + alloc_size = buffers_size + bbt_size;
2051 + alloc_size += buffers_size; //for ra->readback_buffers
2052 + alloc_size += sizeof(*ra);
2053 + alloc_size += sizeof(*ranfc_mtd);
2055 + //make sure gpio-0 is input
2056 + ra_outl(RALINK_PIO_BASE+0x24, ra_inl(RALINK_PIO_BASE+0x24) & ~0x01);
2058 + ra = (struct ra_nand_chip *)kzalloc(alloc_size, GFP_KERNEL | GFP_DMA);
2060 + printk("%s: mem alloc fail \n", __func__);
2063 + memset(ra, 0, alloc_size);
2066 + ra->buffers = (char *)((char *)ra + sizeof(*ra));
2067 + ra->readback_buffers = ra->buffers + buffers_size;
2068 + ra->bbt = ra->readback_buffers + buffers_size;
2069 + ranfc_mtd = (struct mtd_info *)(ra->bbt + bbt_size);
2072 + ra->numchips = CONFIG_NUMCHIPS;
2073 + ra->chip_shift = CONFIG_CHIP_SIZE_BIT;
2074 + ra->page_shift = CONFIG_PAGE_SIZE_BIT;
2075 + ra->oob_shift = CONFIG_OOBSIZE_PER_PAGE_BIT;
2076 + ra->erase_shift = (CONFIG_PAGE_SIZE_BIT + CONFIG_NUMPAGE_PER_BLOCK_BIT);
2077 + ra->badblockpos = CONFIG_BAD_BLOCK_POS;
2078 + ra_oob_layout.eccpos[0] = CONFIG_ECC_OFFSET;
2079 + ra_oob_layout.eccpos[1] = CONFIG_ECC_OFFSET + 1;
2080 + ra_oob_layout.eccpos[2] = CONFIG_ECC_OFFSET + 2;
2081 + ra->oob = &ra_oob_layout;
2082 + ra->buffers_page = -1;
2084 +#if defined (WORKAROUND_RX_BUF_OV)
2085 + if (ranfc_verify) {
2086 + ra->sandbox_page = nand_bbt_find_sandbox(ra);
2089 + ra_outl(NFC_CTRL, ra_inl(NFC_CTRL) | 0x01); //set wp to high
2092 + ranfc_mtd->type = MTD_NANDFLASH;
2093 + ranfc_mtd->flags = MTD_CAP_NANDFLASH;
2094 + ranfc_mtd->size = CONFIG_NUMCHIPS * CFG_CHIPSIZE;
2095 + ranfc_mtd->erasesize = CFG_BLOCKSIZE;
2096 + ranfc_mtd->writesize = CFG_PAGESIZE;
2097 + ranfc_mtd->oobsize = CFG_PAGE_OOBSIZE;
2098 + ranfc_mtd->oobavail = RA_CHIP_OOB_AVAIL;
2099 + ranfc_mtd->name = "ra_nfc";
2100 + //ranfc_mtd->index
2101 + ranfc_mtd->ecclayout = &ra_oob_layout;
2102 + //ranfc_mtd->numberaseregions
2103 + //ranfc_mtd->eraseregions
2104 + //ranfc_mtd->bansize
2105 + ranfc_mtd->_erase = ramtd_nand_erase;
2106 + //ranfc_mtd->point
2107 + //ranfc_mtd->unpoint
2108 + ranfc_mtd->_read = ramtd_nand_read;
2109 + ranfc_mtd->_write = ramtd_nand_write;
2110 + ranfc_mtd->_read_oob = ramtd_nand_readoob;
2111 + ranfc_mtd->_write_oob = ramtd_nand_writeoob;
2112 + //ranfc_mtd->get_fact_prot_info; ranfc_mtd->read_fact_prot_reg;
2113 + //ranfc_mtd->get_user_prot_info; ranfc_mtd->read_user_prot_reg;
2114 + //ranfc_mtd->write_user_prot_reg; ranfc_mtd->lock_user_prot_reg;
2115 + //ranfc_mtd->writev; ranfc_mtd->sync; ranfc_mtd->lock; ranfc_mtd->unlock; ranfc_mtd->suspend; ranfc_mtd->resume;
2116 + ranfc_mtd->_block_isbad = ramtd_nand_block_isbad;
2117 + ranfc_mtd->_block_markbad = ramtd_nand_block_markbad;
2118 + //ranfc_mtd->reboot_notifier
2119 + //ranfc_mtd->ecc_stats;
2122 + //ranfc_mtd->get_device; ranfc_mtd->put_device
2123 + ranfc_mtd->priv = ra;
2125 + ranfc_mtd->owner = THIS_MODULE;
2126 + ra->controller = &ra->hwcontrol;
2127 + mutex_init(ra->controller);
2129 + printk("%s: alloc %x, at %p , btt(%p, %x), ranfc_mtd:%p\n",
2130 + __func__ , alloc_size, ra, ra->bbt, bbt_size, ranfc_mtd);
2132 + ppdata.of_node = pdev->dev.of_node;
2133 + err = mtd_device_parse_register(ranfc_mtd, mtk_probe_types,
2134 + &ppdata, NULL, 0);
2140 +mtk_nand_remove(struct platform_device *pdev)
2142 + struct ra_nand_chip *ra;
2145 + ra = (struct ra_nand_chip *)ranfc_mtd->priv;
2147 + /* Deregister partitions */
2148 + //del_mtd_partitions(ranfc_mtd);
2154 +static const struct of_device_id mtk_nand_match[] = {
2155 + { .compatible = "mtk,mt7620-nand" },
2158 +MODULE_DEVICE_TABLE(of, mtk_nand_match);
2160 +static struct platform_driver mtk_nand_driver = {
2161 + .probe = mtk_nand_probe,
2162 + .remove = mtk_nand_remove,
2164 + .name = "mt7620_nand",
2165 + .owner = THIS_MODULE,
2166 + .of_match_table = mtk_nand_match,
2170 +module_platform_driver(mtk_nand_driver);
2173 +MODULE_LICENSE("GPL");
2175 +++ b/drivers/mtd/maps/ralink_nand.h
2177 +#ifndef RT2880_NAND_H
2178 +#define RT2880_NAND_H
2180 +#include <linux/mtd/mtd.h>
2182 +//#include "gdma.h"
2184 +#define RALINK_SYSCTL_BASE 0xB0000000
2185 +#define RALINK_PIO_BASE 0xB0000600
2186 +#define RALINK_NAND_CTRL_BASE 0xB0000810
2187 +#define CONFIG_RALINK_MT7620
2189 +#define SKIP_BAD_BLOCK
2190 +//#define RANDOM_GEN_BAD_BLOCK
2192 +#define ra_inl(addr) (*(volatile unsigned int *)(addr))
2193 +#define ra_outl(addr, value) (*(volatile unsigned int *)(addr) = (value))
2194 +#define ra_aor(addr, a_mask, o_value) ra_outl(addr, (ra_inl(addr) & (a_mask)) | (o_value))
2195 +#define ra_and(addr, a_mask) ra_aor(addr, a_mask, 0)
2196 +#define ra_or(addr, o_value) ra_aor(addr, -1, o_value)
2199 +#define CONFIG_NUMCHIPS 1
2200 +#define CONFIG_NOT_SUPPORT_WP //rt3052 has no WP signal for chip.
2201 +//#define CONFIG_NOT_SUPPORT_RB
2203 +extern int is_nand_page_2048;
2204 +extern const unsigned int nand_size_map[2][3];
2207 +// chip geometry: SAMSUNG small size 32MB.
2208 +#define CONFIG_CHIP_SIZE_BIT (nand_size_map[is_nand_page_2048][nand_addrlen-3]) //! (1<<NAND_SIZE_BYTE) MB
2209 +//#define CONFIG_CHIP_SIZE_BIT (is_nand_page_2048? 29 : 25) //! (1<<NAND_SIZE_BYTE) MB
2210 +#define CONFIG_PAGE_SIZE_BIT (is_nand_page_2048? 11 : 9) //! (1<<PAGE_SIZE) MB
2211 +//#define CONFIG_SUBPAGE_BIT 1 //! these bits will be compensate by command cycle
2212 +#define CONFIG_NUMPAGE_PER_BLOCK_BIT (is_nand_page_2048? 6 : 5) //! order of number of pages a block.
2213 +#define CONFIG_OOBSIZE_PER_PAGE_BIT (is_nand_page_2048? 6 : 4) //! byte number of oob a page.
2214 +#define CONFIG_BAD_BLOCK_POS (is_nand_page_2048? 0 : 4) //! offset of byte to denote bad block.
2215 +#define CONFIG_ECC_BYTES 3 //! ecc has 3 bytes
2216 +#define CONFIG_ECC_OFFSET (is_nand_page_2048? 6 : 5) //! ecc starts from offset 5.
2218 +//this section should not be modified.
2219 +//#define CFG_COLUMN_ADDR_MASK ((1 << (CONFIG_PAGE_SIZE_BIT - CONFIG_SUBPAGE_BIT)) - 1)
2220 +//#define CFG_COLUMN_ADDR_CYCLE (((CONFIG_PAGE_SIZE_BIT - CONFIG_SUBPAGE_BIT) + 7)/8)
2221 +//#define CFG_ROW_ADDR_CYCLE ((CONFIG_CHIP_SIZE_BIT - CONFIG_PAGE_SIZE_BIT + 7)/8)
2222 +//#define CFG_ADDR_CYCLE (CFG_COLUMN_ADDR_CYCLE + CFG_ROW_ADDR_CYCLE)
2224 +#define CFG_COLUMN_ADDR_CYCLE (is_nand_page_2048? 2 : 1)
2225 +#define CFG_ROW_ADDR_CYCLE (nand_addrlen - CFG_COLUMN_ADDR_CYCLE)
2226 +#define CFG_ADDR_CYCLE (CFG_COLUMN_ADDR_CYCLE + CFG_ROW_ADDR_CYCLE)
2228 +#define CFG_CHIPSIZE (1 << ((CONFIG_CHIP_SIZE_BIT>=32)? 31 : CONFIG_CHIP_SIZE_BIT))
2229 +//#define CFG_CHIPSIZE (1 << CONFIG_CHIP_SIZE_BIT)
2230 +#define CFG_PAGESIZE (1 << CONFIG_PAGE_SIZE_BIT)
2231 +#define CFG_BLOCKSIZE (CFG_PAGESIZE << CONFIG_NUMPAGE_PER_BLOCK_BIT)
2232 +#define CFG_NUMPAGE (1 << (CONFIG_CHIP_SIZE_BIT - CONFIG_PAGE_SIZE_BIT))
2233 +#define CFG_NUMBLOCK (CFG_NUMPAGE >> CONFIG_NUMPAGE_PER_BLOCK_BIT)
2234 +#define CFG_BLOCK_OOBSIZE (1 << (CONFIG_OOBSIZE_PER_PAGE_BIT + CONFIG_NUMPAGE_PER_BLOCK_BIT))
2235 +#define CFG_PAGE_OOBSIZE (1 << CONFIG_OOBSIZE_PER_PAGE_BIT)
2237 +#define NAND_BLOCK_ALIGN(addr) ((addr) & (CFG_BLOCKSIZE-1))
2238 +#define NAND_PAGE_ALIGN(addr) ((addr) & (CFG_PAGESIZE-1))
2241 +#define NFC_BASE RALINK_NAND_CTRL_BASE
2242 +#define NFC_CTRL (NFC_BASE + 0x0)
2243 +#define NFC_CONF (NFC_BASE + 0x4)
2244 +#define NFC_CMD1 (NFC_BASE + 0x8)
2245 +#define NFC_CMD2 (NFC_BASE + 0xc)
2246 +#define NFC_CMD3 (NFC_BASE + 0x10)
2247 +#define NFC_ADDR (NFC_BASE + 0x14)
2248 +#define NFC_DATA (NFC_BASE + 0x18)
2249 +#if defined (CONFIG_RALINK_RT6855) || defined (CONFIG_RALINK_RT6855A) || \
2250 + defined (CONFIG_RALINK_MT7620) || defined (CONFIG_RALINK_MT7621)
2251 +#define NFC_ECC (NFC_BASE + 0x30)
2253 +#define NFC_ECC (NFC_BASE + 0x1c)
2255 +#define NFC_STATUS (NFC_BASE + 0x20)
2256 +#define NFC_INT_EN (NFC_BASE + 0x24)
2257 +#define NFC_INT_ST (NFC_BASE + 0x28)
2258 +#if defined (CONFIG_RALINK_RT6855) || defined (CONFIG_RALINK_RT6855A) || \
2259 + defined (CONFIG_RALINK_MT7620) || defined (CONFIG_RALINK_MT7621)
2260 +#define NFC_CONF1 (NFC_BASE + 0x2c)
2261 +#define NFC_ECC_P1 (NFC_BASE + 0x30)
2262 +#define NFC_ECC_P2 (NFC_BASE + 0x34)
2263 +#define NFC_ECC_P3 (NFC_BASE + 0x38)
2264 +#define NFC_ECC_P4 (NFC_BASE + 0x3c)
2265 +#define NFC_ECC_ERR1 (NFC_BASE + 0x40)
2266 +#define NFC_ECC_ERR2 (NFC_BASE + 0x44)
2267 +#define NFC_ECC_ERR3 (NFC_BASE + 0x48)
2268 +#define NFC_ECC_ERR4 (NFC_BASE + 0x4c)
2269 +#define NFC_ADDR2 (NFC_BASE + 0x50)
2273 + INT_ST_ND_DONE = 1<<0,
2274 + INT_ST_TX_BUF_RDY = 1<<1,
2275 + INT_ST_RX_BUF_RDY = 1<<2,
2276 + INT_ST_ECC_ERR = 1<<3,
2277 + INT_ST_TX_TRAS_ERR = 1<<4,
2278 + INT_ST_RX_TRAS_ERR = 1<<5,
2279 + INT_ST_TX_KICK_ERR = 1<<6,
2280 + INT_ST_RX_KICK_ERR = 1<<7
2284 +//#define WORKAROUND_RX_BUF_OV 1
2287 +/*************************************************************
2288 + * stolen from nand.h
2289 + *************************************************************/
2292 + * Standard NAND flash commands
2294 +#define NAND_CMD_READ0 0
2295 +#define NAND_CMD_READ1 1
2296 +#define NAND_CMD_RNDOUT 5
2297 +#define NAND_CMD_PAGEPROG 0x10
2298 +#define NAND_CMD_READOOB 0x50
2299 +#define NAND_CMD_ERASE1 0x60
2300 +#define NAND_CMD_STATUS 0x70
2301 +#define NAND_CMD_STATUS_MULTI 0x71
2302 +#define NAND_CMD_SEQIN 0x80
2303 +#define NAND_CMD_RNDIN 0x85
2304 +#define NAND_CMD_READID 0x90
2305 +#define NAND_CMD_ERASE2 0xd0
2306 +#define NAND_CMD_RESET 0xff
2308 +/* Extended commands for large page devices */
2309 +#define NAND_CMD_READSTART 0x30
2310 +#define NAND_CMD_RNDOUTSTART 0xE0
2311 +#define NAND_CMD_CACHEDPROG 0x15
2313 +/* Extended commands for AG-AND device */
2315 + * Note: the command for NAND_CMD_DEPLETE1 is really 0x00 but
2316 + * there is no way to distinguish that from NAND_CMD_READ0
2317 + * until the remaining sequence of commands has been completed
2318 + * so add a high order bit and mask it off in the command.
2320 +#define NAND_CMD_DEPLETE1 0x100
2321 +#define NAND_CMD_DEPLETE2 0x38
2322 +#define NAND_CMD_STATUS_MULTI 0x71
2323 +#define NAND_CMD_STATUS_ERROR 0x72
2324 +/* multi-bank error status (banks 0-3) */
2325 +#define NAND_CMD_STATUS_ERROR0 0x73
2326 +#define NAND_CMD_STATUS_ERROR1 0x74
2327 +#define NAND_CMD_STATUS_ERROR2 0x75
2328 +#define NAND_CMD_STATUS_ERROR3 0x76
2329 +#define NAND_CMD_STATUS_RESET 0x7f
2330 +#define NAND_CMD_STATUS_CLEAR 0xff
2332 +#define NAND_CMD_NONE -1
2335 +#define NAND_STATUS_FAIL 0x01
2336 +#define NAND_STATUS_FAIL_N1 0x02
2337 +#define NAND_STATUS_TRUE_READY 0x20
2338 +#define NAND_STATUS_READY 0x40
2339 +#define NAND_STATUS_WP 0x80
2351 +/*************************************************************/
2355 +typedef enum _ra_flags {
2357 + FLAG_ECC_EN = (1<<0),
2358 + FLAG_USE_GDMA = (1<<1),
2359 + FLAG_VERIFY = (1<<2),
2363 +#define BBTTAG_BITS 2
2364 +#define BBTTAG_BITS_MASK ((1<<BBTTAG_BITS) -1)
2366 + BBT_TAG_UNKNOWN = 0, //2'b01
2367 + BBT_TAG_GOOD = 3, //2'b11
2368 + BBT_TAG_BAD = 2, //2'b10
2369 + BBT_TAG_RES = 1, //2'b01
2372 +struct ra_nand_chip {
2379 +#if !defined (__UBOOT__)
2380 + struct mutex hwcontrol;
2381 + struct mutex *controller;
2383 + struct nand_ecclayout *oob;
2385 + unsigned int buffers_page;
2386 + char *buffers; //[CFG_PAGESIZE + CFG_PAGE_OOBSIZE];
2387 + char *readback_buffers;
2388 + unsigned char *bbt;
2389 +#if defined (WORKAROUND_RX_BUF_OV)
2390 + unsigned int sandbox_page; // steal a page (block) for read ECC verification
2398 +int nand_dma_sync(void);
2399 +void release_dma_buf(void);
2400 +int set_gdma_ch(unsigned long dst,
2401 + unsigned long src, unsigned int len, int burst_size,
2402 + int soft_mode, int src_req_type, int dst_req_type,
2403 + int src_burst_mode, int dst_burst_mode);