1 From fc006d0622ab8c43086b2c9018c03012db332033 Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Sun, 27 Jul 2014 11:15:12 +0100
4 Subject: [PATCH 50/57] SPI: ralink: add Ralink SoC spi driver
6 Add the driver needed to make SPI work on Ralink SoC.
8 Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
9 Acked-by: John Crispin <blogic@openwrt.org>
11 drivers/spi/Kconfig | 6 +
12 drivers/spi/Makefile | 1 +
13 drivers/spi/spi-rt2880.c | 432 ++++++++++++++++++++++++++++++++++++++++++++++
14 3 files changed, 439 insertions(+)
15 create mode 100644 drivers/spi/spi-rt2880.c
17 diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
18 index 581ee2a..009f8f3 100644
19 --- a/drivers/spi/Kconfig
20 +++ b/drivers/spi/Kconfig
21 @@ -381,6 +381,12 @@ config SPI_RSPI
23 SPI driver for Renesas RSPI and QSPI blocks.
26 + tristate "Ralink RT288x SPI Controller"
29 + This selects a driver for the Ralink RT288x/RT305x SPI Controller.
32 tristate "Samsung S3C24XX series SPI"
33 depends on ARCH_S3C24XX
34 diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
35 index 95af48d..1f647e5 100644
36 --- a/drivers/spi/Makefile
37 +++ b/drivers/spi/Makefile
38 @@ -60,6 +60,7 @@ spi-pxa2xx-platform-$(CONFIG_SPI_PXA2XX_DMA) += spi-pxa2xx-dma.o
39 obj-$(CONFIG_SPI_PXA2XX) += spi-pxa2xx-platform.o
40 obj-$(CONFIG_SPI_PXA2XX_PCI) += spi-pxa2xx-pci.o
41 obj-$(CONFIG_SPI_RSPI) += spi-rspi.o
42 +obj-$(CONFIG_SPI_RT2880) += spi-rt2880.o
43 obj-$(CONFIG_SPI_S3C24XX) += spi-s3c24xx-hw.o
44 spi-s3c24xx-hw-y := spi-s3c24xx.o
45 spi-s3c24xx-hw-$(CONFIG_SPI_S3C24XX_FIQ) += spi-s3c24xx-fiq.o
46 diff --git a/drivers/spi/spi-rt2880.c b/drivers/spi/spi-rt2880.c
48 index 0000000..ac9de67
50 +++ b/drivers/spi/spi-rt2880.c
53 + * spi-rt2880.c -- Ralink RT288x/RT305x SPI controller driver
55 + * Copyright (C) 2011 Sergiy <piratfm@gmail.com>
56 + * Copyright (C) 2011-2013 Gabor Juhos <juhosg@openwrt.org>
58 + * Some parts are based on spi-orion.c:
59 + * Author: Shadi Ammouri <shadi@marvell.com>
60 + * Copyright (C) 2007-2008 Marvell Ltd.
62 + * This program is free software; you can redistribute it and/or modify
63 + * it under the terms of the GNU General Public License version 2 as
64 + * published by the Free Software Foundation.
67 +#include <linux/init.h>
68 +#include <linux/module.h>
69 +#include <linux/clk.h>
70 +#include <linux/err.h>
71 +#include <linux/delay.h>
72 +#include <linux/io.h>
73 +#include <linux/reset.h>
74 +#include <linux/spi/spi.h>
75 +#include <linux/platform_device.h>
77 +#define DRIVER_NAME "spi-rt2880"
78 +/* only one slave is supported*/
79 +#define RALINK_NUM_CHIPSELECTS 1
81 +#define RALINK_SPI_WAIT_MAX_LOOP 2000
83 +#define RAMIPS_SPI_STAT 0x00
84 +#define RAMIPS_SPI_CFG 0x10
85 +#define RAMIPS_SPI_CTL 0x14
86 +#define RAMIPS_SPI_DATA 0x20
87 +#define RAMIPS_SPI_FIFO_STAT 0x38
89 +/* SPISTAT register bit field */
90 +#define SPISTAT_BUSY BIT(0)
92 +/* SPICFG register bit field */
93 +#define SPICFG_LSBFIRST 0
94 +#define SPICFG_MSBFIRST BIT(8)
95 +#define SPICFG_SPICLKPOL BIT(6)
96 +#define SPICFG_RXCLKEDGE_FALLING BIT(5)
97 +#define SPICFG_TXCLKEDGE_FALLING BIT(4)
98 +#define SPICFG_SPICLK_PRESCALE_MASK 0x7
99 +#define SPICFG_SPICLK_DIV2 0
100 +#define SPICFG_SPICLK_DIV4 1
101 +#define SPICFG_SPICLK_DIV8 2
102 +#define SPICFG_SPICLK_DIV16 3
103 +#define SPICFG_SPICLK_DIV32 4
104 +#define SPICFG_SPICLK_DIV64 5
105 +#define SPICFG_SPICLK_DIV128 6
106 +#define SPICFG_SPICLK_DISABLE 7
108 +/* SPICTL register bit field */
109 +#define SPICTL_HIZSDO BIT(3)
110 +#define SPICTL_STARTWR BIT(2)
111 +#define SPICTL_STARTRD BIT(1)
112 +#define SPICTL_SPIENA BIT(0)
114 +/* SPIFIFOSTAT register bit field */
115 +#define SPIFIFOSTAT_TXFULL BIT(17)
118 + struct spi_master *master;
119 + void __iomem *base;
120 + unsigned int sys_freq;
121 + unsigned int speed;
126 +static inline struct rt2880_spi *spidev_to_rt2880_spi(struct spi_device *spi)
128 + return spi_master_get_devdata(spi->master);
131 +static inline u32 rt2880_spi_read(struct rt2880_spi *rs, u32 reg)
133 + return ioread32(rs->base + reg);
136 +static inline void rt2880_spi_write(struct rt2880_spi *rs, u32 reg, u32 val)
138 + iowrite32(val, rs->base + reg);
141 +static inline void rt2880_spi_setbits(struct rt2880_spi *rs, u32 reg, u32 mask)
143 + void __iomem *addr = rs->base + reg;
144 + unsigned long flags;
147 + spin_lock_irqsave(&rs->lock, flags);
148 + val = ioread32(addr);
150 + iowrite32(val, addr);
151 + spin_unlock_irqrestore(&rs->lock, flags);
154 +static inline void rt2880_spi_clrbits(struct rt2880_spi *rs, u32 reg, u32 mask)
156 + void __iomem *addr = rs->base + reg;
157 + unsigned long flags;
160 + spin_lock_irqsave(&rs->lock, flags);
161 + val = ioread32(addr);
163 + iowrite32(val, addr);
164 + spin_unlock_irqrestore(&rs->lock, flags);
167 +static int rt2880_spi_baudrate_set(struct spi_device *spi, unsigned int speed)
169 + struct rt2880_spi *rs = spidev_to_rt2880_spi(spi);
174 + dev_dbg(&spi->dev, "speed:%u\n", speed);
177 + * the supported rates are: 2, 4, 8, ... 128
178 + * round up as we look for equal or less speed
180 + rate = DIV_ROUND_UP(rs->sys_freq, speed);
181 + dev_dbg(&spi->dev, "rate-1:%u\n", rate);
182 + rate = roundup_pow_of_two(rate);
183 + dev_dbg(&spi->dev, "rate-2:%u\n", rate);
185 + /* check if requested speed is too small */
192 + /* Convert the rate to SPI clock divisor value. */
193 + prescale = ilog2(rate / 2);
194 + dev_dbg(&spi->dev, "prescale:%u\n", prescale);
196 + reg = rt2880_spi_read(rs, RAMIPS_SPI_CFG);
197 + reg = ((reg & ~SPICFG_SPICLK_PRESCALE_MASK) | prescale);
198 + rt2880_spi_write(rs, RAMIPS_SPI_CFG, reg);
204 + * called only when no transfer is active on the bus
207 +rt2880_spi_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
209 + struct rt2880_spi *rs = spidev_to_rt2880_spi(spi);
210 + unsigned int speed = spi->max_speed_hz;
213 + if ((t != NULL) && t->speed_hz)
214 + speed = t->speed_hz;
216 + if (rs->speed != speed) {
217 + dev_dbg(&spi->dev, "speed_hz:%u\n", speed);
218 + rc = rt2880_spi_baudrate_set(spi, speed);
226 +static void rt2880_spi_set_cs(struct rt2880_spi *rs, int enable)
229 + rt2880_spi_clrbits(rs, RAMIPS_SPI_CTL, SPICTL_SPIENA);
231 + rt2880_spi_setbits(rs, RAMIPS_SPI_CTL, SPICTL_SPIENA);
234 +static inline int rt2880_spi_wait_till_ready(struct rt2880_spi *rs)
238 + for (i = 0; i < RALINK_SPI_WAIT_MAX_LOOP; i++) {
241 + status = rt2880_spi_read(rs, RAMIPS_SPI_STAT);
242 + if ((status & SPISTAT_BUSY) == 0)
253 +rt2880_spi_write_read(struct spi_device *spi, struct spi_transfer *xfer)
255 + struct rt2880_spi *rs = spidev_to_rt2880_spi(spi);
256 + unsigned count = 0;
257 + u8 *rx = xfer->rx_buf;
258 + const u8 *tx = xfer->tx_buf;
261 + dev_dbg(&spi->dev, "read (%d): %s %s\n", xfer->len,
262 + (tx != NULL) ? "tx" : " ",
263 + (rx != NULL) ? "rx" : " ");
266 + for (count = 0; count < xfer->len; count++) {
267 + rt2880_spi_write(rs, RAMIPS_SPI_DATA, tx[count]);
268 + rt2880_spi_setbits(rs, RAMIPS_SPI_CTL, SPICTL_STARTWR);
269 + err = rt2880_spi_wait_till_ready(rs);
271 + dev_err(&spi->dev, "TX failed, err=%d\n", err);
278 + for (count = 0; count < xfer->len; count++) {
279 + rt2880_spi_setbits(rs, RAMIPS_SPI_CTL, SPICTL_STARTRD);
280 + err = rt2880_spi_wait_till_ready(rs);
282 + dev_err(&spi->dev, "RX failed, err=%d\n", err);
285 + rx[count] = (u8) rt2880_spi_read(rs, RAMIPS_SPI_DATA);
293 +static int rt2880_spi_transfer_one_message(struct spi_master *master,
294 + struct spi_message *m)
296 + struct rt2880_spi *rs = spi_master_get_devdata(master);
297 + struct spi_device *spi = m->spi;
298 + struct spi_transfer *t = NULL;
299 + int par_override = 0;
303 + /* Load defaults */
304 + status = rt2880_spi_setup_transfer(spi, NULL);
308 + list_for_each_entry(t, &m->transfers, transfer_list) {
309 + if (t->tx_buf == NULL && t->rx_buf == NULL && t->len) {
311 + "message rejected: invalid transfer data buffers\n");
316 + if (t->speed_hz && t->speed_hz < (rs->sys_freq / 128)) {
318 + "message rejected: device min speed (%d Hz) exceeds required transfer speed (%d Hz)\n",
319 + (rs->sys_freq / 128), t->speed_hz);
324 + if (par_override || t->speed_hz || t->bits_per_word) {
326 + status = rt2880_spi_setup_transfer(spi, t);
329 + if (!t->speed_hz && !t->bits_per_word)
334 + rt2880_spi_set_cs(rs, 1);
339 + m->actual_length += rt2880_spi_write_read(spi, t);
341 + if (t->delay_usecs)
342 + udelay(t->delay_usecs);
344 + if (t->cs_change) {
345 + rt2880_spi_set_cs(rs, 0);
352 + rt2880_spi_set_cs(rs, 0);
354 + m->status = status;
355 + spi_finalize_current_message(master);
360 +static int rt2880_spi_setup(struct spi_device *spi)
362 + struct rt2880_spi *rs = spidev_to_rt2880_spi(spi);
364 + if ((spi->max_speed_hz == 0) ||
365 + (spi->max_speed_hz > (rs->sys_freq / 2)))
366 + spi->max_speed_hz = (rs->sys_freq / 2);
368 + if (spi->max_speed_hz < (rs->sys_freq / 128)) {
369 + dev_err(&spi->dev, "setup: requested speed is too low %d Hz\n",
370 + spi->max_speed_hz);
375 + * baudrate & width will be set rt2880_spi_setup_transfer
380 +static void rt2880_spi_reset(struct rt2880_spi *rs)
382 + rt2880_spi_write(rs, RAMIPS_SPI_CFG,
383 + SPICFG_MSBFIRST | SPICFG_TXCLKEDGE_FALLING |
384 + SPICFG_SPICLK_DIV16 | SPICFG_SPICLKPOL);
385 + rt2880_spi_write(rs, RAMIPS_SPI_CTL, SPICTL_HIZSDO | SPICTL_SPIENA);
388 +static int rt2880_spi_probe(struct platform_device *pdev)
390 + struct spi_master *master;
391 + struct rt2880_spi *rs;
392 + unsigned long flags;
393 + void __iomem *base;
394 + struct resource *r;
398 + r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
399 + base = devm_ioremap_resource(&pdev->dev, r);
401 + return PTR_ERR(base);
403 + clk = devm_clk_get(&pdev->dev, NULL);
405 + dev_err(&pdev->dev, "unable to get SYS clock, err=%d\n",
407 + return PTR_ERR(clk);
410 + status = clk_prepare_enable(clk);
414 + master = spi_alloc_master(&pdev->dev, sizeof(*rs));
415 + if (master == NULL) {
416 + dev_dbg(&pdev->dev, "master allocation failed\n");
420 + /* we support only mode 0, and no options */
421 + master->mode_bits = 0;
423 + master->setup = rt2880_spi_setup;
424 + master->transfer_one_message = rt2880_spi_transfer_one_message;
425 + master->num_chipselect = RALINK_NUM_CHIPSELECTS;
426 + master->bits_per_word_mask = SPI_BPW_MASK(8);
427 + master->dev.of_node = pdev->dev.of_node;
429 + dev_set_drvdata(&pdev->dev, master);
431 + rs = spi_master_get_devdata(master);
434 + rs->master = master;
435 + rs->sys_freq = clk_get_rate(rs->clk);
436 + dev_dbg(&pdev->dev, "sys_freq: %u\n", rs->sys_freq);
437 + spin_lock_irqsave(&rs->lock, flags);
439 + device_reset(&pdev->dev);
441 + rt2880_spi_reset(rs);
443 + return spi_register_master(master);
446 +static int rt2880_spi_remove(struct platform_device *pdev)
448 + struct spi_master *master;
449 + struct rt2880_spi *rs;
451 + master = dev_get_drvdata(&pdev->dev);
452 + rs = spi_master_get_devdata(master);
454 + clk_disable(rs->clk);
455 + spi_unregister_master(master);
460 +MODULE_ALIAS("platform:" DRIVER_NAME);
462 +static const struct of_device_id rt2880_spi_match[] = {
463 + { .compatible = "ralink,rt2880-spi" },
466 +MODULE_DEVICE_TABLE(of, rt2880_spi_match);
468 +static struct platform_driver rt2880_spi_driver = {
470 + .name = DRIVER_NAME,
471 + .owner = THIS_MODULE,
472 + .of_match_table = rt2880_spi_match,
474 + .probe = rt2880_spi_probe,
475 + .remove = rt2880_spi_remove,
478 +module_platform_driver(rt2880_spi_driver);
480 +MODULE_DESCRIPTION("Ralink SPI driver");
481 +MODULE_AUTHOR("Sergiy <piratfm@gmail.com>");
482 +MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
483 +MODULE_LICENSE("GPL");