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[openwrt/openwrt.git] / target / linux / ramips / patches-3.14 / 0053-mmc-MIPS-ralink-add-sdhci-for-mt7620a-SoC.patch
1 From f954801c6f48fc291c39ca8a888dbdfda1021415 Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Thu, 13 Nov 2014 19:08:40 +0100
4 Subject: [PATCH] mmc: MIPS: ralink: add sdhci for mt7620a SoC
5
6 Signed-off-by: John Crispin <blogic@openwrt.org>
7 ---
8 drivers/mmc/host/Kconfig | 2 +
9 drivers/mmc/host/Makefile | 1 +
10 drivers/mmc/host/mtk-mmc/Kconfig | 16 +
11 drivers/mmc/host/mtk-mmc/Makefile | 42 +
12 drivers/mmc/host/mtk-mmc/board.h | 137 ++
13 drivers/mmc/host/mtk-mmc/dbg.c | 347 ++++
14 drivers/mmc/host/mtk-mmc/dbg.h | 153 ++
15 drivers/mmc/host/mtk-mmc/mt6575_sd.h | 1001 +++++++++++
16 drivers/mmc/host/mtk-mmc/sd.c | 3041 ++++++++++++++++++++++++++++++++++
17 9 files changed, 4740 insertions(+)
18 create mode 100644 drivers/mmc/host/mtk-mmc/Kconfig
19 create mode 100644 drivers/mmc/host/mtk-mmc/Makefile
20 create mode 100644 drivers/mmc/host/mtk-mmc/board.h
21 create mode 100644 drivers/mmc/host/mtk-mmc/dbg.c
22 create mode 100644 drivers/mmc/host/mtk-mmc/dbg.h
23 create mode 100644 drivers/mmc/host/mtk-mmc/mt6575_sd.h
24 create mode 100644 drivers/mmc/host/mtk-mmc/sd.c
25
26 diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
27 index ef6bf59..73362eb 100644
28 --- a/drivers/mmc/host/Kconfig
29 +++ b/drivers/mmc/host/Kconfig
30 @@ -657,3 +657,5 @@ config MMC_REALTEK_PCI
31 help
32 Say Y here to include driver code to support SD/MMC card interface
33 of Realtek PCI-E card reader
34 +
35 +source "drivers/mmc/host/mtk-mmc/Kconfig"
36 diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile
37 index c800bed..b68b10e 100644
38 --- a/drivers/mmc/host/Makefile
39 +++ b/drivers/mmc/host/Makefile
40 @@ -2,6 +2,7 @@
41 # Makefile for MMC/SD host controller drivers
42 #
43
44 +obj-$(CONFIG_MTK_MMC) += mtk-mmc/
45 obj-$(CONFIG_MMC_ARMMMCI) += mmci.o
46 obj-$(CONFIG_MMC_PXA) += pxamci.o
47 obj-$(CONFIG_MMC_MXC) += mxcmmc.o
48 diff --git a/drivers/mmc/host/mtk-mmc/Kconfig b/drivers/mmc/host/mtk-mmc/Kconfig
49 new file mode 100644
50 index 0000000..a58b0f3
51 --- /dev/null
52 +++ b/drivers/mmc/host/mtk-mmc/Kconfig
53 @@ -0,0 +1,16 @@
54 +config MTK_MMC
55 + tristate "MTK SD/MMC"
56 + depends on !MTD_NAND_RALINK
57 +
58 +config MTK_AEE_KDUMP
59 + bool "MTK AEE KDUMP"
60 + depends on MTK_MMC
61 +
62 +config MTK_MMC_CD_POLL
63 + bool "Card Detect with Polling"
64 + depends on MTK_MMC
65 +
66 +config MTK_MMC_EMMC_8BIT
67 + bool "eMMC 8-bit support"
68 + depends on MTK_MMC && RALINK_MT7628
69 +
70 diff --git a/drivers/mmc/host/mtk-mmc/Makefile b/drivers/mmc/host/mtk-mmc/Makefile
71 new file mode 100644
72 index 0000000..caead0b
73 --- /dev/null
74 +++ b/drivers/mmc/host/mtk-mmc/Makefile
75 @@ -0,0 +1,42 @@
76 +# Copyright Statement:
77 +#
78 +# This software/firmware and related documentation ("MediaTek Software") are
79 +# protected under relevant copyright laws. The information contained herein
80 +# is confidential and proprietary to MediaTek Inc. and/or its licensors.
81 +# Without the prior written permission of MediaTek inc. and/or its licensors,
82 +# any reproduction, modification, use or disclosure of MediaTek Software,
83 +# and information contained herein, in whole or in part, shall be strictly prohibited.
84 +#
85 +# MediaTek Inc. (C) 2010. All rights reserved.
86 +#
87 +# BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
88 +# THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
89 +# RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
90 +# AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
91 +# EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
92 +# MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
93 +# NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
94 +# SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
95 +# SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
96 +# THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
97 +# THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
98 +# CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
99 +# SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
100 +# STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
101 +# CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
102 +# AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
103 +# OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
104 +# MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
105 +#
106 +# The following software/firmware and/or related documentation ("MediaTek Software")
107 +# have been modified by MediaTek Inc. All revisions are subject to any receiver's
108 +# applicable license agreements with MediaTek Inc.
109 +
110 +obj-$(CONFIG_MTK_MMC) += mtk_sd.o
111 +mtk_sd-objs := sd.o dbg.o
112 +ifeq ($(CONFIG_MTK_AEE_KDUMP),y)
113 +EXTRA_CFLAGS += -DMT6575_SD_DEBUG
114 +endif
115 +
116 +clean:
117 + @rm -f *.o modules.order .*.cmd
118 diff --git a/drivers/mmc/host/mtk-mmc/board.h b/drivers/mmc/host/mtk-mmc/board.h
119 new file mode 100644
120 index 0000000..33bfc7b
121 --- /dev/null
122 +++ b/drivers/mmc/host/mtk-mmc/board.h
123 @@ -0,0 +1,137 @@
124 +/* Copyright Statement:
125 + *
126 + * This software/firmware and related documentation ("MediaTek Software") are
127 + * protected under relevant copyright laws. The information contained herein
128 + * is confidential and proprietary to MediaTek Inc. and/or its licensors.
129 + * Without the prior written permission of MediaTek inc. and/or its licensors,
130 + * any reproduction, modification, use or disclosure of MediaTek Software,
131 + * and information contained herein, in whole or in part, shall be strictly prohibited.
132 + */
133 +/* MediaTek Inc. (C) 2010. All rights reserved.
134 + *
135 + * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
136 + * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
137 + * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
138 + * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
139 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
140 + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
141 + * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
142 + * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
143 + * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
144 + * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
145 + * THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
146 + * CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
147 + * SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
148 + * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
149 + * CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
150 + * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
151 + * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
152 + * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
153 + *
154 + * The following software/firmware and/or related documentation ("MediaTek Software")
155 + * have been modified by MediaTek Inc. All revisions are subject to any receiver's
156 + * applicable license agreements with MediaTek Inc.
157 + */
158 +
159 +#ifndef __ARCH_ARM_MACH_BOARD_H
160 +#define __ARCH_ARM_MACH_BOARD_H
161 +
162 +#include <generated/autoconf.h>
163 +#include <linux/pm.h>
164 +/* --- chhung */
165 +// #include <mach/mt6575.h>
166 +// #include <board-custom.h>
167 +/* end of chhung */
168 +
169 +typedef void (*sdio_irq_handler_t)(void*); /* external irq handler */
170 +typedef void (*pm_callback_t)(pm_message_t state, void *data);
171 +
172 +#define MSDC_CD_PIN_EN (1 << 0) /* card detection pin is wired */
173 +#define MSDC_WP_PIN_EN (1 << 1) /* write protection pin is wired */
174 +#define MSDC_RST_PIN_EN (1 << 2) /* emmc reset pin is wired */
175 +#define MSDC_SDIO_IRQ (1 << 3) /* use internal sdio irq (bus) */
176 +#define MSDC_EXT_SDIO_IRQ (1 << 4) /* use external sdio irq */
177 +#define MSDC_REMOVABLE (1 << 5) /* removable slot */
178 +#define MSDC_SYS_SUSPEND (1 << 6) /* suspended by system */
179 +#define MSDC_HIGHSPEED (1 << 7) /* high-speed mode support */
180 +#define MSDC_UHS1 (1 << 8) /* uhs-1 mode support */
181 +#define MSDC_DDR (1 << 9) /* ddr mode support */
182 +
183 +
184 +#define MSDC_SMPL_RISING (0)
185 +#define MSDC_SMPL_FALLING (1)
186 +
187 +#define MSDC_CMD_PIN (0)
188 +#define MSDC_DAT_PIN (1)
189 +#define MSDC_CD_PIN (2)
190 +#define MSDC_WP_PIN (3)
191 +#define MSDC_RST_PIN (4)
192 +
193 +enum {
194 + MSDC_CLKSRC_48MHZ = 0,
195 +// MSDC_CLKSRC_26MHZ = 0,
196 +// MSDC_CLKSRC_197MHZ = 1,
197 +// MSDC_CLKSRC_208MHZ = 2
198 +};
199 +
200 +struct msdc_hw {
201 + unsigned char clk_src; /* host clock source */
202 + unsigned char cmd_edge; /* command latch edge */
203 + unsigned char data_edge; /* data latch edge */
204 + unsigned char clk_drv; /* clock pad driving */
205 + unsigned char cmd_drv; /* command pad driving */
206 + unsigned char dat_drv; /* data pad driving */
207 + unsigned long flags; /* hardware capability flags */
208 + unsigned long data_pins; /* data pins */
209 + unsigned long data_offset; /* data address offset */
210 +
211 + /* config gpio pull mode */
212 + void (*config_gpio_pin)(int type, int pull);
213 +
214 + /* external power control for card */
215 + void (*ext_power_on)(void);
216 + void (*ext_power_off)(void);
217 +
218 + /* external sdio irq operations */
219 + void (*request_sdio_eirq)(sdio_irq_handler_t sdio_irq_handler, void *data);
220 + void (*enable_sdio_eirq)(void);
221 + void (*disable_sdio_eirq)(void);
222 +
223 + /* external cd irq operations */
224 + void (*request_cd_eirq)(sdio_irq_handler_t cd_irq_handler, void *data);
225 + void (*enable_cd_eirq)(void);
226 + void (*disable_cd_eirq)(void);
227 + int (*get_cd_status)(void);
228 +
229 + /* power management callback for external module */
230 + void (*register_pm)(pm_callback_t pm_cb, void *data);
231 +};
232 +
233 +extern struct msdc_hw msdc0_hw;
234 +extern struct msdc_hw msdc1_hw;
235 +extern struct msdc_hw msdc2_hw;
236 +extern struct msdc_hw msdc3_hw;
237 +
238 +/*GPS driver*/
239 +#define GPS_FLAG_FORCE_OFF 0x0001
240 +struct mt3326_gps_hardware {
241 + int (*ext_power_on)(int);
242 + int (*ext_power_off)(int);
243 +};
244 +extern struct mt3326_gps_hardware mt3326_gps_hw;
245 +
246 +/* NAND driver */
247 +struct mt6575_nand_host_hw {
248 + unsigned int nfi_bus_width; /* NFI_BUS_WIDTH */
249 + unsigned int nfi_access_timing; /* NFI_ACCESS_TIMING */
250 + unsigned int nfi_cs_num; /* NFI_CS_NUM */
251 + unsigned int nand_sec_size; /* NAND_SECTOR_SIZE */
252 + unsigned int nand_sec_shift; /* NAND_SECTOR_SHIFT */
253 + unsigned int nand_ecc_size;
254 + unsigned int nand_ecc_bytes;
255 + unsigned int nand_ecc_mode;
256 +};
257 +extern struct mt6575_nand_host_hw mt6575_nand_hw;
258 +
259 +#endif /* __ARCH_ARM_MACH_BOARD_H */
260 +
261 diff --git a/drivers/mmc/host/mtk-mmc/dbg.c b/drivers/mmc/host/mtk-mmc/dbg.c
262 new file mode 100644
263 index 0000000..4dc115b
264 --- /dev/null
265 +++ b/drivers/mmc/host/mtk-mmc/dbg.c
266 @@ -0,0 +1,347 @@
267 +/* Copyright Statement:
268 + *
269 + * This software/firmware and related documentation ("MediaTek Software") are
270 + * protected under relevant copyright laws. The information contained herein
271 + * is confidential and proprietary to MediaTek Inc. and/or its licensors.
272 + * Without the prior written permission of MediaTek inc. and/or its licensors,
273 + * any reproduction, modification, use or disclosure of MediaTek Software,
274 + * and information contained herein, in whole or in part, shall be strictly prohibited.
275 + *
276 + * MediaTek Inc. (C) 2010. All rights reserved.
277 + *
278 + * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
279 + * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
280 + * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
281 + * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
282 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
283 + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
284 + * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
285 + * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
286 + * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
287 + * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
288 + * THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
289 + * CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
290 + * SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
291 + * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
292 + * CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
293 + * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
294 + * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
295 + * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
296 + *
297 + * The following software/firmware and/or related documentation ("MediaTek Software")
298 + * have been modified by MediaTek Inc. All revisions are subject to any receiver's
299 + * applicable license agreements with MediaTek Inc.
300 + */
301 +
302 +#include <linux/version.h>
303 +#include <linux/kernel.h>
304 +#include <linux/sched.h>
305 +#include <linux/kthread.h>
306 +#include <linux/delay.h>
307 +#include <linux/module.h>
308 +#include <linux/init.h>
309 +#include <linux/proc_fs.h>
310 +#include <linux/string.h>
311 +#include <linux/uaccess.h>
312 +// #include <mach/mt6575_gpt.h> /* --- by chhung */
313 +#include "dbg.h"
314 +#include "mt6575_sd.h"
315 +#include <linux/seq_file.h>
316 +
317 +static char cmd_buf[256];
318 +
319 +/* for debug zone */
320 +unsigned int sd_debug_zone[4]={
321 + 0,
322 + 0,
323 + 0,
324 + 0
325 +};
326 +
327 +/* mode select */
328 +u32 dma_size[4]={
329 + 512,
330 + 512,
331 + 512,
332 + 512
333 +};
334 +msdc_mode drv_mode[4]={
335 + MODE_SIZE_DEP, /* using DMA or not depend on the size */
336 + MODE_SIZE_DEP,
337 + MODE_SIZE_DEP,
338 + MODE_SIZE_DEP
339 +};
340 +
341 +#if defined (MT6575_SD_DEBUG)
342 +/* for driver profile */
343 +#define TICKS_ONE_MS (13000)
344 +u32 gpt_enable = 0;
345 +u32 sdio_pro_enable = 0; /* make sure gpt is enabled */
346 +u32 sdio_pro_time = 0; /* no more than 30s */
347 +struct sdio_profile sdio_perfomance = {0};
348 +
349 +#if 0 /* --- chhung */
350 +void msdc_init_gpt(void)
351 +{
352 + GPT_CONFIG config;
353 +
354 + config.num = GPT6;
355 + config.mode = GPT_FREE_RUN;
356 + config.clkSrc = GPT_CLK_SRC_SYS;
357 + config.clkDiv = GPT_CLK_DIV_1; /* 13MHz GPT6 */
358 +
359 + if (GPT_Config(config) == FALSE )
360 + return;
361 +
362 + GPT_Start(GPT6);
363 +}
364 +#endif /* end of --- */
365 +
366 +u32 msdc_time_calc(u32 old_L32, u32 old_H32, u32 new_L32, u32 new_H32)
367 +{
368 + u32 ret = 0;
369 +
370 + if (new_H32 == old_H32) {
371 + ret = new_L32 - old_L32;
372 + } else if(new_H32 == (old_H32 + 1)) {
373 + if (new_L32 > old_L32) {
374 + printk("msdc old_L<0x%x> new_L<0x%x>\n", old_L32, new_L32);
375 + }
376 + ret = (0xffffffff - old_L32);
377 + ret += new_L32;
378 + } else {
379 + printk("msdc old_H<0x%x> new_H<0x%x>\n", old_H32, new_H32);
380 + }
381 +
382 + return ret;
383 +}
384 +
385 +void msdc_sdio_profile(struct sdio_profile* result)
386 +{
387 + struct cmd_profile* cmd;
388 + u32 i;
389 +
390 + printk("sdio === performance dump ===\n");
391 + printk("sdio === total execute tick<%d> time<%dms> Tx<%dB> Rx<%dB>\n",
392 + result->total_tc, result->total_tc / TICKS_ONE_MS,
393 + result->total_tx_bytes, result->total_rx_bytes);
394 +
395 + /* CMD52 Dump */
396 + cmd = &result->cmd52_rx;
397 + printk("sdio === CMD52 Rx <%d>times tick<%d> Max<%d> Min<%d> Aver<%d>\n", cmd->count, cmd->tot_tc,
398 + cmd->max_tc, cmd->min_tc, cmd->tot_tc/cmd->count);
399 + cmd = &result->cmd52_tx;
400 + printk("sdio === CMD52 Tx <%d>times tick<%d> Max<%d> Min<%d> Aver<%d>\n", cmd->count, cmd->tot_tc,
401 + cmd->max_tc, cmd->min_tc, cmd->tot_tc/cmd->count);
402 +
403 + /* CMD53 Rx bytes + block mode */
404 + for (i=0; i<512; i++) {
405 + cmd = &result->cmd53_rx_byte[i];
406 + if (cmd->count) {
407 + printk("sdio<%6d><%3dB>_Rx_<%9d><%9d><%6d><%6d>_<%9dB><%2dM>\n", cmd->count, i, cmd->tot_tc,
408 + cmd->max_tc, cmd->min_tc, cmd->tot_tc/cmd->count,
409 + cmd->tot_bytes, (cmd->tot_bytes/10)*13 / (cmd->tot_tc/10));
410 + }
411 + }
412 + for (i=0; i<100; i++) {
413 + cmd = &result->cmd53_rx_blk[i];
414 + if (cmd->count) {
415 + printk("sdio<%6d><%3d>B_Rx_<%9d><%9d><%6d><%6d>_<%9dB><%2dM>\n", cmd->count, i, cmd->tot_tc,
416 + cmd->max_tc, cmd->min_tc, cmd->tot_tc/cmd->count,
417 + cmd->tot_bytes, (cmd->tot_bytes/10)*13 / (cmd->tot_tc/10));
418 + }
419 + }
420 +
421 + /* CMD53 Tx bytes + block mode */
422 + for (i=0; i<512; i++) {
423 + cmd = &result->cmd53_tx_byte[i];
424 + if (cmd->count) {
425 + printk("sdio<%6d><%3dB>_Tx_<%9d><%9d><%6d><%6d>_<%9dB><%2dM>\n", cmd->count, i, cmd->tot_tc,
426 + cmd->max_tc, cmd->min_tc, cmd->tot_tc/cmd->count,
427 + cmd->tot_bytes, (cmd->tot_bytes/10)*13 / (cmd->tot_tc/10));
428 + }
429 + }
430 + for (i=0; i<100; i++) {
431 + cmd = &result->cmd53_tx_blk[i];
432 + if (cmd->count) {
433 + printk("sdio<%6d><%3d>B_Tx_<%9d><%9d><%6d><%6d>_<%9dB><%2dM>\n", cmd->count, i, cmd->tot_tc,
434 + cmd->max_tc, cmd->min_tc, cmd->tot_tc/cmd->count,
435 + cmd->tot_bytes, (cmd->tot_bytes/10)*13 / (cmd->tot_tc/10));
436 + }
437 + }
438 +
439 + printk("sdio === performance dump done ===\n");
440 +}
441 +
442 +//========= sdio command table ===========
443 +void msdc_performance(u32 opcode, u32 sizes, u32 bRx, u32 ticks)
444 +{
445 + struct sdio_profile* result = &sdio_perfomance;
446 + struct cmd_profile* cmd;
447 + u32 block;
448 +
449 + if (sdio_pro_enable == 0) {
450 + return;
451 + }
452 +
453 + if (opcode == 52) {
454 + cmd = bRx ? &result->cmd52_rx : &result->cmd52_tx;
455 + } else if (opcode == 53) {
456 + if (sizes < 512) {
457 + cmd = bRx ? &result->cmd53_rx_byte[sizes] : &result->cmd53_tx_byte[sizes];
458 + } else {
459 + block = sizes / 512;
460 + if (block >= 99) {
461 + printk("cmd53 error blocks\n");
462 + while(1);
463 + }
464 + cmd = bRx ? &result->cmd53_rx_blk[block] : &result->cmd53_tx_blk[block];
465 + }
466 + } else {
467 + return;
468 + }
469 +
470 + /* update the members */
471 + if (ticks > cmd->max_tc){
472 + cmd->max_tc = ticks;
473 + }
474 + if (cmd->min_tc == 0 || ticks < cmd->min_tc) {
475 + cmd->min_tc = ticks;
476 + }
477 + cmd->tot_tc += ticks;
478 + cmd->tot_bytes += sizes;
479 + cmd->count ++;
480 +
481 + if (bRx) {
482 + result->total_rx_bytes += sizes;
483 + } else {
484 + result->total_tx_bytes += sizes;
485 + }
486 + result->total_tc += ticks;
487 +
488 + /* dump when total_tc > 30s */
489 + if (result->total_tc >= sdio_pro_time * TICKS_ONE_MS * 1000) {
490 + msdc_sdio_profile(result);
491 + memset(result, 0 , sizeof(struct sdio_profile));
492 + }
493 +}
494 +
495 +//========== driver proc interface ===========
496 +static int msdc_debug_proc_read(struct seq_file *s, void *p)
497 +{
498 + seq_printf(s, "\n=========================================\n");
499 + seq_printf(s, "Index<0> + Id + Zone\n");
500 + seq_printf(s, "-> PWR<9> WRN<8> | FIO<7> OPS<6> FUN<5> CFG<4> | INT<3> RSP<2> CMD<1> DMA<0>\n");
501 + seq_printf(s, "-> echo 0 3 0x3ff >msdc_bebug -> host[3] debug zone set to 0x3ff\n");
502 + seq_printf(s, "-> MSDC[0] Zone: 0x%.8x\n", sd_debug_zone[0]);
503 + seq_printf(s, "-> MSDC[1] Zone: 0x%.8x\n", sd_debug_zone[1]);
504 + seq_printf(s, "-> MSDC[2] Zone: 0x%.8x\n", sd_debug_zone[2]);
505 + seq_printf(s, "-> MSDC[3] Zone: 0x%.8x\n", sd_debug_zone[3]);
506 +
507 + seq_printf(s, "Index<1> + ID:4|Mode:4 + DMA_SIZE\n");
508 + seq_printf(s, "-> 0)PIO 1)DMA 2)SIZE\n");
509 + seq_printf(s, "-> echo 1 22 0x200 >msdc_bebug -> host[2] size mode, dma when >= 512\n");
510 + seq_printf(s, "-> MSDC[0] mode<%d> size<%d>\n", drv_mode[0], dma_size[0]);
511 + seq_printf(s, "-> MSDC[1] mode<%d> size<%d>\n", drv_mode[1], dma_size[1]);
512 + seq_printf(s, "-> MSDC[2] mode<%d> size<%d>\n", drv_mode[2], dma_size[2]);
513 + seq_printf(s, "-> MSDC[3] mode<%d> size<%d>\n", drv_mode[3], dma_size[3]);
514 +
515 + seq_printf(s, "Index<3> + SDIO_PROFILE + TIME\n");
516 + seq_printf(s, "-> echo 3 1 0x1E >msdc_bebug -> enable sdio_profile, 30s\n");
517 + seq_printf(s, "-> SDIO_PROFILE<%d> TIME<%ds>\n", sdio_pro_enable, sdio_pro_time);
518 + seq_printf(s, "=========================================\n\n");
519 +
520 + return 0;
521 +}
522 +
523 +static ssize_t msdc_debug_proc_write(struct file *file,
524 + const char __user *buf, size_t count, loff_t *data)
525 +{
526 + int ret;
527 +
528 + int cmd, p1, p2;
529 + int id, zone;
530 + int mode, size;
531 +
532 + if (count == 0)return -1;
533 + if(count > 255)count = 255;
534 +
535 + ret = copy_from_user(cmd_buf, buf, count);
536 + if (ret < 0)return -1;
537 +
538 + cmd_buf[count] = '\0';
539 + printk("msdc Write %s\n", cmd_buf);
540 +
541 + sscanf(cmd_buf, "%x %x %x", &cmd, &p1, &p2);
542 +
543 + if(cmd == SD_TOOL_ZONE) {
544 + id = p1; zone = p2; zone &= 0x3ff;
545 + printk("msdc host_id<%d> zone<0x%.8x>\n", id, zone);
546 + if(id >=0 && id<=3){
547 + sd_debug_zone[id] = zone;
548 + }
549 + else if(id == 4){
550 + sd_debug_zone[0] = sd_debug_zone[1] = zone;
551 + sd_debug_zone[2] = sd_debug_zone[3] = zone;
552 + }
553 + else{
554 + printk("msdc host_id error when set debug zone\n");
555 + }
556 + } else if (cmd == SD_TOOL_DMA_SIZE) {
557 + id = p1>>4; mode = (p1&0xf); size = p2;
558 + if(id >=0 && id<=3){
559 + drv_mode[id] = mode;
560 + dma_size[id] = p2;
561 + }
562 + else if(id == 4){
563 + drv_mode[0] = drv_mode[1] = mode;
564 + drv_mode[2] = drv_mode[3] = mode;
565 + dma_size[0] = dma_size[1] = p2;
566 + dma_size[2] = dma_size[3] = p2;
567 + }
568 + else{
569 + printk("msdc host_id error when select mode\n");
570 + }
571 + } else if (cmd == SD_TOOL_SDIO_PROFILE) {
572 + if (p1 == 1) { /* enable profile */
573 + if (gpt_enable == 0) {
574 + // msdc_init_gpt(); /* --- by chhung */
575 + gpt_enable = 1;
576 + }
577 + sdio_pro_enable = 1;
578 + if (p2 == 0) p2 = 1; if (p2 >= 30) p2 = 30;
579 + sdio_pro_time = p2 ;
580 + } else if (p1 == 0) {
581 + /* todo */
582 + sdio_pro_enable = 0;
583 + }
584 + }
585 +
586 + return count;
587 +}
588 +
589 +static int msdc_debug_show(struct inode *inode, struct file *file)
590 +{
591 + return single_open(file, msdc_debug_proc_read, NULL);
592 +}
593 +
594 +static const struct file_operations msdc_debug_fops = {
595 + .owner = THIS_MODULE,
596 + .open = msdc_debug_show,
597 + .read = seq_read,
598 + .write = msdc_debug_proc_write,
599 + .llseek = seq_lseek,
600 + .release = single_release,
601 +};
602 +
603 +int msdc_debug_proc_init(void)
604 +{
605 + struct proc_dir_entry *de = proc_create("msdc_debug", 0667, NULL, &msdc_debug_fops);
606 +
607 + if (!de || IS_ERR(de))
608 + printk("!! Create MSDC debug PROC fail !!\n");
609 +
610 + return 0 ;
611 +}
612 +EXPORT_SYMBOL_GPL(msdc_debug_proc_init);
613 +#endif
614 diff --git a/drivers/mmc/host/mtk-mmc/dbg.h b/drivers/mmc/host/mtk-mmc/dbg.h
615 new file mode 100644
616 index 0000000..6b141e6
617 --- /dev/null
618 +++ b/drivers/mmc/host/mtk-mmc/dbg.h
619 @@ -0,0 +1,153 @@
620 +/* Copyright Statement:
621 + *
622 + * This software/firmware and related documentation ("MediaTek Software") are
623 + * protected under relevant copyright laws. The information contained herein
624 + * is confidential and proprietary to MediaTek Inc. and/or its licensors.
625 + * Without the prior written permission of MediaTek inc. and/or its licensors,
626 + * any reproduction, modification, use or disclosure of MediaTek Software,
627 + * and information contained herein, in whole or in part, shall be strictly prohibited.
628 + *
629 + * MediaTek Inc. (C) 2010. All rights reserved.
630 + *
631 + * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
632 + * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
633 + * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
634 + * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
635 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
636 + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
637 + * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
638 + * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
639 + * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
640 + * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
641 + * THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
642 + * CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
643 + * SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
644 + * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
645 + * CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
646 + * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
647 + * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
648 + * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
649 + *
650 + * The following software/firmware and/or related documentation ("MediaTek Software")
651 + * have been modified by MediaTek Inc. All revisions are subject to any receiver's
652 + * applicable license agreements with MediaTek Inc.
653 + */
654 +#ifndef __MT_MSDC_DEUBG__
655 +#define __MT_MSDC_DEUBG__
656 +
657 +//==========================
658 +extern u32 sdio_pro_enable;
659 +/* for a type command, e.g. CMD53, 2 blocks */
660 +struct cmd_profile {
661 + u32 max_tc; /* Max tick count */
662 + u32 min_tc;
663 + u32 tot_tc; /* total tick count */
664 + u32 tot_bytes;
665 + u32 count; /* the counts of the command */
666 +};
667 +
668 +/* dump when total_tc and total_bytes */
669 +struct sdio_profile {
670 + u32 total_tc; /* total tick count of CMD52 and CMD53 */
671 + u32 total_tx_bytes; /* total bytes of CMD53 Tx */
672 + u32 total_rx_bytes; /* total bytes of CMD53 Rx */
673 +
674 + /*CMD52*/
675 + struct cmd_profile cmd52_tx;
676 + struct cmd_profile cmd52_rx;
677 +
678 + /*CMD53 in byte unit */
679 + struct cmd_profile cmd53_tx_byte[512];
680 + struct cmd_profile cmd53_rx_byte[512];
681 +
682 + /*CMD53 in block unit */
683 + struct cmd_profile cmd53_tx_blk[100];
684 + struct cmd_profile cmd53_rx_blk[100];
685 +};
686 +
687 +//==========================
688 +typedef enum {
689 + SD_TOOL_ZONE = 0,
690 + SD_TOOL_DMA_SIZE = 1,
691 + SD_TOOL_PM_ENABLE = 2,
692 + SD_TOOL_SDIO_PROFILE = 3,
693 +} msdc_dbg;
694 +
695 +typedef enum {
696 + MODE_PIO = 0,
697 + MODE_DMA = 1,
698 + MODE_SIZE_DEP = 2,
699 +} msdc_mode;
700 +extern msdc_mode drv_mode[4];
701 +extern u32 dma_size[4];
702 +
703 +/* Debug message event */
704 +#define DBG_EVT_NONE (0) /* No event */
705 +#define DBG_EVT_DMA (1 << 0) /* DMA related event */
706 +#define DBG_EVT_CMD (1 << 1) /* MSDC CMD related event */
707 +#define DBG_EVT_RSP (1 << 2) /* MSDC CMD RSP related event */
708 +#define DBG_EVT_INT (1 << 3) /* MSDC INT event */
709 +#define DBG_EVT_CFG (1 << 4) /* MSDC CFG event */
710 +#define DBG_EVT_FUC (1 << 5) /* Function event */
711 +#define DBG_EVT_OPS (1 << 6) /* Read/Write operation event */
712 +#define DBG_EVT_FIO (1 << 7) /* FIFO operation event */
713 +#define DBG_EVT_WRN (1 << 8) /* Warning event */
714 +#define DBG_EVT_PWR (1 << 9) /* Power event */
715 +#define DBG_EVT_ALL (0xffffffff)
716 +
717 +#define DBG_EVT_MASK (DBG_EVT_ALL)
718 +
719 +extern unsigned int sd_debug_zone[4];
720 +#define TAG "msdc"
721 +#if 0 /* +++ chhung */
722 +#define BUG_ON(x) \
723 +do { \
724 + if (x) { \
725 + printk("[BUG] %s LINE:%d FILE:%s\n", #x, __LINE__, __FILE__); \
726 + while(1); \
727 + } \
728 +}while(0)
729 +#endif /* end of +++ */
730 +
731 +#define N_MSG(evt, fmt, args...) \
732 +do { \
733 + if ((DBG_EVT_##evt) & sd_debug_zone[host->id]) { \
734 + printk(KERN_ERR TAG"%d -> "fmt" <- %s() : L<%d> PID<%s><0x%x>\n", \
735 + host->id, ##args , __FUNCTION__, __LINE__, current->comm, current->pid); \
736 + } \
737 +} while(0)
738 +
739 +#define ERR_MSG(fmt, args...) \
740 +do { \
741 + printk(KERN_ERR TAG"%d -> "fmt" <- %s() : L<%d> PID<%s><0x%x>\n", \
742 + host->id, ##args , __FUNCTION__, __LINE__, current->comm, current->pid); \
743 +} while(0);
744 +
745 +#if defined CONFIG_MTK_MMC_CD_POLL
746 +#define INIT_MSG(fmt, args...)
747 +#define IRQ_MSG(fmt, args...)
748 +#else
749 +#define INIT_MSG(fmt, args...) \
750 +do { \
751 + printk(KERN_ERR TAG"%d -> "fmt" <- %s() : L<%d> PID<%s><0x%x>\n", \
752 + host->id, ##args , __FUNCTION__, __LINE__, current->comm, current->pid); \
753 +} while(0);
754 +
755 +/* PID in ISR in not corrent */
756 +#define IRQ_MSG(fmt, args...) \
757 +do { \
758 + printk(KERN_ERR TAG"%d -> "fmt" <- %s() : L<%d>\n", \
759 + host->id, ##args , __FUNCTION__, __LINE__); \
760 +} while(0);
761 +#endif
762 +
763 +int msdc_debug_proc_init(void);
764 +
765 +#if 0 /* --- chhung */
766 +void msdc_init_gpt(void);
767 +extern void GPT_GetCounter64(UINT32 *cntL32, UINT32 *cntH32);
768 +#endif /* end of --- */
769 +u32 msdc_time_calc(u32 old_L32, u32 old_H32, u32 new_L32, u32 new_H32);
770 +void msdc_performance(u32 opcode, u32 sizes, u32 bRx, u32 ticks);
771 +
772 +#endif
773 diff --git a/drivers/mmc/host/mtk-mmc/mt6575_sd.h b/drivers/mmc/host/mtk-mmc/mt6575_sd.h
774 new file mode 100644
775 index 0000000..e90c4f1
776 --- /dev/null
777 +++ b/drivers/mmc/host/mtk-mmc/mt6575_sd.h
778 @@ -0,0 +1,1001 @@
779 +/* Copyright Statement:
780 + *
781 + * This software/firmware and related documentation ("MediaTek Software") are
782 + * protected under relevant copyright laws. The information contained herein
783 + * is confidential and proprietary to MediaTek Inc. and/or its licensors.
784 + * Without the prior written permission of MediaTek inc. and/or its licensors,
785 + * any reproduction, modification, use or disclosure of MediaTek Software,
786 + * and information contained herein, in whole or in part, shall be strictly prohibited.
787 + */
788 +/* MediaTek Inc. (C) 2010. All rights reserved.
789 + *
790 + * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
791 + * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
792 + * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
793 + * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
794 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
795 + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
796 + * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
797 + * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
798 + * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
799 + * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
800 + * THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
801 + * CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
802 + * SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
803 + * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
804 + * CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
805 + * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
806 + * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
807 + * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
808 + *
809 + * The following software/firmware and/or related documentation ("MediaTek Software")
810 + * have been modified by MediaTek Inc. All revisions are subject to any receiver's
811 + * applicable license agreements with MediaTek Inc.
812 + */
813 +
814 +#ifndef MT6575_SD_H
815 +#define MT6575_SD_H
816 +
817 +#include <linux/bitops.h>
818 +#include <linux/mmc/host.h>
819 +
820 +// #include <mach/mt6575_reg_base.h> /* --- by chhung */
821 +
822 +/*--------------------------------------------------------------------------*/
823 +/* Common Macro */
824 +/*--------------------------------------------------------------------------*/
825 +#define REG_ADDR(x) ((volatile u32*)(base + OFFSET_##x))
826 +
827 +/*--------------------------------------------------------------------------*/
828 +/* Common Definition */
829 +/*--------------------------------------------------------------------------*/
830 +#define MSDC_FIFO_SZ (128)
831 +#define MSDC_FIFO_THD (64) // (128)
832 +#define MSDC_NUM (4)
833 +
834 +#define MSDC_MS (0)
835 +#define MSDC_SDMMC (1)
836 +
837 +#define MSDC_MODE_UNKNOWN (0)
838 +#define MSDC_MODE_PIO (1)
839 +#define MSDC_MODE_DMA_BASIC (2)
840 +#define MSDC_MODE_DMA_DESC (3)
841 +#define MSDC_MODE_DMA_ENHANCED (4)
842 +#define MSDC_MODE_MMC_STREAM (5)
843 +
844 +#define MSDC_BUS_1BITS (0)
845 +#define MSDC_BUS_4BITS (1)
846 +#define MSDC_BUS_8BITS (2)
847 +
848 +#define MSDC_BRUST_8B (3)
849 +#define MSDC_BRUST_16B (4)
850 +#define MSDC_BRUST_32B (5)
851 +#define MSDC_BRUST_64B (6)
852 +
853 +#define MSDC_PIN_PULL_NONE (0)
854 +#define MSDC_PIN_PULL_DOWN (1)
855 +#define MSDC_PIN_PULL_UP (2)
856 +#define MSDC_PIN_KEEP (3)
857 +
858 +#define MSDC_MAX_SCLK (48000000) /* +/- by chhung */
859 +#define MSDC_MIN_SCLK (260000)
860 +
861 +#define MSDC_AUTOCMD12 (0x0001)
862 +#define MSDC_AUTOCMD23 (0x0002)
863 +#define MSDC_AUTOCMD19 (0x0003)
864 +
865 +#define MSDC_EMMC_BOOTMODE0 (0) /* Pull low CMD mode */
866 +#define MSDC_EMMC_BOOTMODE1 (1) /* Reset CMD mode */
867 +
868 +enum {
869 + RESP_NONE = 0,
870 + RESP_R1,
871 + RESP_R2,
872 + RESP_R3,
873 + RESP_R4,
874 + RESP_R5,
875 + RESP_R6,
876 + RESP_R7,
877 + RESP_R1B
878 +};
879 +
880 +/*--------------------------------------------------------------------------*/
881 +/* Register Offset */
882 +/*--------------------------------------------------------------------------*/
883 +#define OFFSET_MSDC_CFG (0x0)
884 +#define OFFSET_MSDC_IOCON (0x04)
885 +#define OFFSET_MSDC_PS (0x08)
886 +#define OFFSET_MSDC_INT (0x0c)
887 +#define OFFSET_MSDC_INTEN (0x10)
888 +#define OFFSET_MSDC_FIFOCS (0x14)
889 +#define OFFSET_MSDC_TXDATA (0x18)
890 +#define OFFSET_MSDC_RXDATA (0x1c)
891 +#define OFFSET_SDC_CFG (0x30)
892 +#define OFFSET_SDC_CMD (0x34)
893 +#define OFFSET_SDC_ARG (0x38)
894 +#define OFFSET_SDC_STS (0x3c)
895 +#define OFFSET_SDC_RESP0 (0x40)
896 +#define OFFSET_SDC_RESP1 (0x44)
897 +#define OFFSET_SDC_RESP2 (0x48)
898 +#define OFFSET_SDC_RESP3 (0x4c)
899 +#define OFFSET_SDC_BLK_NUM (0x50)
900 +#define OFFSET_SDC_CSTS (0x58)
901 +#define OFFSET_SDC_CSTS_EN (0x5c)
902 +#define OFFSET_SDC_DCRC_STS (0x60)
903 +#define OFFSET_EMMC_CFG0 (0x70)
904 +#define OFFSET_EMMC_CFG1 (0x74)
905 +#define OFFSET_EMMC_STS (0x78)
906 +#define OFFSET_EMMC_IOCON (0x7c)
907 +#define OFFSET_SDC_ACMD_RESP (0x80)
908 +#define OFFSET_SDC_ACMD19_TRG (0x84)
909 +#define OFFSET_SDC_ACMD19_STS (0x88)
910 +#define OFFSET_MSDC_DMA_SA (0x90)
911 +#define OFFSET_MSDC_DMA_CA (0x94)
912 +#define OFFSET_MSDC_DMA_CTRL (0x98)
913 +#define OFFSET_MSDC_DMA_CFG (0x9c)
914 +#define OFFSET_MSDC_DBG_SEL (0xa0)
915 +#define OFFSET_MSDC_DBG_OUT (0xa4)
916 +#define OFFSET_MSDC_PATCH_BIT (0xb0)
917 +#define OFFSET_MSDC_PATCH_BIT1 (0xb4)
918 +#define OFFSET_MSDC_PAD_CTL0 (0xe0)
919 +#define OFFSET_MSDC_PAD_CTL1 (0xe4)
920 +#define OFFSET_MSDC_PAD_CTL2 (0xe8)
921 +#define OFFSET_MSDC_PAD_TUNE (0xec)
922 +#define OFFSET_MSDC_DAT_RDDLY0 (0xf0)
923 +#define OFFSET_MSDC_DAT_RDDLY1 (0xf4)
924 +#define OFFSET_MSDC_HW_DBG (0xf8)
925 +#define OFFSET_MSDC_VERSION (0x100)
926 +#define OFFSET_MSDC_ECO_VER (0x104)
927 +
928 +/*--------------------------------------------------------------------------*/
929 +/* Register Address */
930 +/*--------------------------------------------------------------------------*/
931 +
932 +/* common register */
933 +#define MSDC_CFG REG_ADDR(MSDC_CFG)
934 +#define MSDC_IOCON REG_ADDR(MSDC_IOCON)
935 +#define MSDC_PS REG_ADDR(MSDC_PS)
936 +#define MSDC_INT REG_ADDR(MSDC_INT)
937 +#define MSDC_INTEN REG_ADDR(MSDC_INTEN)
938 +#define MSDC_FIFOCS REG_ADDR(MSDC_FIFOCS)
939 +#define MSDC_TXDATA REG_ADDR(MSDC_TXDATA)
940 +#define MSDC_RXDATA REG_ADDR(MSDC_RXDATA)
941 +#define MSDC_PATCH_BIT0 REG_ADDR(MSDC_PATCH_BIT)
942 +
943 +/* sdmmc register */
944 +#define SDC_CFG REG_ADDR(SDC_CFG)
945 +#define SDC_CMD REG_ADDR(SDC_CMD)
946 +#define SDC_ARG REG_ADDR(SDC_ARG)
947 +#define SDC_STS REG_ADDR(SDC_STS)
948 +#define SDC_RESP0 REG_ADDR(SDC_RESP0)
949 +#define SDC_RESP1 REG_ADDR(SDC_RESP1)
950 +#define SDC_RESP2 REG_ADDR(SDC_RESP2)
951 +#define SDC_RESP3 REG_ADDR(SDC_RESP3)
952 +#define SDC_BLK_NUM REG_ADDR(SDC_BLK_NUM)
953 +#define SDC_CSTS REG_ADDR(SDC_CSTS)
954 +#define SDC_CSTS_EN REG_ADDR(SDC_CSTS_EN)
955 +#define SDC_DCRC_STS REG_ADDR(SDC_DCRC_STS)
956 +
957 +/* emmc register*/
958 +#define EMMC_CFG0 REG_ADDR(EMMC_CFG0)
959 +#define EMMC_CFG1 REG_ADDR(EMMC_CFG1)
960 +#define EMMC_STS REG_ADDR(EMMC_STS)
961 +#define EMMC_IOCON REG_ADDR(EMMC_IOCON)
962 +
963 +/* auto command register */
964 +#define SDC_ACMD_RESP REG_ADDR(SDC_ACMD_RESP)
965 +#define SDC_ACMD19_TRG REG_ADDR(SDC_ACMD19_TRG)
966 +#define SDC_ACMD19_STS REG_ADDR(SDC_ACMD19_STS)
967 +
968 +/* dma register */
969 +#define MSDC_DMA_SA REG_ADDR(MSDC_DMA_SA)
970 +#define MSDC_DMA_CA REG_ADDR(MSDC_DMA_CA)
971 +#define MSDC_DMA_CTRL REG_ADDR(MSDC_DMA_CTRL)
972 +#define MSDC_DMA_CFG REG_ADDR(MSDC_DMA_CFG)
973 +
974 +/* pad ctrl register */
975 +#define MSDC_PAD_CTL0 REG_ADDR(MSDC_PAD_CTL0)
976 +#define MSDC_PAD_CTL1 REG_ADDR(MSDC_PAD_CTL1)
977 +#define MSDC_PAD_CTL2 REG_ADDR(MSDC_PAD_CTL2)
978 +
979 +/* data read delay */
980 +#define MSDC_DAT_RDDLY0 REG_ADDR(MSDC_DAT_RDDLY0)
981 +#define MSDC_DAT_RDDLY1 REG_ADDR(MSDC_DAT_RDDLY1)
982 +
983 +/* debug register */
984 +#define MSDC_DBG_SEL REG_ADDR(MSDC_DBG_SEL)
985 +#define MSDC_DBG_OUT REG_ADDR(MSDC_DBG_OUT)
986 +
987 +/* misc register */
988 +#define MSDC_PATCH_BIT REG_ADDR(MSDC_PATCH_BIT)
989 +#define MSDC_PATCH_BIT1 REG_ADDR(MSDC_PATCH_BIT1)
990 +#define MSDC_PAD_TUNE REG_ADDR(MSDC_PAD_TUNE)
991 +#define MSDC_HW_DBG REG_ADDR(MSDC_HW_DBG)
992 +#define MSDC_VERSION REG_ADDR(MSDC_VERSION)
993 +#define MSDC_ECO_VER REG_ADDR(MSDC_ECO_VER) /* ECO Version */
994 +
995 +/*--------------------------------------------------------------------------*/
996 +/* Register Mask */
997 +/*--------------------------------------------------------------------------*/
998 +
999 +/* MSDC_CFG mask */
1000 +#define MSDC_CFG_MODE (0x1 << 0) /* RW */
1001 +#define MSDC_CFG_CKPDN (0x1 << 1) /* RW */
1002 +#define MSDC_CFG_RST (0x1 << 2) /* RW */
1003 +#define MSDC_CFG_PIO (0x1 << 3) /* RW */
1004 +#define MSDC_CFG_CKDRVEN (0x1 << 4) /* RW */
1005 +#define MSDC_CFG_BV18SDT (0x1 << 5) /* RW */
1006 +#define MSDC_CFG_BV18PSS (0x1 << 6) /* R */
1007 +#define MSDC_CFG_CKSTB (0x1 << 7) /* R */
1008 +#define MSDC_CFG_CKDIV (0xff << 8) /* RW */
1009 +#define MSDC_CFG_CKMOD (0x3 << 16) /* RW */
1010 +
1011 +/* MSDC_IOCON mask */
1012 +#define MSDC_IOCON_SDR104CKS (0x1 << 0) /* RW */
1013 +#define MSDC_IOCON_RSPL (0x1 << 1) /* RW */
1014 +#define MSDC_IOCON_DSPL (0x1 << 2) /* RW */
1015 +#define MSDC_IOCON_DDLSEL (0x1 << 3) /* RW */
1016 +#define MSDC_IOCON_DDR50CKD (0x1 << 4) /* RW */
1017 +#define MSDC_IOCON_DSPLSEL (0x1 << 5) /* RW */
1018 +#define MSDC_IOCON_D0SPL (0x1 << 16) /* RW */
1019 +#define MSDC_IOCON_D1SPL (0x1 << 17) /* RW */
1020 +#define MSDC_IOCON_D2SPL (0x1 << 18) /* RW */
1021 +#define MSDC_IOCON_D3SPL (0x1 << 19) /* RW */
1022 +#define MSDC_IOCON_D4SPL (0x1 << 20) /* RW */
1023 +#define MSDC_IOCON_D5SPL (0x1 << 21) /* RW */
1024 +#define MSDC_IOCON_D6SPL (0x1 << 22) /* RW */
1025 +#define MSDC_IOCON_D7SPL (0x1 << 23) /* RW */
1026 +#define MSDC_IOCON_RISCSZ (0x3 << 24) /* RW */
1027 +
1028 +/* MSDC_PS mask */
1029 +#define MSDC_PS_CDEN (0x1 << 0) /* RW */
1030 +#define MSDC_PS_CDSTS (0x1 << 1) /* R */
1031 +#define MSDC_PS_CDDEBOUNCE (0xf << 12) /* RW */
1032 +#define MSDC_PS_DAT (0xff << 16) /* R */
1033 +#define MSDC_PS_CMD (0x1 << 24) /* R */
1034 +#define MSDC_PS_WP (0x1UL<< 31) /* R */
1035 +
1036 +/* MSDC_INT mask */
1037 +#define MSDC_INT_MMCIRQ (0x1 << 0) /* W1C */
1038 +#define MSDC_INT_CDSC (0x1 << 1) /* W1C */
1039 +#define MSDC_INT_ACMDRDY (0x1 << 3) /* W1C */
1040 +#define MSDC_INT_ACMDTMO (0x1 << 4) /* W1C */
1041 +#define MSDC_INT_ACMDCRCERR (0x1 << 5) /* W1C */
1042 +#define MSDC_INT_DMAQ_EMPTY (0x1 << 6) /* W1C */
1043 +#define MSDC_INT_SDIOIRQ (0x1 << 7) /* W1C */
1044 +#define MSDC_INT_CMDRDY (0x1 << 8) /* W1C */
1045 +#define MSDC_INT_CMDTMO (0x1 << 9) /* W1C */
1046 +#define MSDC_INT_RSPCRCERR (0x1 << 10) /* W1C */
1047 +#define MSDC_INT_CSTA (0x1 << 11) /* R */
1048 +#define MSDC_INT_XFER_COMPL (0x1 << 12) /* W1C */
1049 +#define MSDC_INT_DXFER_DONE (0x1 << 13) /* W1C */
1050 +#define MSDC_INT_DATTMO (0x1 << 14) /* W1C */
1051 +#define MSDC_INT_DATCRCERR (0x1 << 15) /* W1C */
1052 +#define MSDC_INT_ACMD19_DONE (0x1 << 16) /* W1C */
1053 +
1054 +/* MSDC_INTEN mask */
1055 +#define MSDC_INTEN_MMCIRQ (0x1 << 0) /* RW */
1056 +#define MSDC_INTEN_CDSC (0x1 << 1) /* RW */
1057 +#define MSDC_INTEN_ACMDRDY (0x1 << 3) /* RW */
1058 +#define MSDC_INTEN_ACMDTMO (0x1 << 4) /* RW */
1059 +#define MSDC_INTEN_ACMDCRCERR (0x1 << 5) /* RW */
1060 +#define MSDC_INTEN_DMAQ_EMPTY (0x1 << 6) /* RW */
1061 +#define MSDC_INTEN_SDIOIRQ (0x1 << 7) /* RW */
1062 +#define MSDC_INTEN_CMDRDY (0x1 << 8) /* RW */
1063 +#define MSDC_INTEN_CMDTMO (0x1 << 9) /* RW */
1064 +#define MSDC_INTEN_RSPCRCERR (0x1 << 10) /* RW */
1065 +#define MSDC_INTEN_CSTA (0x1 << 11) /* RW */
1066 +#define MSDC_INTEN_XFER_COMPL (0x1 << 12) /* RW */
1067 +#define MSDC_INTEN_DXFER_DONE (0x1 << 13) /* RW */
1068 +#define MSDC_INTEN_DATTMO (0x1 << 14) /* RW */
1069 +#define MSDC_INTEN_DATCRCERR (0x1 << 15) /* RW */
1070 +#define MSDC_INTEN_ACMD19_DONE (0x1 << 16) /* RW */
1071 +
1072 +/* MSDC_FIFOCS mask */
1073 +#define MSDC_FIFOCS_RXCNT (0xff << 0) /* R */
1074 +#define MSDC_FIFOCS_TXCNT (0xff << 16) /* R */
1075 +#define MSDC_FIFOCS_CLR (0x1UL<< 31) /* RW */
1076 +
1077 +/* SDC_CFG mask */
1078 +#define SDC_CFG_SDIOINTWKUP (0x1 << 0) /* RW */
1079 +#define SDC_CFG_INSWKUP (0x1 << 1) /* RW */
1080 +#define SDC_CFG_BUSWIDTH (0x3 << 16) /* RW */
1081 +#define SDC_CFG_SDIO (0x1 << 19) /* RW */
1082 +#define SDC_CFG_SDIOIDE (0x1 << 20) /* RW */
1083 +#define SDC_CFG_INTATGAP (0x1 << 21) /* RW */
1084 +#define SDC_CFG_DTOC (0xffUL << 24) /* RW */
1085 +
1086 +/* SDC_CMD mask */
1087 +#define SDC_CMD_OPC (0x3f << 0) /* RW */
1088 +#define SDC_CMD_BRK (0x1 << 6) /* RW */
1089 +#define SDC_CMD_RSPTYP (0x7 << 7) /* RW */
1090 +#define SDC_CMD_DTYP (0x3 << 11) /* RW */
1091 +#define SDC_CMD_DTYP (0x3 << 11) /* RW */
1092 +#define SDC_CMD_RW (0x1 << 13) /* RW */
1093 +#define SDC_CMD_STOP (0x1 << 14) /* RW */
1094 +#define SDC_CMD_GOIRQ (0x1 << 15) /* RW */
1095 +#define SDC_CMD_BLKLEN (0xfff<< 16) /* RW */
1096 +#define SDC_CMD_AUTOCMD (0x3 << 28) /* RW */
1097 +#define SDC_CMD_VOLSWTH (0x1 << 30) /* RW */
1098 +
1099 +/* SDC_STS mask */
1100 +#define SDC_STS_SDCBUSY (0x1 << 0) /* RW */
1101 +#define SDC_STS_CMDBUSY (0x1 << 1) /* RW */
1102 +#define SDC_STS_SWR_COMPL (0x1 << 31) /* RW */
1103 +
1104 +/* SDC_DCRC_STS mask */
1105 +#define SDC_DCRC_STS_NEG (0xf << 8) /* RO */
1106 +#define SDC_DCRC_STS_POS (0xff << 0) /* RO */
1107 +
1108 +/* EMMC_CFG0 mask */
1109 +#define EMMC_CFG0_BOOTSTART (0x1 << 0) /* W */
1110 +#define EMMC_CFG0_BOOTSTOP (0x1 << 1) /* W */
1111 +#define EMMC_CFG0_BOOTMODE (0x1 << 2) /* RW */
1112 +#define EMMC_CFG0_BOOTACKDIS (0x1 << 3) /* RW */
1113 +#define EMMC_CFG0_BOOTWDLY (0x7 << 12) /* RW */
1114 +#define EMMC_CFG0_BOOTSUPP (0x1 << 15) /* RW */
1115 +
1116 +/* EMMC_CFG1 mask */
1117 +#define EMMC_CFG1_BOOTDATTMC (0xfffff << 0) /* RW */
1118 +#define EMMC_CFG1_BOOTACKTMC (0xfffUL << 20) /* RW */
1119 +
1120 +/* EMMC_STS mask */
1121 +#define EMMC_STS_BOOTCRCERR (0x1 << 0) /* W1C */
1122 +#define EMMC_STS_BOOTACKERR (0x1 << 1) /* W1C */
1123 +#define EMMC_STS_BOOTDATTMO (0x1 << 2) /* W1C */
1124 +#define EMMC_STS_BOOTACKTMO (0x1 << 3) /* W1C */
1125 +#define EMMC_STS_BOOTUPSTATE (0x1 << 4) /* R */
1126 +#define EMMC_STS_BOOTACKRCV (0x1 << 5) /* W1C */
1127 +#define EMMC_STS_BOOTDATRCV (0x1 << 6) /* R */
1128 +
1129 +/* EMMC_IOCON mask */
1130 +#define EMMC_IOCON_BOOTRST (0x1 << 0) /* RW */
1131 +
1132 +/* SDC_ACMD19_TRG mask */
1133 +#define SDC_ACMD19_TRG_TUNESEL (0xf << 0) /* RW */
1134 +
1135 +/* MSDC_DMA_CTRL mask */
1136 +#define MSDC_DMA_CTRL_START (0x1 << 0) /* W */
1137 +#define MSDC_DMA_CTRL_STOP (0x1 << 1) /* W */
1138 +#define MSDC_DMA_CTRL_RESUME (0x1 << 2) /* W */
1139 +#define MSDC_DMA_CTRL_MODE (0x1 << 8) /* RW */
1140 +#define MSDC_DMA_CTRL_LASTBUF (0x1 << 10) /* RW */
1141 +#define MSDC_DMA_CTRL_BRUSTSZ (0x7 << 12) /* RW */
1142 +#define MSDC_DMA_CTRL_XFERSZ (0xffffUL << 16)/* RW */
1143 +
1144 +/* MSDC_DMA_CFG mask */
1145 +#define MSDC_DMA_CFG_STS (0x1 << 0) /* R */
1146 +#define MSDC_DMA_CFG_DECSEN (0x1 << 1) /* RW */
1147 +#define MSDC_DMA_CFG_BDCSERR (0x1 << 4) /* R */
1148 +#define MSDC_DMA_CFG_GPDCSERR (0x1 << 5) /* R */
1149 +
1150 +/* MSDC_PATCH_BIT mask */
1151 +#define MSDC_PATCH_BIT_WFLSMODE (0x1 << 0) /* RW */
1152 +#define MSDC_PATCH_BIT_ODDSUPP (0x1 << 1) /* RW */
1153 +#define MSDC_PATCH_BIT_CKGEN_CK (0x1 << 6) /* E2: Fixed to 1 */
1154 +#define MSDC_PATCH_BIT_IODSSEL (0x1 << 16) /* RW */
1155 +#define MSDC_PATCH_BIT_IOINTSEL (0x1 << 17) /* RW */
1156 +#define MSDC_PATCH_BIT_BUSYDLY (0xf << 18) /* RW */
1157 +#define MSDC_PATCH_BIT_WDOD (0xf << 22) /* RW */
1158 +#define MSDC_PATCH_BIT_IDRTSEL (0x1 << 26) /* RW */
1159 +#define MSDC_PATCH_BIT_CMDFSEL (0x1 << 27) /* RW */
1160 +#define MSDC_PATCH_BIT_INTDLSEL (0x1 << 28) /* RW */
1161 +#define MSDC_PATCH_BIT_SPCPUSH (0x1 << 29) /* RW */
1162 +#define MSDC_PATCH_BIT_DECRCTMO (0x1 << 30) /* RW */
1163 +
1164 +/* MSDC_PATCH_BIT1 mask */
1165 +#define MSDC_PATCH_BIT1_WRDAT_CRCS (0x7 << 3)
1166 +#define MSDC_PATCH_BIT1_CMD_RSP (0x7 << 0)
1167 +
1168 +/* MSDC_PAD_CTL0 mask */
1169 +#define MSDC_PAD_CTL0_CLKDRVN (0x7 << 0) /* RW */
1170 +#define MSDC_PAD_CTL0_CLKDRVP (0x7 << 4) /* RW */
1171 +#define MSDC_PAD_CTL0_CLKSR (0x1 << 8) /* RW */
1172 +#define MSDC_PAD_CTL0_CLKPD (0x1 << 16) /* RW */
1173 +#define MSDC_PAD_CTL0_CLKPU (0x1 << 17) /* RW */
1174 +#define MSDC_PAD_CTL0_CLKSMT (0x1 << 18) /* RW */
1175 +#define MSDC_PAD_CTL0_CLKIES (0x1 << 19) /* RW */
1176 +#define MSDC_PAD_CTL0_CLKTDSEL (0xf << 20) /* RW */
1177 +#define MSDC_PAD_CTL0_CLKRDSEL (0xffUL<< 24) /* RW */
1178 +
1179 +/* MSDC_PAD_CTL1 mask */
1180 +#define MSDC_PAD_CTL1_CMDDRVN (0x7 << 0) /* RW */
1181 +#define MSDC_PAD_CTL1_CMDDRVP (0x7 << 4) /* RW */
1182 +#define MSDC_PAD_CTL1_CMDSR (0x1 << 8) /* RW */
1183 +#define MSDC_PAD_CTL1_CMDPD (0x1 << 16) /* RW */
1184 +#define MSDC_PAD_CTL1_CMDPU (0x1 << 17) /* RW */
1185 +#define MSDC_PAD_CTL1_CMDSMT (0x1 << 18) /* RW */
1186 +#define MSDC_PAD_CTL1_CMDIES (0x1 << 19) /* RW */
1187 +#define MSDC_PAD_CTL1_CMDTDSEL (0xf << 20) /* RW */
1188 +#define MSDC_PAD_CTL1_CMDRDSEL (0xffUL<< 24) /* RW */
1189 +
1190 +/* MSDC_PAD_CTL2 mask */
1191 +#define MSDC_PAD_CTL2_DATDRVN (0x7 << 0) /* RW */
1192 +#define MSDC_PAD_CTL2_DATDRVP (0x7 << 4) /* RW */
1193 +#define MSDC_PAD_CTL2_DATSR (0x1 << 8) /* RW */
1194 +#define MSDC_PAD_CTL2_DATPD (0x1 << 16) /* RW */
1195 +#define MSDC_PAD_CTL2_DATPU (0x1 << 17) /* RW */
1196 +#define MSDC_PAD_CTL2_DATIES (0x1 << 19) /* RW */
1197 +#define MSDC_PAD_CTL2_DATSMT (0x1 << 18) /* RW */
1198 +#define MSDC_PAD_CTL2_DATTDSEL (0xf << 20) /* RW */
1199 +#define MSDC_PAD_CTL2_DATRDSEL (0xffUL<< 24) /* RW */
1200 +
1201 +/* MSDC_PAD_TUNE mask */
1202 +#define MSDC_PAD_TUNE_DATWRDLY (0x1F << 0) /* RW */
1203 +#define MSDC_PAD_TUNE_DATRRDLY (0x1F << 8) /* RW */
1204 +#define MSDC_PAD_TUNE_CMDRDLY (0x1F << 16) /* RW */
1205 +#define MSDC_PAD_TUNE_CMDRRDLY (0x1FUL << 22) /* RW */
1206 +#define MSDC_PAD_TUNE_CLKTXDLY (0x1FUL << 27) /* RW */
1207 +
1208 +/* MSDC_DAT_RDDLY0/1 mask */
1209 +#define MSDC_DAT_RDDLY0_D0 (0x1F << 0) /* RW */
1210 +#define MSDC_DAT_RDDLY0_D1 (0x1F << 8) /* RW */
1211 +#define MSDC_DAT_RDDLY0_D2 (0x1F << 16) /* RW */
1212 +#define MSDC_DAT_RDDLY0_D3 (0x1F << 24) /* RW */
1213 +
1214 +#define MSDC_DAT_RDDLY1_D4 (0x1F << 0) /* RW */
1215 +#define MSDC_DAT_RDDLY1_D5 (0x1F << 8) /* RW */
1216 +#define MSDC_DAT_RDDLY1_D6 (0x1F << 16) /* RW */
1217 +#define MSDC_DAT_RDDLY1_D7 (0x1F << 24) /* RW */
1218 +
1219 +#define MSDC_CKGEN_MSDC_DLY_SEL (0x1F<<10)
1220 +#define MSDC_INT_DAT_LATCH_CK_SEL (0x7<<7)
1221 +#define MSDC_CKGEN_MSDC_CK_SEL (0x1<<6)
1222 +#define CARD_READY_FOR_DATA (1<<8)
1223 +#define CARD_CURRENT_STATE(x) ((x&0x00001E00)>>9)
1224 +
1225 +/*--------------------------------------------------------------------------*/
1226 +/* Descriptor Structure */
1227 +/*--------------------------------------------------------------------------*/
1228 +typedef struct {
1229 + u32 hwo:1; /* could be changed by hw */
1230 + u32 bdp:1;
1231 + u32 rsv0:6;
1232 + u32 chksum:8;
1233 + u32 intr:1;
1234 + u32 rsv1:15;
1235 + void *next;
1236 + void *ptr;
1237 + u32 buflen:16;
1238 + u32 extlen:8;
1239 + u32 rsv2:8;
1240 + u32 arg;
1241 + u32 blknum;
1242 + u32 cmd;
1243 +} gpd_t;
1244 +
1245 +typedef struct {
1246 + u32 eol:1;
1247 + u32 rsv0:7;
1248 + u32 chksum:8;
1249 + u32 rsv1:1;
1250 + u32 blkpad:1;
1251 + u32 dwpad:1;
1252 + u32 rsv2:13;
1253 + void *next;
1254 + void *ptr;
1255 + u32 buflen:16;
1256 + u32 rsv3:16;
1257 +} bd_t;
1258 +
1259 +/*--------------------------------------------------------------------------*/
1260 +/* Register Debugging Structure */
1261 +/*--------------------------------------------------------------------------*/
1262 +
1263 +typedef struct {
1264 + u32 msdc:1;
1265 + u32 ckpwn:1;
1266 + u32 rst:1;
1267 + u32 pio:1;
1268 + u32 ckdrven:1;
1269 + u32 start18v:1;
1270 + u32 pass18v:1;
1271 + u32 ckstb:1;
1272 + u32 ckdiv:8;
1273 + u32 ckmod:2;
1274 + u32 pad:14;
1275 +} msdc_cfg_reg;
1276 +typedef struct {
1277 + u32 sdr104cksel:1;
1278 + u32 rsmpl:1;
1279 + u32 dsmpl:1;
1280 + u32 ddlysel:1;
1281 + u32 ddr50ckd:1;
1282 + u32 dsplsel:1;
1283 + u32 pad1:10;
1284 + u32 d0spl:1;
1285 + u32 d1spl:1;
1286 + u32 d2spl:1;
1287 + u32 d3spl:1;
1288 + u32 d4spl:1;
1289 + u32 d5spl:1;
1290 + u32 d6spl:1;
1291 + u32 d7spl:1;
1292 + u32 riscsz:1;
1293 + u32 pad2:7;
1294 +} msdc_iocon_reg;
1295 +typedef struct {
1296 + u32 cden:1;
1297 + u32 cdsts:1;
1298 + u32 pad1:10;
1299 + u32 cddebounce:4;
1300 + u32 dat:8;
1301 + u32 cmd:1;
1302 + u32 pad2:6;
1303 + u32 wp:1;
1304 +} msdc_ps_reg;
1305 +typedef struct {
1306 + u32 mmcirq:1;
1307 + u32 cdsc:1;
1308 + u32 pad1:1;
1309 + u32 atocmdrdy:1;
1310 + u32 atocmdtmo:1;
1311 + u32 atocmdcrc:1;
1312 + u32 dmaqempty:1;
1313 + u32 sdioirq:1;
1314 + u32 cmdrdy:1;
1315 + u32 cmdtmo:1;
1316 + u32 rspcrc:1;
1317 + u32 csta:1;
1318 + u32 xfercomp:1;
1319 + u32 dxferdone:1;
1320 + u32 dattmo:1;
1321 + u32 datcrc:1;
1322 + u32 atocmd19done:1;
1323 + u32 pad2:15;
1324 +} msdc_int_reg;
1325 +typedef struct {
1326 + u32 mmcirq:1;
1327 + u32 cdsc:1;
1328 + u32 pad1:1;
1329 + u32 atocmdrdy:1;
1330 + u32 atocmdtmo:1;
1331 + u32 atocmdcrc:1;
1332 + u32 dmaqempty:1;
1333 + u32 sdioirq:1;
1334 + u32 cmdrdy:1;
1335 + u32 cmdtmo:1;
1336 + u32 rspcrc:1;
1337 + u32 csta:1;
1338 + u32 xfercomp:1;
1339 + u32 dxferdone:1;
1340 + u32 dattmo:1;
1341 + u32 datcrc:1;
1342 + u32 atocmd19done:1;
1343 + u32 pad2:15;
1344 +} msdc_inten_reg;
1345 +typedef struct {
1346 + u32 rxcnt:8;
1347 + u32 pad1:8;
1348 + u32 txcnt:8;
1349 + u32 pad2:7;
1350 + u32 clr:1;
1351 +} msdc_fifocs_reg;
1352 +typedef struct {
1353 + u32 val;
1354 +} msdc_txdat_reg;
1355 +typedef struct {
1356 + u32 val;
1357 +} msdc_rxdat_reg;
1358 +typedef struct {
1359 + u32 sdiowkup:1;
1360 + u32 inswkup:1;
1361 + u32 pad1:14;
1362 + u32 buswidth:2;
1363 + u32 pad2:1;
1364 + u32 sdio:1;
1365 + u32 sdioide:1;
1366 + u32 intblkgap:1;
1367 + u32 pad4:2;
1368 + u32 dtoc:8;
1369 +} sdc_cfg_reg;
1370 +typedef struct {
1371 + u32 cmd:6;
1372 + u32 brk:1;
1373 + u32 rsptyp:3;
1374 + u32 pad1:1;
1375 + u32 dtype:2;
1376 + u32 rw:1;
1377 + u32 stop:1;
1378 + u32 goirq:1;
1379 + u32 blklen:12;
1380 + u32 atocmd:2;
1381 + u32 volswth:1;
1382 + u32 pad2:1;
1383 +} sdc_cmd_reg;
1384 +typedef struct {
1385 + u32 arg;
1386 +} sdc_arg_reg;
1387 +typedef struct {
1388 + u32 sdcbusy:1;
1389 + u32 cmdbusy:1;
1390 + u32 pad:29;
1391 + u32 swrcmpl:1;
1392 +} sdc_sts_reg;
1393 +typedef struct {
1394 + u32 val;
1395 +} sdc_resp0_reg;
1396 +typedef struct {
1397 + u32 val;
1398 +} sdc_resp1_reg;
1399 +typedef struct {
1400 + u32 val;
1401 +} sdc_resp2_reg;
1402 +typedef struct {
1403 + u32 val;
1404 +} sdc_resp3_reg;
1405 +typedef struct {
1406 + u32 num;
1407 +} sdc_blknum_reg;
1408 +typedef struct {
1409 + u32 sts;
1410 +} sdc_csts_reg;
1411 +typedef struct {
1412 + u32 sts;
1413 +} sdc_cstsen_reg;
1414 +typedef struct {
1415 + u32 datcrcsts:8;
1416 + u32 ddrcrcsts:4;
1417 + u32 pad:20;
1418 +} sdc_datcrcsts_reg;
1419 +typedef struct {
1420 + u32 bootstart:1;
1421 + u32 bootstop:1;
1422 + u32 bootmode:1;
1423 + u32 pad1:9;
1424 + u32 bootwaidly:3;
1425 + u32 bootsupp:1;
1426 + u32 pad2:16;
1427 +} emmc_cfg0_reg;
1428 +typedef struct {
1429 + u32 bootcrctmc:16;
1430 + u32 pad:4;
1431 + u32 bootacktmc:12;
1432 +} emmc_cfg1_reg;
1433 +typedef struct {
1434 + u32 bootcrcerr:1;
1435 + u32 bootackerr:1;
1436 + u32 bootdattmo:1;
1437 + u32 bootacktmo:1;
1438 + u32 bootupstate:1;
1439 + u32 bootackrcv:1;
1440 + u32 bootdatrcv:1;
1441 + u32 pad:25;
1442 +} emmc_sts_reg;
1443 +typedef struct {
1444 + u32 bootrst:1;
1445 + u32 pad:31;
1446 +} emmc_iocon_reg;
1447 +typedef struct {
1448 + u32 val;
1449 +} msdc_acmd_resp_reg;
1450 +typedef struct {
1451 + u32 tunesel:4;
1452 + u32 pad:28;
1453 +} msdc_acmd19_trg_reg;
1454 +typedef struct {
1455 + u32 val;
1456 +} msdc_acmd19_sts_reg;
1457 +typedef struct {
1458 + u32 addr;
1459 +} msdc_dma_sa_reg;
1460 +typedef struct {
1461 + u32 addr;
1462 +} msdc_dma_ca_reg;
1463 +typedef struct {
1464 + u32 start:1;
1465 + u32 stop:1;
1466 + u32 resume:1;
1467 + u32 pad1:5;
1468 + u32 mode:1;
1469 + u32 pad2:1;
1470 + u32 lastbuf:1;
1471 + u32 pad3:1;
1472 + u32 brustsz:3;
1473 + u32 pad4:1;
1474 + u32 xfersz:16;
1475 +} msdc_dma_ctrl_reg;
1476 +typedef struct {
1477 + u32 status:1;
1478 + u32 decsen:1;
1479 + u32 pad1:2;
1480 + u32 bdcsen:1;
1481 + u32 gpdcsen:1;
1482 + u32 pad2:26;
1483 +} msdc_dma_cfg_reg;
1484 +typedef struct {
1485 + u32 sel:16;
1486 + u32 pad2:16;
1487 +} msdc_dbg_sel_reg;
1488 +typedef struct {
1489 + u32 val;
1490 +} msdc_dbg_out_reg;
1491 +typedef struct {
1492 + u32 clkdrvn:3;
1493 + u32 rsv0:1;
1494 + u32 clkdrvp:3;
1495 + u32 rsv1:1;
1496 + u32 clksr:1;
1497 + u32 rsv2:7;
1498 + u32 clkpd:1;
1499 + u32 clkpu:1;
1500 + u32 clksmt:1;
1501 + u32 clkies:1;
1502 + u32 clktdsel:4;
1503 + u32 clkrdsel:8;
1504 +} msdc_pad_ctl0_reg;
1505 +typedef struct {
1506 + u32 cmddrvn:3;
1507 + u32 rsv0:1;
1508 + u32 cmddrvp:3;
1509 + u32 rsv1:1;
1510 + u32 cmdsr:1;
1511 + u32 rsv2:7;
1512 + u32 cmdpd:1;
1513 + u32 cmdpu:1;
1514 + u32 cmdsmt:1;
1515 + u32 cmdies:1;
1516 + u32 cmdtdsel:4;
1517 + u32 cmdrdsel:8;
1518 +} msdc_pad_ctl1_reg;
1519 +typedef struct {
1520 + u32 datdrvn:3;
1521 + u32 rsv0:1;
1522 + u32 datdrvp:3;
1523 + u32 rsv1:1;
1524 + u32 datsr:1;
1525 + u32 rsv2:7;
1526 + u32 datpd:1;
1527 + u32 datpu:1;
1528 + u32 datsmt:1;
1529 + u32 daties:1;
1530 + u32 dattdsel:4;
1531 + u32 datrdsel:8;
1532 +} msdc_pad_ctl2_reg;
1533 +typedef struct {
1534 + u32 wrrxdly:3;
1535 + u32 pad1:5;
1536 + u32 rdrxdly:8;
1537 + u32 pad2:16;
1538 +} msdc_pad_tune_reg;
1539 +typedef struct {
1540 + u32 dat0:5;
1541 + u32 rsv0:3;
1542 + u32 dat1:5;
1543 + u32 rsv1:3;
1544 + u32 dat2:5;
1545 + u32 rsv2:3;
1546 + u32 dat3:5;
1547 + u32 rsv3:3;
1548 +} msdc_dat_rddly0;
1549 +typedef struct {
1550 + u32 dat4:5;
1551 + u32 rsv4:3;
1552 + u32 dat5:5;
1553 + u32 rsv5:3;
1554 + u32 dat6:5;
1555 + u32 rsv6:3;
1556 + u32 dat7:5;
1557 + u32 rsv7:3;
1558 +} msdc_dat_rddly1;
1559 +typedef struct {
1560 + u32 dbg0sel:8;
1561 + u32 dbg1sel:6;
1562 + u32 pad1:2;
1563 + u32 dbg2sel:6;
1564 + u32 pad2:2;
1565 + u32 dbg3sel:6;
1566 + u32 pad3:2;
1567 +} msdc_hw_dbg_reg;
1568 +typedef struct {
1569 + u32 val;
1570 +} msdc_version_reg;
1571 +typedef struct {
1572 + u32 val;
1573 +} msdc_eco_ver_reg;
1574 +
1575 +struct msdc_regs {
1576 + msdc_cfg_reg msdc_cfg; /* base+0x00h */
1577 + msdc_iocon_reg msdc_iocon; /* base+0x04h */
1578 + msdc_ps_reg msdc_ps; /* base+0x08h */
1579 + msdc_int_reg msdc_int; /* base+0x0ch */
1580 + msdc_inten_reg msdc_inten; /* base+0x10h */
1581 + msdc_fifocs_reg msdc_fifocs; /* base+0x14h */
1582 + msdc_txdat_reg msdc_txdat; /* base+0x18h */
1583 + msdc_rxdat_reg msdc_rxdat; /* base+0x1ch */
1584 + u32 rsv1[4];
1585 + sdc_cfg_reg sdc_cfg; /* base+0x30h */
1586 + sdc_cmd_reg sdc_cmd; /* base+0x34h */
1587 + sdc_arg_reg sdc_arg; /* base+0x38h */
1588 + sdc_sts_reg sdc_sts; /* base+0x3ch */
1589 + sdc_resp0_reg sdc_resp0; /* base+0x40h */
1590 + sdc_resp1_reg sdc_resp1; /* base+0x44h */
1591 + sdc_resp2_reg sdc_resp2; /* base+0x48h */
1592 + sdc_resp3_reg sdc_resp3; /* base+0x4ch */
1593 + sdc_blknum_reg sdc_blknum; /* base+0x50h */
1594 + u32 rsv2[1];
1595 + sdc_csts_reg sdc_csts; /* base+0x58h */
1596 + sdc_cstsen_reg sdc_cstsen; /* base+0x5ch */
1597 + sdc_datcrcsts_reg sdc_dcrcsta; /* base+0x60h */
1598 + u32 rsv3[3];
1599 + emmc_cfg0_reg emmc_cfg0; /* base+0x70h */
1600 + emmc_cfg1_reg emmc_cfg1; /* base+0x74h */
1601 + emmc_sts_reg emmc_sts; /* base+0x78h */
1602 + emmc_iocon_reg emmc_iocon; /* base+0x7ch */
1603 + msdc_acmd_resp_reg acmd_resp; /* base+0x80h */
1604 + msdc_acmd19_trg_reg acmd19_trg; /* base+0x84h */
1605 + msdc_acmd19_sts_reg acmd19_sts; /* base+0x88h */
1606 + u32 rsv4[1];
1607 + msdc_dma_sa_reg dma_sa; /* base+0x90h */
1608 + msdc_dma_ca_reg dma_ca; /* base+0x94h */
1609 + msdc_dma_ctrl_reg dma_ctrl; /* base+0x98h */
1610 + msdc_dma_cfg_reg dma_cfg; /* base+0x9ch */
1611 + msdc_dbg_sel_reg dbg_sel; /* base+0xa0h */
1612 + msdc_dbg_out_reg dbg_out; /* base+0xa4h */
1613 + u32 rsv5[2];
1614 + u32 patch0; /* base+0xb0h */
1615 + u32 patch1; /* base+0xb4h */
1616 + u32 rsv6[10];
1617 + msdc_pad_ctl0_reg pad_ctl0; /* base+0xe0h */
1618 + msdc_pad_ctl1_reg pad_ctl1; /* base+0xe4h */
1619 + msdc_pad_ctl2_reg pad_ctl2; /* base+0xe8h */
1620 + msdc_pad_tune_reg pad_tune; /* base+0xech */
1621 + msdc_dat_rddly0 dat_rddly0; /* base+0xf0h */
1622 + msdc_dat_rddly1 dat_rddly1; /* base+0xf4h */
1623 + msdc_hw_dbg_reg hw_dbg; /* base+0xf8h */
1624 + u32 rsv7[1];
1625 + msdc_version_reg version; /* base+0x100h */
1626 + msdc_eco_ver_reg eco_ver; /* base+0x104h */
1627 +};
1628 +
1629 +struct scatterlist_ex {
1630 + u32 cmd;
1631 + u32 arg;
1632 + u32 sglen;
1633 + struct scatterlist *sg;
1634 +};
1635 +
1636 +#define DMA_FLAG_NONE (0x00000000)
1637 +#define DMA_FLAG_EN_CHKSUM (0x00000001)
1638 +#define DMA_FLAG_PAD_BLOCK (0x00000002)
1639 +#define DMA_FLAG_PAD_DWORD (0x00000004)
1640 +
1641 +struct msdc_dma {
1642 + u32 flags; /* flags */
1643 + u32 xfersz; /* xfer size in bytes */
1644 + u32 sglen; /* size of scatter list */
1645 + u32 blklen; /* block size */
1646 + struct scatterlist *sg; /* I/O scatter list */
1647 + struct scatterlist_ex *esg; /* extended I/O scatter list */
1648 + u8 mode; /* dma mode */
1649 + u8 burstsz; /* burst size */
1650 + u8 intr; /* dma done interrupt */
1651 + u8 padding; /* padding */
1652 + u32 cmd; /* enhanced mode command */
1653 + u32 arg; /* enhanced mode arg */
1654 + u32 rsp; /* enhanced mode command response */
1655 + u32 autorsp; /* auto command response */
1656 +
1657 + gpd_t *gpd; /* pointer to gpd array */
1658 + bd_t *bd; /* pointer to bd array */
1659 + dma_addr_t gpd_addr; /* the physical address of gpd array */
1660 + dma_addr_t bd_addr; /* the physical address of bd array */
1661 + u32 used_gpd; /* the number of used gpd elements */
1662 + u32 used_bd; /* the number of used bd elements */
1663 +};
1664 +
1665 +struct msdc_host
1666 +{
1667 + struct msdc_hw *hw;
1668 +
1669 + struct mmc_host *mmc; /* mmc structure */
1670 + struct mmc_command *cmd;
1671 + struct mmc_data *data;
1672 + struct mmc_request *mrq;
1673 + int cmd_rsp;
1674 + int cmd_rsp_done;
1675 + int cmd_r1b_done;
1676 +
1677 + int error;
1678 + spinlock_t lock; /* mutex */
1679 + struct semaphore sem;
1680 +
1681 + u32 blksz; /* host block size */
1682 + u32 base; /* host base address */
1683 + int id; /* host id */
1684 + int pwr_ref; /* core power reference count */
1685 +
1686 + u32 xfer_size; /* total transferred size */
1687 +
1688 + struct msdc_dma dma; /* dma channel */
1689 + u32 dma_addr; /* dma transfer address */
1690 + u32 dma_left_size; /* dma transfer left size */
1691 + u32 dma_xfer_size; /* dma transfer size in bytes */
1692 + int dma_xfer; /* dma transfer mode */
1693 +
1694 + u32 timeout_ns; /* data timeout ns */
1695 + u32 timeout_clks; /* data timeout clks */
1696 +
1697 + atomic_t abort; /* abort transfer */
1698 +
1699 + int irq; /* host interrupt */
1700 +
1701 + struct tasklet_struct card_tasklet;
1702 +#if 0
1703 + struct work_struct card_workqueue;
1704 +#else
1705 + struct delayed_work card_delaywork;
1706 +#endif
1707 +
1708 + struct completion cmd_done;
1709 + struct completion xfer_done;
1710 + struct pm_message pm_state;
1711 +
1712 + u32 mclk; /* mmc subsystem clock */
1713 + u32 hclk; /* host clock speed */
1714 + u32 sclk; /* SD/MS clock speed */
1715 + u8 core_clkon; /* Host core clock on ? */
1716 + u8 card_clkon; /* Card clock on ? */
1717 + u8 core_power; /* core power */
1718 + u8 power_mode; /* host power mode */
1719 + u8 card_inserted; /* card inserted ? */
1720 + u8 suspend; /* host suspended ? */
1721 + u8 reserved;
1722 + u8 app_cmd; /* for app command */
1723 + u32 app_cmd_arg;
1724 + u64 starttime;
1725 +};
1726 +
1727 +static inline unsigned int uffs(unsigned int x)
1728 +{
1729 + unsigned int r = 1;
1730 +
1731 + if (!x)
1732 + return 0;
1733 + if (!(x & 0xffff)) {
1734 + x >>= 16;
1735 + r += 16;
1736 + }
1737 + if (!(x & 0xff)) {
1738 + x >>= 8;
1739 + r += 8;
1740 + }
1741 + if (!(x & 0xf)) {
1742 + x >>= 4;
1743 + r += 4;
1744 + }
1745 + if (!(x & 3)) {
1746 + x >>= 2;
1747 + r += 2;
1748 + }
1749 + if (!(x & 1)) {
1750 + x >>= 1;
1751 + r += 1;
1752 + }
1753 + return r;
1754 +}
1755 +#define sdr_read8(reg) __raw_readb(reg)
1756 +#define sdr_read16(reg) __raw_readw(reg)
1757 +#define sdr_read32(reg) __raw_readl(reg)
1758 +#define sdr_write8(reg,val) __raw_writeb(val,reg)
1759 +#define sdr_write16(reg,val) __raw_writew(val,reg)
1760 +#define sdr_write32(reg,val) __raw_writel(val,reg)
1761 +
1762 +#define sdr_set_bits(reg,bs) ((*(volatile u32*)(reg)) |= (u32)(bs))
1763 +#define sdr_clr_bits(reg,bs) ((*(volatile u32*)(reg)) &= ~((u32)(bs)))
1764 +
1765 +#define sdr_set_field(reg,field,val) \
1766 + do { \
1767 + volatile unsigned int tv = sdr_read32(reg); \
1768 + tv &= ~(field); \
1769 + tv |= ((val) << (uffs((unsigned int)field) - 1)); \
1770 + sdr_write32(reg,tv); \
1771 + } while(0)
1772 +#define sdr_get_field(reg,field,val) \
1773 + do { \
1774 + volatile unsigned int tv = sdr_read32(reg); \
1775 + val = ((tv & (field)) >> (uffs((unsigned int)field) - 1)); \
1776 + } while(0)
1777 +
1778 +#endif
1779 +
1780 diff --git a/drivers/mmc/host/mtk-mmc/sd.c b/drivers/mmc/host/mtk-mmc/sd.c
1781 new file mode 100644
1782 index 0000000..0bb60c1
1783 --- /dev/null
1784 +++ b/drivers/mmc/host/mtk-mmc/sd.c
1785 @@ -0,0 +1,3041 @@
1786 +/* Copyright Statement:
1787 + *
1788 + * This software/firmware and related documentation ("MediaTek Software") are
1789 + * protected under relevant copyright laws. The information contained herein
1790 + * is confidential and proprietary to MediaTek Inc. and/or its licensors.
1791 + * Without the prior written permission of MediaTek inc. and/or its licensors,
1792 + * any reproduction, modification, use or disclosure of MediaTek Software,
1793 + * and information contained herein, in whole or in part, shall be strictly prohibited.
1794 + *
1795 + * MediaTek Inc. (C) 2010. All rights reserved.
1796 + *
1797 + * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
1798 + * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
1799 + * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
1800 + * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
1801 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
1802 + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
1803 + * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
1804 + * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
1805 + * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
1806 + * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
1807 + * THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
1808 + * CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
1809 + * SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
1810 + * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
1811 + * CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
1812 + * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
1813 + * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
1814 + * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
1815 + *
1816 + * The following software/firmware and/or related documentation ("MediaTek Software")
1817 + * have been modified by MediaTek Inc. All revisions are subject to any receiver's
1818 + * applicable license agreements with MediaTek Inc.
1819 + */
1820 +
1821 +#include <linux/module.h>
1822 +#include <linux/moduleparam.h>
1823 +#include <linux/init.h>
1824 +#include <linux/spinlock.h>
1825 +#include <linux/timer.h>
1826 +#include <linux/ioport.h>
1827 +#include <linux/device.h>
1828 +#include <linux/platform_device.h>
1829 +#include <linux/interrupt.h>
1830 +#include <linux/delay.h>
1831 +#include <linux/blkdev.h>
1832 +#include <linux/slab.h>
1833 +#include <linux/mmc/host.h>
1834 +#include <linux/mmc/card.h>
1835 +#include <linux/mmc/core.h>
1836 +#include <linux/mmc/mmc.h>
1837 +#include <linux/mmc/sd.h>
1838 +#include <linux/mmc/sdio.h>
1839 +#include <linux/dma-mapping.h>
1840 +
1841 +/* +++ by chhung */
1842 +#include <linux/types.h>
1843 +#include <linux/kernel.h>
1844 +#include <linux/version.h>
1845 +#include <linux/pm.h>
1846 +
1847 +#define MSDC_SMPL_FALLING (1)
1848 +#define MSDC_CD_PIN_EN (1 << 0) /* card detection pin is wired */
1849 +#define MSDC_WP_PIN_EN (1 << 1) /* write protection pin is wired */
1850 +#define MSDC_REMOVABLE (1 << 5) /* removable slot */
1851 +#define MSDC_SYS_SUSPEND (1 << 6) /* suspended by system */
1852 +#define MSDC_HIGHSPEED (1 << 7)
1853 +
1854 +//#define IRQ_SDC 14 //MT7620 /*FIXME*/
1855 +#define RALINK_SYSCTL_BASE 0xb0000000
1856 +#define RALINK_MSDC_BASE 0xb0130000
1857 +#define IRQ_SDC 22 /*FIXME*/
1858 +
1859 +#include <asm/dma.h>
1860 +/* end of +++ */
1861 +
1862 +#include <asm/mach-ralink/ralink_regs.h>
1863 +
1864 +#if 0 /* --- by chhung */
1865 +#include <mach/board.h>
1866 +#include <mach/mt6575_devs.h>
1867 +#include <mach/mt6575_typedefs.h>
1868 +#include <mach/mt6575_clock_manager.h>
1869 +#include <mach/mt6575_pm_ldo.h>
1870 +//#include <mach/mt6575_pll.h>
1871 +//#include <mach/mt6575_gpio.h>
1872 +//#include <mach/mt6575_gpt_sw.h>
1873 +#include <asm/tcm.h>
1874 +// #include <mach/mt6575_gpt.h>
1875 +#endif /* end of --- */
1876 +
1877 +#include "mt6575_sd.h"
1878 +#include "dbg.h"
1879 +
1880 +/* +++ by chhung */
1881 +#include "board.h"
1882 +/* end of +++ */
1883 +
1884 +#if 0 /* --- by chhung */
1885 +#define isb() __asm__ __volatile__ ("" : : : "memory")
1886 +#define dsb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" \
1887 + : : "r" (0) : "memory")
1888 +#define dmb() __asm__ __volatile__ ("" : : : "memory")
1889 +#endif /* end of --- */
1890 +
1891 +#define DRV_NAME "mtk-sd"
1892 +
1893 +#define HOST_MAX_NUM (1) /* +/- by chhung */
1894 +
1895 +#if defined (CONFIG_SOC_MT7620)
1896 +#define HOST_MAX_MCLK (48000000) /* +/- by chhung */
1897 +#elif defined (CONFIG_SOC_MT7621)
1898 +#define HOST_MAX_MCLK (50000000) /* +/- by chhung */
1899 +#endif
1900 +#define HOST_MIN_MCLK (260000)
1901 +
1902 +#define HOST_MAX_BLKSZ (2048)
1903 +
1904 +#define MSDC_OCR_AVAIL (MMC_VDD_28_29 | MMC_VDD_29_30 | MMC_VDD_30_31 | MMC_VDD_31_32 | MMC_VDD_32_33)
1905 +
1906 +#define GPIO_PULL_DOWN (0)
1907 +#define GPIO_PULL_UP (1)
1908 +
1909 +#if 0 /* --- by chhung */
1910 +#define MSDC_CLKSRC_REG (0xf100000C)
1911 +#define PDN_REG (0xF1000010)
1912 +#endif /* end of --- */
1913 +
1914 +#define DEFAULT_DEBOUNCE (8) /* 8 cycles */
1915 +#define DEFAULT_DTOC (40) /* data timeout counter. 65536x40 sclk. */
1916 +
1917 +#define CMD_TIMEOUT (HZ/10) /* 100ms */
1918 +#define DAT_TIMEOUT (HZ/2 * 5) /* 500ms x5 */
1919 +
1920 +#define MAX_DMA_CNT (64 * 1024 - 512) /* a single transaction for WIFI may be 50K*/
1921 +
1922 +#define MAX_GPD_NUM (1 + 1) /* one null gpd */
1923 +#define MAX_BD_NUM (1024)
1924 +#define MAX_BD_PER_GPD (MAX_BD_NUM)
1925 +
1926 +#define MAX_HW_SGMTS (MAX_BD_NUM)
1927 +#define MAX_PHY_SGMTS (MAX_BD_NUM)
1928 +#define MAX_SGMT_SZ (MAX_DMA_CNT)
1929 +#define MAX_REQ_SZ (MAX_SGMT_SZ * 8)
1930 +
1931 +#ifdef MT6575_SD_DEBUG
1932 +static struct msdc_regs *msdc_reg[HOST_MAX_NUM];
1933 +#endif
1934 +
1935 +//=================================
1936 +#define PERI_MSDC0_PDN (15)
1937 +//#define PERI_MSDC1_PDN (16)
1938 +//#define PERI_MSDC2_PDN (17)
1939 +//#define PERI_MSDC3_PDN (18)
1940 +
1941 +struct msdc_host *msdc_6575_host[] = {NULL,NULL,NULL,NULL};
1942 +#if 0 /* --- by chhung */
1943 +/* gate means clock power down */
1944 +static int g_clk_gate = 0;
1945 +#define msdc_gate_clock(id) \
1946 + do { \
1947 + g_clk_gate &= ~(1 << ((id) + PERI_MSDC0_PDN)); \
1948 + } while(0)
1949 +/* not like power down register. 1 means clock on. */
1950 +#define msdc_ungate_clock(id) \
1951 + do { \
1952 + g_clk_gate |= 1 << ((id) + PERI_MSDC0_PDN); \
1953 + } while(0)
1954 +
1955 +// do we need sync object or not
1956 +void msdc_clk_status(int * status)
1957 +{
1958 + *status = g_clk_gate;
1959 +}
1960 +#endif /* end of --- */
1961 +
1962 +/* +++ by chhung */
1963 +struct msdc_hw msdc0_hw = {
1964 + .clk_src = 0,
1965 + .cmd_edge = MSDC_SMPL_FALLING,
1966 + .data_edge = MSDC_SMPL_FALLING,
1967 + .clk_drv = 4,
1968 + .cmd_drv = 4,
1969 + .dat_drv = 4,
1970 + .data_pins = 4,
1971 + .data_offset = 0,
1972 + .flags = MSDC_SYS_SUSPEND | MSDC_WP_PIN_EN | MSDC_CD_PIN_EN | MSDC_REMOVABLE | MSDC_HIGHSPEED,
1973 +// .flags = MSDC_SYS_SUSPEND | MSDC_WP_PIN_EN | MSDC_CD_PIN_EN | MSDC_REMOVABLE,
1974 +};
1975 +
1976 +static struct resource mtk_sd_resources[] = {
1977 + [0] = {
1978 + .start = RALINK_MSDC_BASE,
1979 + .end = RALINK_MSDC_BASE+0x3fff,
1980 + .flags = IORESOURCE_MEM,
1981 + },
1982 + [1] = {
1983 + .start = IRQ_SDC, /*FIXME*/
1984 + .end = IRQ_SDC, /*FIXME*/
1985 + .flags = IORESOURCE_IRQ,
1986 + },
1987 +};
1988 +
1989 +static struct platform_device mtk_sd_device = {
1990 + .name = "mtk-sd",
1991 + .id = 0,
1992 + .num_resources = ARRAY_SIZE(mtk_sd_resources),
1993 + .resource = mtk_sd_resources,
1994 +};
1995 +/* end of +++ */
1996 +
1997 +static int msdc_rsp[] = {
1998 + 0, /* RESP_NONE */
1999 + 1, /* RESP_R1 */
2000 + 2, /* RESP_R2 */
2001 + 3, /* RESP_R3 */
2002 + 4, /* RESP_R4 */
2003 + 1, /* RESP_R5 */
2004 + 1, /* RESP_R6 */
2005 + 1, /* RESP_R7 */
2006 + 7, /* RESP_R1b */
2007 +};
2008 +
2009 +/* For Inhanced DMA */
2010 +#define msdc_init_gpd_ex(gpd,extlen,cmd,arg,blknum) \
2011 + do { \
2012 + ((gpd_t*)gpd)->extlen = extlen; \
2013 + ((gpd_t*)gpd)->cmd = cmd; \
2014 + ((gpd_t*)gpd)->arg = arg; \
2015 + ((gpd_t*)gpd)->blknum = blknum; \
2016 + }while(0)
2017 +
2018 +#define msdc_init_bd(bd, blkpad, dwpad, dptr, dlen) \
2019 + do { \
2020 + BUG_ON(dlen > 0xFFFFUL); \
2021 + ((bd_t*)bd)->blkpad = blkpad; \
2022 + ((bd_t*)bd)->dwpad = dwpad; \
2023 + ((bd_t*)bd)->ptr = (void*)dptr; \
2024 + ((bd_t*)bd)->buflen = dlen; \
2025 + }while(0)
2026 +
2027 +#define msdc_txfifocnt() ((sdr_read32(MSDC_FIFOCS) & MSDC_FIFOCS_TXCNT) >> 16)
2028 +#define msdc_rxfifocnt() ((sdr_read32(MSDC_FIFOCS) & MSDC_FIFOCS_RXCNT) >> 0)
2029 +#define msdc_fifo_write32(v) sdr_write32(MSDC_TXDATA, (v))
2030 +#define msdc_fifo_write8(v) sdr_write8(MSDC_TXDATA, (v))
2031 +#define msdc_fifo_read32() sdr_read32(MSDC_RXDATA)
2032 +#define msdc_fifo_read8() sdr_read8(MSDC_RXDATA)
2033 +
2034 +
2035 +#define msdc_dma_on() sdr_clr_bits(MSDC_CFG, MSDC_CFG_PIO)
2036 +#define msdc_dma_off() sdr_set_bits(MSDC_CFG, MSDC_CFG_PIO)
2037 +
2038 +#define msdc_retry(expr,retry,cnt) \
2039 + do { \
2040 + int backup = cnt; \
2041 + while (retry) { \
2042 + if (!(expr)) break; \
2043 + if (cnt-- == 0) { \
2044 + retry--; mdelay(1); cnt = backup; \
2045 + } \
2046 + } \
2047 + WARN_ON(retry == 0); \
2048 + } while(0)
2049 +
2050 +#if 0 /* --- by chhung */
2051 +#define msdc_reset() \
2052 + do { \
2053 + int retry = 3, cnt = 1000; \
2054 + sdr_set_bits(MSDC_CFG, MSDC_CFG_RST); \
2055 + dsb(); \
2056 + msdc_retry(sdr_read32(MSDC_CFG) & MSDC_CFG_RST, retry, cnt); \
2057 + } while(0)
2058 +#else
2059 +#define msdc_reset() \
2060 + do { \
2061 + int retry = 3, cnt = 1000; \
2062 + sdr_set_bits(MSDC_CFG, MSDC_CFG_RST); \
2063 + msdc_retry(sdr_read32(MSDC_CFG) & MSDC_CFG_RST, retry, cnt); \
2064 + } while(0)
2065 +#endif /* end of +/- */
2066 +
2067 +#define msdc_clr_int() \
2068 + do { \
2069 + volatile u32 val = sdr_read32(MSDC_INT); \
2070 + sdr_write32(MSDC_INT, val); \
2071 + } while(0)
2072 +
2073 +#define msdc_clr_fifo() \
2074 + do { \
2075 + int retry = 3, cnt = 1000; \
2076 + sdr_set_bits(MSDC_FIFOCS, MSDC_FIFOCS_CLR); \
2077 + msdc_retry(sdr_read32(MSDC_FIFOCS) & MSDC_FIFOCS_CLR, retry, cnt); \
2078 + } while(0)
2079 +
2080 +#define msdc_irq_save(val) \
2081 + do { \
2082 + val = sdr_read32(MSDC_INTEN); \
2083 + sdr_clr_bits(MSDC_INTEN, val); \
2084 + } while(0)
2085 +
2086 +#define msdc_irq_restore(val) \
2087 + do { \
2088 + sdr_set_bits(MSDC_INTEN, val); \
2089 + } while(0)
2090 +
2091 +/* clock source for host: global */
2092 +#if defined (CONFIG_SOC_MT7620)
2093 +static u32 hclks[] = {48000000}; /* +/- by chhung */
2094 +#elif defined (CONFIG_SOC_MT7621)
2095 +static u32 hclks[] = {50000000}; /* +/- by chhung */
2096 +#endif
2097 +
2098 +//============================================
2099 +// the power for msdc host controller: global
2100 +// always keep the VMC on.
2101 +//============================================
2102 +#define msdc_vcore_on(host) \
2103 + do { \
2104 + INIT_MSG("[+]VMC ref. count<%d>", ++host->pwr_ref); \
2105 + (void)hwPowerOn(MT65XX_POWER_LDO_VMC, VOL_3300, "SD"); \
2106 + } while (0)
2107 +#define msdc_vcore_off(host) \
2108 + do { \
2109 + INIT_MSG("[-]VMC ref. count<%d>", --host->pwr_ref); \
2110 + (void)hwPowerDown(MT65XX_POWER_LDO_VMC, "SD"); \
2111 + } while (0)
2112 +
2113 +//====================================
2114 +// the vdd output for card: global
2115 +// always keep the VMCH on.
2116 +//====================================
2117 +#define msdc_vdd_on(host) \
2118 + do { \
2119 + (void)hwPowerOn(MT65XX_POWER_LDO_VMCH, VOL_3300, "SD"); \
2120 + } while (0)
2121 +#define msdc_vdd_off(host) \
2122 + do { \
2123 + (void)hwPowerDown(MT65XX_POWER_LDO_VMCH, "SD"); \
2124 + } while (0)
2125 +
2126 +#define sdc_is_busy() (sdr_read32(SDC_STS) & SDC_STS_SDCBUSY)
2127 +#define sdc_is_cmd_busy() (sdr_read32(SDC_STS) & SDC_STS_CMDBUSY)
2128 +
2129 +#define sdc_send_cmd(cmd,arg) \
2130 + do { \
2131 + sdr_write32(SDC_ARG, (arg)); \
2132 + sdr_write32(SDC_CMD, (cmd)); \
2133 + } while(0)
2134 +
2135 +// can modify to read h/w register.
2136 +//#define is_card_present(h) ((sdr_read32(MSDC_PS) & MSDC_PS_CDSTS) ? 0 : 1);
2137 +#define is_card_present(h) (((struct msdc_host*)(h))->card_inserted)
2138 +
2139 +/* +++ by chhung */
2140 +#ifndef __ASSEMBLY__
2141 +#define PHYSADDR(a) (((unsigned long)(a)) & 0x1fffffff)
2142 +#else
2143 +#define PHYSADDR(a) ((a) & 0x1fffffff)
2144 +#endif
2145 +/* end of +++ */
2146 +static unsigned int msdc_do_command(struct msdc_host *host,
2147 + struct mmc_command *cmd,
2148 + int tune,
2149 + unsigned long timeout);
2150 +
2151 +static int msdc_tune_cmdrsp(struct msdc_host*host,struct mmc_command *cmd);
2152 +
2153 +#ifdef MT6575_SD_DEBUG
2154 +static void msdc_dump_card_status(struct msdc_host *host, u32 status)
2155 +{
2156 + static char *state[] = {
2157 + "Idle", /* 0 */
2158 + "Ready", /* 1 */
2159 + "Ident", /* 2 */
2160 + "Stby", /* 3 */
2161 + "Tran", /* 4 */
2162 + "Data", /* 5 */
2163 + "Rcv", /* 6 */
2164 + "Prg", /* 7 */
2165 + "Dis", /* 8 */
2166 + "Reserved", /* 9 */
2167 + "Reserved", /* 10 */
2168 + "Reserved", /* 11 */
2169 + "Reserved", /* 12 */
2170 + "Reserved", /* 13 */
2171 + "Reserved", /* 14 */
2172 + "I/O mode", /* 15 */
2173 + };
2174 + if (status & R1_OUT_OF_RANGE)
2175 + N_MSG(RSP, "[CARD_STATUS] Out of Range");
2176 + if (status & R1_ADDRESS_ERROR)
2177 + N_MSG(RSP, "[CARD_STATUS] Address Error");
2178 + if (status & R1_BLOCK_LEN_ERROR)
2179 + N_MSG(RSP, "[CARD_STATUS] Block Len Error");
2180 + if (status & R1_ERASE_SEQ_ERROR)
2181 + N_MSG(RSP, "[CARD_STATUS] Erase Seq Error");
2182 + if (status & R1_ERASE_PARAM)
2183 + N_MSG(RSP, "[CARD_STATUS] Erase Param");
2184 + if (status & R1_WP_VIOLATION)
2185 + N_MSG(RSP, "[CARD_STATUS] WP Violation");
2186 + if (status & R1_CARD_IS_LOCKED)
2187 + N_MSG(RSP, "[CARD_STATUS] Card is Locked");
2188 + if (status & R1_LOCK_UNLOCK_FAILED)
2189 + N_MSG(RSP, "[CARD_STATUS] Lock/Unlock Failed");
2190 + if (status & R1_COM_CRC_ERROR)
2191 + N_MSG(RSP, "[CARD_STATUS] Command CRC Error");
2192 + if (status & R1_ILLEGAL_COMMAND)
2193 + N_MSG(RSP, "[CARD_STATUS] Illegal Command");
2194 + if (status & R1_CARD_ECC_FAILED)
2195 + N_MSG(RSP, "[CARD_STATUS] Card ECC Failed");
2196 + if (status & R1_CC_ERROR)
2197 + N_MSG(RSP, "[CARD_STATUS] CC Error");
2198 + if (status & R1_ERROR)
2199 + N_MSG(RSP, "[CARD_STATUS] Error");
2200 + if (status & R1_UNDERRUN)
2201 + N_MSG(RSP, "[CARD_STATUS] Underrun");
2202 + if (status & R1_OVERRUN)
2203 + N_MSG(RSP, "[CARD_STATUS] Overrun");
2204 + if (status & R1_CID_CSD_OVERWRITE)
2205 + N_MSG(RSP, "[CARD_STATUS] CID/CSD Overwrite");
2206 + if (status & R1_WP_ERASE_SKIP)
2207 + N_MSG(RSP, "[CARD_STATUS] WP Eraser Skip");
2208 + if (status & R1_CARD_ECC_DISABLED)
2209 + N_MSG(RSP, "[CARD_STATUS] Card ECC Disabled");
2210 + if (status & R1_ERASE_RESET)
2211 + N_MSG(RSP, "[CARD_STATUS] Erase Reset");
2212 + if (status & R1_READY_FOR_DATA)
2213 + N_MSG(RSP, "[CARD_STATUS] Ready for Data");
2214 + if (status & R1_SWITCH_ERROR)
2215 + N_MSG(RSP, "[CARD_STATUS] Switch error");
2216 + if (status & R1_APP_CMD)
2217 + N_MSG(RSP, "[CARD_STATUS] App Command");
2218 +
2219 + N_MSG(RSP, "[CARD_STATUS] '%s' State", state[R1_CURRENT_STATE(status)]);
2220 +}
2221 +
2222 +static void msdc_dump_ocr_reg(struct msdc_host *host, u32 resp)
2223 +{
2224 + if (resp & (1 << 7))
2225 + N_MSG(RSP, "[OCR] Low Voltage Range");
2226 + if (resp & (1 << 15))
2227 + N_MSG(RSP, "[OCR] 2.7-2.8 volt");
2228 + if (resp & (1 << 16))
2229 + N_MSG(RSP, "[OCR] 2.8-2.9 volt");
2230 + if (resp & (1 << 17))
2231 + N_MSG(RSP, "[OCR] 2.9-3.0 volt");
2232 + if (resp & (1 << 18))
2233 + N_MSG(RSP, "[OCR] 3.0-3.1 volt");
2234 + if (resp & (1 << 19))
2235 + N_MSG(RSP, "[OCR] 3.1-3.2 volt");
2236 + if (resp & (1 << 20))
2237 + N_MSG(RSP, "[OCR] 3.2-3.3 volt");
2238 + if (resp & (1 << 21))
2239 + N_MSG(RSP, "[OCR] 3.3-3.4 volt");
2240 + if (resp & (1 << 22))
2241 + N_MSG(RSP, "[OCR] 3.4-3.5 volt");
2242 + if (resp & (1 << 23))
2243 + N_MSG(RSP, "[OCR] 3.5-3.6 volt");
2244 + if (resp & (1 << 24))
2245 + N_MSG(RSP, "[OCR] Switching to 1.8V Accepted (S18A)");
2246 + if (resp & (1 << 30))
2247 + N_MSG(RSP, "[OCR] Card Capacity Status (CCS)");
2248 + if (resp & (1 << 31))
2249 + N_MSG(RSP, "[OCR] Card Power Up Status (Idle)");
2250 + else
2251 + N_MSG(RSP, "[OCR] Card Power Up Status (Busy)");
2252 +}
2253 +
2254 +static void msdc_dump_rca_resp(struct msdc_host *host, u32 resp)
2255 +{
2256 + u32 status = (((resp >> 15) & 0x1) << 23) |
2257 + (((resp >> 14) & 0x1) << 22) |
2258 + (((resp >> 13) & 0x1) << 19) |
2259 + (resp & 0x1fff);
2260 +
2261 + N_MSG(RSP, "[RCA] 0x%.4x", resp >> 16);
2262 + msdc_dump_card_status(host, status);
2263 +}
2264 +
2265 +static void msdc_dump_io_resp(struct msdc_host *host, u32 resp)
2266 +{
2267 + u32 flags = (resp >> 8) & 0xFF;
2268 + char *state[] = {"DIS", "CMD", "TRN", "RFU"};
2269 +
2270 + if (flags & (1 << 7))
2271 + N_MSG(RSP, "[IO] COM_CRC_ERR");
2272 + if (flags & (1 << 6))
2273 + N_MSG(RSP, "[IO] Illgal command");
2274 + if (flags & (1 << 3))
2275 + N_MSG(RSP, "[IO] Error");
2276 + if (flags & (1 << 2))
2277 + N_MSG(RSP, "[IO] RFU");
2278 + if (flags & (1 << 1))
2279 + N_MSG(RSP, "[IO] Function number error");
2280 + if (flags & (1 << 0))
2281 + N_MSG(RSP, "[IO] Out of range");
2282 +
2283 + N_MSG(RSP, "[IO] State: %s, Data:0x%x", state[(resp >> 12) & 0x3], resp & 0xFF);
2284 +}
2285 +#endif
2286 +
2287 +static void msdc_set_timeout(struct msdc_host *host, u32 ns, u32 clks)
2288 +{
2289 + u32 base = host->base;
2290 + u32 timeout, clk_ns;
2291 +
2292 + host->timeout_ns = ns;
2293 + host->timeout_clks = clks;
2294 +
2295 + clk_ns = 1000000000UL / host->sclk;
2296 + timeout = ns / clk_ns + clks;
2297 + timeout = timeout >> 16; /* in 65536 sclk cycle unit */
2298 + timeout = timeout > 1 ? timeout - 1 : 0;
2299 + timeout = timeout > 255 ? 255 : timeout;
2300 +
2301 + sdr_set_field(SDC_CFG, SDC_CFG_DTOC, timeout);
2302 +
2303 + N_MSG(OPS, "Set read data timeout: %dns %dclks -> %d x 65536 cycles",
2304 + ns, clks, timeout + 1);
2305 +}
2306 +
2307 +/* msdc_eirq_sdio() will be called when EIRQ(for WIFI) */
2308 +static void msdc_eirq_sdio(void *data)
2309 +{
2310 + struct msdc_host *host = (struct msdc_host *)data;
2311 +
2312 + N_MSG(INT, "SDIO EINT");
2313 +
2314 + mmc_signal_sdio_irq(host->mmc);
2315 +}
2316 +
2317 +/* msdc_eirq_cd will not be used! We not using EINT for card detection. */
2318 +static void msdc_eirq_cd(void *data)
2319 +{
2320 + struct msdc_host *host = (struct msdc_host *)data;
2321 +
2322 + N_MSG(INT, "CD EINT");
2323 +
2324 +#if 0
2325 + tasklet_hi_schedule(&host->card_tasklet);
2326 +#else
2327 + schedule_delayed_work(&host->card_delaywork, HZ);
2328 +#endif
2329 +}
2330 +
2331 +#if 0
2332 +static void msdc_tasklet_card(unsigned long arg)
2333 +{
2334 + struct msdc_host *host = (struct msdc_host *)arg;
2335 +#else
2336 +static void msdc_tasklet_card(struct work_struct *work)
2337 +{
2338 + struct msdc_host *host = (struct msdc_host *)container_of(work,
2339 + struct msdc_host, card_delaywork.work);
2340 +#endif
2341 + struct msdc_hw *hw = host->hw;
2342 + u32 base = host->base;
2343 + u32 inserted;
2344 + u32 status = 0;
2345 + //u32 change = 0;
2346 +
2347 + spin_lock(&host->lock);
2348 +
2349 + if (hw->get_cd_status) { // NULL
2350 + inserted = hw->get_cd_status();
2351 + } else {
2352 + status = sdr_read32(MSDC_PS);
2353 + inserted = (status & MSDC_PS_CDSTS) ? 0 : 1;
2354 + }
2355 +
2356 +#if 0
2357 + change = host->card_inserted ^ inserted;
2358 + host->card_inserted = inserted;
2359 +
2360 + if (change && !host->suspend) {
2361 + if (inserted) {
2362 + host->mmc->f_max = HOST_MAX_MCLK; // work around
2363 + }
2364 + mmc_detect_change(host->mmc, msecs_to_jiffies(20));
2365 + }
2366 +#else /* Make sure: handle the last interrupt */
2367 + host->card_inserted = inserted;
2368 +
2369 + if (!host->suspend) {
2370 + host->mmc->f_max = HOST_MAX_MCLK;
2371 + mmc_detect_change(host->mmc, msecs_to_jiffies(20));
2372 + }
2373 +
2374 + IRQ_MSG("card found<%s>", inserted ? "inserted" : "removed");
2375 +#endif
2376 +
2377 + spin_unlock(&host->lock);
2378 +}
2379 +
2380 +#if 0 /* --- by chhung */
2381 +/* For E2 only */
2382 +static u8 clk_src_bit[4] = {
2383 + 0, 3, 5, 7
2384 +};
2385 +
2386 +static void msdc_select_clksrc(struct msdc_host* host, unsigned char clksrc)
2387 +{
2388 + u32 val;
2389 + u32 base = host->base;
2390 +
2391 + BUG_ON(clksrc > 3);
2392 + INIT_MSG("set clock source to <%d>", clksrc);
2393 +
2394 + val = sdr_read32(MSDC_CLKSRC_REG);
2395 + if (sdr_read32(MSDC_ECO_VER) >= 4) {
2396 + val &= ~(0x3 << clk_src_bit[host->id]);
2397 + val |= clksrc << clk_src_bit[host->id];
2398 + } else {
2399 + val &= ~0x3; val |= clksrc;
2400 + }
2401 + sdr_write32(MSDC_CLKSRC_REG, val);
2402 +
2403 + host->hclk = hclks[clksrc];
2404 + host->hw->clk_src = clksrc;
2405 +}
2406 +#endif /* end of --- */
2407 +
2408 +static void msdc_set_mclk(struct msdc_host *host, int ddr, unsigned int hz)
2409 +{
2410 + //struct msdc_hw *hw = host->hw;
2411 + u32 base = host->base;
2412 + u32 mode;
2413 + u32 flags;
2414 + u32 div;
2415 + u32 sclk;
2416 + u32 hclk = host->hclk;
2417 + //u8 clksrc = hw->clk_src;
2418 +
2419 + if (!hz) { // set mmc system clock to 0 ?
2420 + ERR_MSG("set mclk to 0!!!");
2421 + msdc_reset();
2422 + return;
2423 + }
2424 +
2425 + msdc_irq_save(flags);
2426 +
2427 +#if defined (CONFIG_MT7621_FPGA) || defined (CONFIG_MT7628_FPGA)
2428 + mode = 0x0; /* use divisor */
2429 + if (hz >= (hclk >> 1)) {
2430 + div = 0; /* mean div = 1/2 */
2431 + sclk = hclk >> 1; /* sclk = clk / 2 */
2432 + } else {
2433 + div = (hclk + ((hz << 2) - 1)) / (hz << 2);
2434 + sclk = (hclk >> 2) / div;
2435 + }
2436 +#else
2437 + if (ddr) {
2438 + mode = 0x2; /* ddr mode and use divisor */
2439 + if (hz >= (hclk >> 2)) {
2440 + div = 1; /* mean div = 1/4 */
2441 + sclk = hclk >> 2; /* sclk = clk / 4 */
2442 + } else {
2443 + div = (hclk + ((hz << 2) - 1)) / (hz << 2);
2444 + sclk = (hclk >> 2) / div;
2445 + }
2446 + } else if (hz >= hclk) { /* bug fix */
2447 + mode = 0x1; /* no divisor and divisor is ignored */
2448 + div = 0;
2449 + sclk = hclk;
2450 + } else {
2451 + mode = 0x0; /* use divisor */
2452 + if (hz >= (hclk >> 1)) {
2453 + div = 0; /* mean div = 1/2 */
2454 + sclk = hclk >> 1; /* sclk = clk / 2 */
2455 + } else {
2456 + div = (hclk + ((hz << 2) - 1)) / (hz << 2);
2457 + sclk = (hclk >> 2) / div;
2458 + }
2459 + }
2460 +#endif
2461 + /* set clock mode and divisor */
2462 + sdr_set_field(MSDC_CFG, MSDC_CFG_CKMOD, mode);
2463 + sdr_set_field(MSDC_CFG, MSDC_CFG_CKDIV, div);
2464 +
2465 + /* wait clock stable */
2466 + while (!(sdr_read32(MSDC_CFG) & MSDC_CFG_CKSTB));
2467 +
2468 + host->sclk = sclk;
2469 + host->mclk = hz;
2470 + msdc_set_timeout(host, host->timeout_ns, host->timeout_clks); // need?
2471 +
2472 + INIT_MSG("================");
2473 + INIT_MSG("!!! Set<%dKHz> Source<%dKHz> -> sclk<%dKHz>", hz/1000, hclk/1000, sclk/1000);
2474 + INIT_MSG("================");
2475 +
2476 + msdc_irq_restore(flags);
2477 +}
2478 +
2479 +/* Fix me. when need to abort */
2480 +static void msdc_abort_data(struct msdc_host *host)
2481 +{
2482 + u32 base = host->base;
2483 + struct mmc_command *stop = host->mrq->stop;
2484 +
2485 + ERR_MSG("Need to Abort. dma<%d>", host->dma_xfer);
2486 +
2487 + msdc_reset();
2488 + msdc_clr_fifo();
2489 + msdc_clr_int();
2490 +
2491 + // need to check FIFO count 0 ?
2492 +
2493 + if (stop) { /* try to stop, but may not success */
2494 + ERR_MSG("stop when abort CMD<%d>", stop->opcode);
2495 + (void)msdc_do_command(host, stop, 0, CMD_TIMEOUT);
2496 + }
2497 +
2498 + //if (host->mclk >= 25000000) {
2499 + // msdc_set_mclk(host, 0, host->mclk >> 1);
2500 + //}
2501 +}
2502 +
2503 +#if 0 /* --- by chhung */
2504 +static void msdc_pin_config(struct msdc_host *host, int mode)
2505 +{
2506 + struct msdc_hw *hw = host->hw;
2507 + u32 base = host->base;
2508 + int pull = (mode == MSDC_PIN_PULL_UP) ? GPIO_PULL_UP : GPIO_PULL_DOWN;
2509 +
2510 + /* Config WP pin */
2511 + if (hw->flags & MSDC_WP_PIN_EN) {
2512 + if (hw->config_gpio_pin) /* NULL */
2513 + hw->config_gpio_pin(MSDC_WP_PIN, pull);
2514 + }
2515 +
2516 + switch (mode) {
2517 + case MSDC_PIN_PULL_UP:
2518 + //sdr_set_field(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKPU, 1); /* Check & FIXME */
2519 + //sdr_set_field(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKPD, 0); /* Check & FIXME */
2520 + sdr_set_field(MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDPU, 1);
2521 + sdr_set_field(MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDPD, 0);
2522 + sdr_set_field(MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATPU, 1);
2523 + sdr_set_field(MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATPD, 0);
2524 + break;
2525 + case MSDC_PIN_PULL_DOWN:
2526 + //sdr_set_field(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKPU, 0); /* Check & FIXME */
2527 + //sdr_set_field(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKPD, 1); /* Check & FIXME */
2528 + sdr_set_field(MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDPU, 0);
2529 + sdr_set_field(MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDPD, 1);
2530 + sdr_set_field(MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATPU, 0);
2531 + sdr_set_field(MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATPD, 1);
2532 + break;
2533 + case MSDC_PIN_PULL_NONE:
2534 + default:
2535 + //sdr_set_field(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKPU, 0); /* Check & FIXME */
2536 + //sdr_set_field(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKPD, 0); /* Check & FIXME */
2537 + sdr_set_field(MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDPU, 0);
2538 + sdr_set_field(MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDPD, 0);
2539 + sdr_set_field(MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATPU, 0);
2540 + sdr_set_field(MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATPD, 0);
2541 + break;
2542 + }
2543 +
2544 + N_MSG(CFG, "Pins mode(%d), down(%d), up(%d)",
2545 + mode, MSDC_PIN_PULL_DOWN, MSDC_PIN_PULL_UP);
2546 +}
2547 +
2548 +void msdc_pin_reset(struct msdc_host *host, int mode)
2549 +{
2550 + struct msdc_hw *hw = (struct msdc_hw *)host->hw;
2551 + u32 base = host->base;
2552 + int pull = (mode == MSDC_PIN_PULL_UP) ? GPIO_PULL_UP : GPIO_PULL_DOWN;
2553 +
2554 + /* Config reset pin */
2555 + if (hw->flags & MSDC_RST_PIN_EN) {
2556 + if (hw->config_gpio_pin) /* NULL */
2557 + hw->config_gpio_pin(MSDC_RST_PIN, pull);
2558 +
2559 + if (mode == MSDC_PIN_PULL_UP) {
2560 + sdr_clr_bits(EMMC_IOCON, EMMC_IOCON_BOOTRST);
2561 + } else {
2562 + sdr_set_bits(EMMC_IOCON, EMMC_IOCON_BOOTRST);
2563 + }
2564 + }
2565 +}
2566 +
2567 +static void msdc_core_power(struct msdc_host *host, int on)
2568 +{
2569 + N_MSG(CFG, "Turn %s %s power (copower: %d -> %d)",
2570 + on ? "on" : "off", "core", host->core_power, on);
2571 +
2572 + if (on && host->core_power == 0) {
2573 + msdc_vcore_on(host);
2574 + host->core_power = 1;
2575 + msleep(1);
2576 + } else if (!on && host->core_power == 1) {
2577 + msdc_vcore_off(host);
2578 + host->core_power = 0;
2579 + msleep(1);
2580 + }
2581 +}
2582 +
2583 +static void msdc_host_power(struct msdc_host *host, int on)
2584 +{
2585 + N_MSG(CFG, "Turn %s %s power ", on ? "on" : "off", "host");
2586 +
2587 + if (on) {
2588 + //msdc_core_power(host, 1); // need do card detection.
2589 + msdc_pin_reset(host, MSDC_PIN_PULL_UP);
2590 + } else {
2591 + msdc_pin_reset(host, MSDC_PIN_PULL_DOWN);
2592 + //msdc_core_power(host, 0);
2593 + }
2594 +}
2595 +
2596 +static void msdc_card_power(struct msdc_host *host, int on)
2597 +{
2598 + N_MSG(CFG, "Turn %s %s power ", on ? "on" : "off", "card");
2599 +
2600 + if (on) {
2601 + msdc_pin_config(host, MSDC_PIN_PULL_UP);
2602 + if (host->hw->ext_power_on) {
2603 + host->hw->ext_power_on();
2604 + } else {
2605 + //msdc_vdd_on(host); // need todo card detection.
2606 + }
2607 + msleep(1);
2608 + } else {
2609 + if (host->hw->ext_power_off) {
2610 + host->hw->ext_power_off();
2611 + } else {
2612 + //msdc_vdd_off(host);
2613 + }
2614 + msdc_pin_config(host, MSDC_PIN_PULL_DOWN);
2615 + msleep(1);
2616 + }
2617 +}
2618 +
2619 +static void msdc_set_power_mode(struct msdc_host *host, u8 mode)
2620 +{
2621 + N_MSG(CFG, "Set power mode(%d)", mode);
2622 +
2623 + if (host->power_mode == MMC_POWER_OFF && mode != MMC_POWER_OFF) {
2624 + msdc_host_power(host, 1);
2625 + msdc_card_power(host, 1);
2626 + } else if (host->power_mode != MMC_POWER_OFF && mode == MMC_POWER_OFF) {
2627 + msdc_card_power(host, 0);
2628 + msdc_host_power(host, 0);
2629 + }
2630 + host->power_mode = mode;
2631 +}
2632 +#endif /* end of --- */
2633 +
2634 +#ifdef CONFIG_PM
2635 +/*
2636 + register as callback function of WIFI(combo_sdio_register_pm) .
2637 + can called by msdc_drv_suspend/resume too.
2638 +*/
2639 +static void msdc_pm(pm_message_t state, void *data)
2640 +{
2641 + struct msdc_host *host = (struct msdc_host *)data;
2642 + int evt = state.event;
2643 +
2644 + if (evt == PM_EVENT_USER_RESUME || evt == PM_EVENT_USER_SUSPEND) {
2645 + INIT_MSG("USR_%s: suspend<%d> power<%d>",
2646 + evt == PM_EVENT_USER_RESUME ? "EVENT_USER_RESUME" : "EVENT_USER_SUSPEND",
2647 + host->suspend, host->power_mode);
2648 + }
2649 +
2650 + if (evt == PM_EVENT_SUSPEND || evt == PM_EVENT_USER_SUSPEND) {
2651 + if (host->suspend) /* already suspend */ /* default 0*/
2652 + return;
2653 +
2654 + /* for memory card. already power off by mmc */
2655 + if (evt == PM_EVENT_SUSPEND && host->power_mode == MMC_POWER_OFF)
2656 + return;
2657 +
2658 + host->suspend = 1;
2659 + host->pm_state = state; /* default PMSG_RESUME */
2660 +
2661 + INIT_MSG("%s Suspend", evt == PM_EVENT_SUSPEND ? "PM" : "USR");
2662 + if(host->hw->flags & MSDC_SYS_SUSPEND) /* set for card */
2663 + (void)mmc_suspend_host(host->mmc);
2664 + else {
2665 + // host->mmc->pm_flags |= MMC_PM_IGNORE_PM_NOTIFY; /* just for double confirm */ /* --- by chhung */
2666 + mmc_remove_host(host->mmc);
2667 + }
2668 + } else if (evt == PM_EVENT_RESUME || evt == PM_EVENT_USER_RESUME) {
2669 + if (!host->suspend){
2670 + //ERR_MSG("warning: already resume");
2671 + return;
2672 + }
2673 +
2674 + /* No PM resume when USR suspend */
2675 + if (evt == PM_EVENT_RESUME && host->pm_state.event == PM_EVENT_USER_SUSPEND) {
2676 + ERR_MSG("PM Resume when in USR Suspend"); /* won't happen. */
2677 + return;
2678 + }
2679 +
2680 + host->suspend = 0;
2681 + host->pm_state = state;
2682 +
2683 + INIT_MSG("%s Resume", evt == PM_EVENT_RESUME ? "PM" : "USR");
2684 + if(host->hw->flags & MSDC_SYS_SUSPEND) { /* will not set for WIFI */
2685 + (void)mmc_resume_host(host->mmc);
2686 + }
2687 + else {
2688 + // host->mmc->pm_flags |= MMC_PM_IGNORE_PM_NOTIFY; /* --- by chhung */
2689 + mmc_add_host(host->mmc);
2690 + }
2691 + }
2692 +}
2693 +#endif
2694 +
2695 +/*--------------------------------------------------------------------------*/
2696 +/* mmc_host_ops members */
2697 +/*--------------------------------------------------------------------------*/
2698 +static unsigned int msdc_command_start(struct msdc_host *host,
2699 + struct mmc_command *cmd,
2700 + int tune, /* not used */
2701 + unsigned long timeout)
2702 +{
2703 + u32 base = host->base;
2704 + u32 opcode = cmd->opcode;
2705 + u32 rawcmd;
2706 + u32 wints = MSDC_INT_CMDRDY | MSDC_INT_RSPCRCERR | MSDC_INT_CMDTMO |
2707 + MSDC_INT_ACMDRDY | MSDC_INT_ACMDCRCERR | MSDC_INT_ACMDTMO |
2708 + MSDC_INT_ACMD19_DONE;
2709 +
2710 + u32 resp;
2711 + unsigned long tmo;
2712 +
2713 + /* Protocol layer does not provide response type, but our hardware needs
2714 + * to know exact type, not just size!
2715 + */
2716 + if (opcode == MMC_SEND_OP_COND || opcode == SD_APP_OP_COND)
2717 + resp = RESP_R3;
2718 + else if (opcode == MMC_SET_RELATIVE_ADDR || opcode == SD_SEND_RELATIVE_ADDR)
2719 + resp = (mmc_cmd_type(cmd) == MMC_CMD_BCR) ? RESP_R6 : RESP_R1;
2720 + else if (opcode == MMC_FAST_IO)
2721 + resp = RESP_R4;
2722 + else if (opcode == MMC_GO_IRQ_STATE)
2723 + resp = RESP_R5;
2724 + else if (opcode == MMC_SELECT_CARD)
2725 + resp = (cmd->arg != 0) ? RESP_R1B : RESP_NONE;
2726 + else if (opcode == SD_IO_RW_DIRECT || opcode == SD_IO_RW_EXTENDED)
2727 + resp = RESP_R1; /* SDIO workaround. */
2728 + else if (opcode == SD_SEND_IF_COND && (mmc_cmd_type(cmd) == MMC_CMD_BCR))
2729 + resp = RESP_R1;
2730 + else {
2731 + switch (mmc_resp_type(cmd)) {
2732 + case MMC_RSP_R1:
2733 + resp = RESP_R1;
2734 + break;
2735 + case MMC_RSP_R1B:
2736 + resp = RESP_R1B;
2737 + break;
2738 + case MMC_RSP_R2:
2739 + resp = RESP_R2;
2740 + break;
2741 + case MMC_RSP_R3:
2742 + resp = RESP_R3;
2743 + break;
2744 + case MMC_RSP_NONE:
2745 + default:
2746 + resp = RESP_NONE;
2747 + break;
2748 + }
2749 + }
2750 +
2751 + cmd->error = 0;
2752 + /* rawcmd :
2753 + * vol_swt << 30 | auto_cmd << 28 | blklen << 16 | go_irq << 15 |
2754 + * stop << 14 | rw << 13 | dtype << 11 | rsptyp << 7 | brk << 6 | opcode
2755 + */
2756 + rawcmd = opcode | msdc_rsp[resp] << 7 | host->blksz << 16;
2757 +
2758 + if (opcode == MMC_READ_MULTIPLE_BLOCK) {
2759 + rawcmd |= (2 << 11);
2760 + } else if (opcode == MMC_READ_SINGLE_BLOCK) {
2761 + rawcmd |= (1 << 11);
2762 + } else if (opcode == MMC_WRITE_MULTIPLE_BLOCK) {
2763 + rawcmd |= ((2 << 11) | (1 << 13));
2764 + } else if (opcode == MMC_WRITE_BLOCK) {
2765 + rawcmd |= ((1 << 11) | (1 << 13));
2766 + } else if (opcode == SD_IO_RW_EXTENDED) {
2767 + if (cmd->data->flags & MMC_DATA_WRITE)
2768 + rawcmd |= (1 << 13);
2769 + if (cmd->data->blocks > 1)
2770 + rawcmd |= (2 << 11);
2771 + else
2772 + rawcmd |= (1 << 11);
2773 + } else if (opcode == SD_IO_RW_DIRECT && cmd->flags == (unsigned int)-1) {
2774 + rawcmd |= (1 << 14);
2775 + } else if ((opcode == SD_APP_SEND_SCR) ||
2776 + (opcode == SD_APP_SEND_NUM_WR_BLKS) ||
2777 + (opcode == SD_SWITCH && (mmc_cmd_type(cmd) == MMC_CMD_ADTC)) ||
2778 + (opcode == SD_APP_SD_STATUS && (mmc_cmd_type(cmd) == MMC_CMD_ADTC)) ||
2779 + (opcode == MMC_SEND_EXT_CSD && (mmc_cmd_type(cmd) == MMC_CMD_ADTC))) {
2780 + rawcmd |= (1 << 11);
2781 + } else if (opcode == MMC_STOP_TRANSMISSION) {
2782 + rawcmd |= (1 << 14);
2783 + rawcmd &= ~(0x0FFF << 16);
2784 + }
2785 +
2786 + N_MSG(CMD, "CMD<%d><0x%.8x> Arg<0x%.8x>", opcode , rawcmd, cmd->arg);
2787 +
2788 + tmo = jiffies + timeout;
2789 +
2790 + if (opcode == MMC_SEND_STATUS) {
2791 + for (;;) {
2792 + if (!sdc_is_cmd_busy())
2793 + break;
2794 +
2795 + if (time_after(jiffies, tmo)) {
2796 + ERR_MSG("XXX cmd_busy timeout: before CMD<%d>", opcode);
2797 + cmd->error = (unsigned int)-ETIMEDOUT;
2798 + msdc_reset();
2799 + goto end;
2800 + }
2801 + }
2802 + }else {
2803 + for (;;) {
2804 + if (!sdc_is_busy())
2805 + break;
2806 + if (time_after(jiffies, tmo)) {
2807 + ERR_MSG("XXX sdc_busy timeout: before CMD<%d>", opcode);
2808 + cmd->error = (unsigned int)-ETIMEDOUT;
2809 + msdc_reset();
2810 + goto end;
2811 + }
2812 + }
2813 + }
2814 +
2815 + //BUG_ON(in_interrupt());
2816 + host->cmd = cmd;
2817 + host->cmd_rsp = resp;
2818 +
2819 + init_completion(&host->cmd_done);
2820 +
2821 + sdr_set_bits(MSDC_INTEN, wints);
2822 + sdc_send_cmd(rawcmd, cmd->arg);
2823 +
2824 +end:
2825 + return cmd->error;
2826 +}
2827 +
2828 +static unsigned int msdc_command_resp(struct msdc_host *host,
2829 + struct mmc_command *cmd,
2830 + int tune,
2831 + unsigned long timeout)
2832 +{
2833 + u32 base = host->base;
2834 + u32 opcode = cmd->opcode;
2835 + //u32 rawcmd;
2836 + u32 resp;
2837 + u32 wints = MSDC_INT_CMDRDY | MSDC_INT_RSPCRCERR | MSDC_INT_CMDTMO |
2838 + MSDC_INT_ACMDRDY | MSDC_INT_ACMDCRCERR | MSDC_INT_ACMDTMO |
2839 + MSDC_INT_ACMD19_DONE;
2840 +
2841 + resp = host->cmd_rsp;
2842 +
2843 + BUG_ON(in_interrupt());
2844 + //init_completion(&host->cmd_done);
2845 + //sdr_set_bits(MSDC_INTEN, wints);
2846 +
2847 + spin_unlock(&host->lock);
2848 + if(!wait_for_completion_timeout(&host->cmd_done, 10*timeout)){
2849 + ERR_MSG("XXX CMD<%d> wait_for_completion timeout ARG<0x%.8x>", opcode, cmd->arg);
2850 + cmd->error = (unsigned int)-ETIMEDOUT;
2851 + msdc_reset();
2852 + }
2853 + spin_lock(&host->lock);
2854 +
2855 + sdr_clr_bits(MSDC_INTEN, wints);
2856 + host->cmd = NULL;
2857 +
2858 +//end:
2859 +#ifdef MT6575_SD_DEBUG
2860 + switch (resp) {
2861 + case RESP_NONE:
2862 + N_MSG(RSP, "CMD_RSP(%d): %d RSP(%d)", opcode, cmd->error, resp);
2863 + break;
2864 + case RESP_R2:
2865 + N_MSG(RSP, "CMD_RSP(%d): %d RSP(%d)= %.8x %.8x %.8x %.8x",
2866 + opcode, cmd->error, resp, cmd->resp[0], cmd->resp[1],
2867 + cmd->resp[2], cmd->resp[3]);
2868 + break;
2869 + default: /* Response types 1, 3, 4, 5, 6, 7(1b) */
2870 + N_MSG(RSP, "CMD_RSP(%d): %d RSP(%d)= 0x%.8x",
2871 + opcode, cmd->error, resp, cmd->resp[0]);
2872 + if (cmd->error == 0) {
2873 + switch (resp) {
2874 + case RESP_R1:
2875 + case RESP_R1B:
2876 + msdc_dump_card_status(host, cmd->resp[0]);
2877 + break;
2878 + case RESP_R3:
2879 + msdc_dump_ocr_reg(host, cmd->resp[0]);
2880 + break;
2881 + case RESP_R5:
2882 + msdc_dump_io_resp(host, cmd->resp[0]);
2883 + break;
2884 + case RESP_R6:
2885 + msdc_dump_rca_resp(host, cmd->resp[0]);
2886 + break;
2887 + }
2888 + }
2889 + break;
2890 + }
2891 +#endif
2892 +
2893 + /* do we need to save card's RCA when SD_SEND_RELATIVE_ADDR */
2894 +
2895 + if (!tune) {
2896 + return cmd->error;
2897 + }
2898 +
2899 + /* memory card CRC */
2900 + if(host->hw->flags & MSDC_REMOVABLE && cmd->error == (unsigned int)(-EIO) ) {
2901 + if (sdr_read32(SDC_CMD) & 0x1800) { /* check if has data phase */
2902 + msdc_abort_data(host);
2903 + } else {
2904 + /* do basic: reset*/
2905 + msdc_reset();
2906 + msdc_clr_fifo();
2907 + msdc_clr_int();
2908 + }
2909 + cmd->error = msdc_tune_cmdrsp(host,cmd);
2910 + }
2911 +
2912 + // check DAT0
2913 + /* if (resp == RESP_R1B) {
2914 + while ((sdr_read32(MSDC_PS) & 0x10000) != 0x10000);
2915 + } */
2916 + /* CMD12 Error Handle */
2917 +
2918 + return cmd->error;
2919 +}
2920 +
2921 +static unsigned int msdc_do_command(struct msdc_host *host,
2922 + struct mmc_command *cmd,
2923 + int tune,
2924 + unsigned long timeout)
2925 +{
2926 + if (msdc_command_start(host, cmd, tune, timeout))
2927 + goto end;
2928 +
2929 + if (msdc_command_resp(host, cmd, tune, timeout))
2930 + goto end;
2931 +
2932 +end:
2933 +
2934 + N_MSG(CMD, " return<%d> resp<0x%.8x>", cmd->error, cmd->resp[0]);
2935 + return cmd->error;
2936 +}
2937 +
2938 +/* The abort condition when PIO read/write
2939 + tmo:
2940 +*/
2941 +static int msdc_pio_abort(struct msdc_host *host, struct mmc_data *data, unsigned long tmo)
2942 +{
2943 + int ret = 0;
2944 + u32 base = host->base;
2945 +
2946 + if (atomic_read(&host->abort)) {
2947 + ret = 1;
2948 + }
2949 +
2950 + if (time_after(jiffies, tmo)) {
2951 + data->error = (unsigned int)-ETIMEDOUT;
2952 + ERR_MSG("XXX PIO Data Timeout: CMD<%d>", host->mrq->cmd->opcode);
2953 + ret = 1;
2954 + }
2955 +
2956 + if(ret) {
2957 + msdc_reset();
2958 + msdc_clr_fifo();
2959 + msdc_clr_int();
2960 + ERR_MSG("msdc pio find abort");
2961 + }
2962 + return ret;
2963 +}
2964 +
2965 +/*
2966 + Need to add a timeout, or WDT timeout, system reboot.
2967 +*/
2968 +// pio mode data read/write
2969 +static int msdc_pio_read(struct msdc_host *host, struct mmc_data *data)
2970 +{
2971 + struct scatterlist *sg = data->sg;
2972 + u32 base = host->base;
2973 + u32 num = data->sg_len;
2974 + u32 *ptr;
2975 + u8 *u8ptr;
2976 + u32 left = 0;
2977 + u32 count, size = 0;
2978 + u32 wints = MSDC_INTEN_DATTMO | MSDC_INTEN_DATCRCERR ;
2979 + unsigned long tmo = jiffies + DAT_TIMEOUT;
2980 +
2981 + sdr_set_bits(MSDC_INTEN, wints);
2982 + while (num) {
2983 + left = sg_dma_len(sg);
2984 + ptr = sg_virt(sg);
2985 + while (left) {
2986 + if ((left >= MSDC_FIFO_THD) && (msdc_rxfifocnt() >= MSDC_FIFO_THD)) {
2987 + count = MSDC_FIFO_THD >> 2;
2988 + do {
2989 + *ptr++ = msdc_fifo_read32();
2990 + } while (--count);
2991 + left -= MSDC_FIFO_THD;
2992 + } else if ((left < MSDC_FIFO_THD) && msdc_rxfifocnt() >= left) {
2993 + while (left > 3) {
2994 + *ptr++ = msdc_fifo_read32();
2995 + left -= 4;
2996 + }
2997 +
2998 + u8ptr = (u8 *)ptr;
2999 + while(left) {
3000 + * u8ptr++ = msdc_fifo_read8();
3001 + left--;
3002 + }
3003 + }
3004 +
3005 + if (msdc_pio_abort(host, data, tmo)) {
3006 + goto end;
3007 + }
3008 + }
3009 + size += sg_dma_len(sg);
3010 + sg = sg_next(sg); num--;
3011 + }
3012 +end:
3013 + data->bytes_xfered += size;
3014 + N_MSG(FIO, " PIO Read<%d>bytes", size);
3015 +
3016 + sdr_clr_bits(MSDC_INTEN, wints);
3017 + if(data->error) ERR_MSG("read pio data->error<%d> left<%d> size<%d>", data->error, left, size);
3018 + return data->error;
3019 +}
3020 +
3021 +/* please make sure won't using PIO when size >= 512
3022 + which means, memory card block read/write won't using pio
3023 + then don't need to handle the CMD12 when data error.
3024 +*/
3025 +static int msdc_pio_write(struct msdc_host* host, struct mmc_data *data)
3026 +{
3027 + u32 base = host->base;
3028 + struct scatterlist *sg = data->sg;
3029 + u32 num = data->sg_len;
3030 + u32 *ptr;
3031 + u8 *u8ptr;
3032 + u32 left;
3033 + u32 count, size = 0;
3034 + u32 wints = MSDC_INTEN_DATTMO | MSDC_INTEN_DATCRCERR ;
3035 + unsigned long tmo = jiffies + DAT_TIMEOUT;
3036 +
3037 + sdr_set_bits(MSDC_INTEN, wints);
3038 + while (num) {
3039 + left = sg_dma_len(sg);
3040 + ptr = sg_virt(sg);
3041 +
3042 + while (left) {
3043 + if (left >= MSDC_FIFO_SZ && msdc_txfifocnt() == 0) {
3044 + count = MSDC_FIFO_SZ >> 2;
3045 + do {
3046 + msdc_fifo_write32(*ptr); ptr++;
3047 + } while (--count);
3048 + left -= MSDC_FIFO_SZ;
3049 + } else if (left < MSDC_FIFO_SZ && msdc_txfifocnt() == 0) {
3050 + while (left > 3) {
3051 + msdc_fifo_write32(*ptr); ptr++;
3052 + left -= 4;
3053 + }
3054 +
3055 + u8ptr = (u8*)ptr;
3056 + while(left){
3057 + msdc_fifo_write8(*u8ptr); u8ptr++;
3058 + left--;
3059 + }
3060 + }
3061 +
3062 + if (msdc_pio_abort(host, data, tmo)) {
3063 + goto end;
3064 + }
3065 + }
3066 + size += sg_dma_len(sg);
3067 + sg = sg_next(sg); num--;
3068 + }
3069 +end:
3070 + data->bytes_xfered += size;
3071 + N_MSG(FIO, " PIO Write<%d>bytes", size);
3072 + if(data->error) ERR_MSG("write pio data->error<%d>", data->error);
3073 +
3074 + sdr_clr_bits(MSDC_INTEN, wints);
3075 + return data->error;
3076 +}
3077 +
3078 +#if 0 /* --- by chhung */
3079 +// DMA resume / start / stop
3080 +static void msdc_dma_resume(struct msdc_host *host)
3081 +{
3082 + u32 base = host->base;
3083 +
3084 + sdr_set_field(MSDC_DMA_CTRL, MSDC_DMA_CTRL_RESUME, 1);
3085 +
3086 + N_MSG(DMA, "DMA resume");
3087 +}
3088 +#endif /* end of --- */
3089 +
3090 +static void msdc_dma_start(struct msdc_host *host)
3091 +{
3092 + u32 base = host->base;
3093 + u32 wints = MSDC_INTEN_XFER_COMPL | MSDC_INTEN_DATTMO | MSDC_INTEN_DATCRCERR ;
3094 +
3095 + sdr_set_bits(MSDC_INTEN, wints);
3096 + //dsb(); /* --- by chhung */
3097 + sdr_set_field(MSDC_DMA_CTRL, MSDC_DMA_CTRL_START, 1);
3098 +
3099 + N_MSG(DMA, "DMA start");
3100 +}
3101 +
3102 +static void msdc_dma_stop(struct msdc_host *host)
3103 +{
3104 + u32 base = host->base;
3105 + //u32 retries=500;
3106 + u32 wints = MSDC_INTEN_XFER_COMPL | MSDC_INTEN_DATTMO | MSDC_INTEN_DATCRCERR ;
3107 +
3108 + N_MSG(DMA, "DMA status: 0x%.8x",sdr_read32(MSDC_DMA_CFG));
3109 + //while (sdr_read32(MSDC_DMA_CFG) & MSDC_DMA_CFG_STS);
3110 +
3111 + sdr_set_field(MSDC_DMA_CTRL, MSDC_DMA_CTRL_STOP, 1);
3112 + while (sdr_read32(MSDC_DMA_CFG) & MSDC_DMA_CFG_STS);
3113 +
3114 + //dsb(); /* --- by chhung */
3115 + sdr_clr_bits(MSDC_INTEN, wints); /* Not just xfer_comp */
3116 +
3117 + N_MSG(DMA, "DMA stop");
3118 +}
3119 +
3120 +#if 0 /* --- by chhung */
3121 +/* dump a gpd list */
3122 +static void msdc_dma_dump(struct msdc_host *host, struct msdc_dma *dma)
3123 +{
3124 + gpd_t *gpd = dma->gpd;
3125 + bd_t *bd = dma->bd;
3126 + bd_t *ptr;
3127 + int i = 0;
3128 + int p_to_v;
3129 +
3130 + if (dma->mode != MSDC_MODE_DMA_DESC) {
3131 + return;
3132 + }
3133 +
3134 + ERR_MSG("try to dump gpd and bd");
3135 +
3136 + /* dump gpd */
3137 + ERR_MSG(".gpd<0x%.8x> gpd_phy<0x%.8x>", (int)gpd, (int)dma->gpd_addr);
3138 + ERR_MSG("...hwo <%d>", gpd->hwo );
3139 + ERR_MSG("...bdp <%d>", gpd->bdp );
3140 + ERR_MSG("...chksum<0x%.8x>", gpd->chksum );
3141 + //ERR_MSG("...intr <0x%.8x>", gpd->intr );
3142 + ERR_MSG("...next <0x%.8x>", (int)gpd->next );
3143 + ERR_MSG("...ptr <0x%.8x>", (int)gpd->ptr );
3144 + ERR_MSG("...buflen<0x%.8x>", gpd->buflen );
3145 + //ERR_MSG("...extlen<0x%.8x>", gpd->extlen );
3146 + //ERR_MSG("...arg <0x%.8x>", gpd->arg );
3147 + //ERR_MSG("...blknum<0x%.8x>", gpd->blknum );
3148 + //ERR_MSG("...cmd <0x%.8x>", gpd->cmd );
3149 +
3150 + /* dump bd */
3151 + ERR_MSG(".bd<0x%.8x> bd_phy<0x%.8x> gpd_ptr<0x%.8x>", (int)bd, (int)dma->bd_addr, (int)gpd->ptr);
3152 + ptr = bd;
3153 + p_to_v = ((u32)bd - (u32)dma->bd_addr);
3154 + while (1) {
3155 + ERR_MSG(".bd[%d]", i); i++;
3156 + ERR_MSG("...eol <%d>", ptr->eol );
3157 + ERR_MSG("...chksum<0x%.8x>", ptr->chksum );
3158 + //ERR_MSG("...blkpad<0x%.8x>", ptr->blkpad );
3159 + //ERR_MSG("...dwpad <0x%.8x>", ptr->dwpad );
3160 + ERR_MSG("...next <0x%.8x>", (int)ptr->next );
3161 + ERR_MSG("...ptr <0x%.8x>", (int)ptr->ptr );
3162 + ERR_MSG("...buflen<0x%.8x>", (int)ptr->buflen );
3163 +
3164 + if (ptr->eol == 1) {
3165 + break;
3166 + }
3167 +
3168 + /* find the next bd, virtual address of ptr->next */
3169 + /* don't need to enable when use malloc */
3170 + //BUG_ON( (ptr->next + p_to_v)!=(ptr+1) );
3171 + //ERR_MSG(".next bd<0x%.8x><0x%.8x>", (ptr->next + p_to_v), (ptr+1));
3172 + ptr++;
3173 + }
3174 +
3175 + ERR_MSG("dump gpd and bd finished");
3176 +}
3177 +#endif /* end of --- */
3178 +
3179 +/* calc checksum */
3180 +static u8 msdc_dma_calcs(u8 *buf, u32 len)
3181 +{
3182 + u32 i, sum = 0;
3183 + for (i = 0; i < len; i++) {
3184 + sum += buf[i];
3185 + }
3186 + return 0xFF - (u8)sum;
3187 +}
3188 +
3189 +/* gpd bd setup + dma registers */
3190 +static int msdc_dma_config(struct msdc_host *host, struct msdc_dma *dma)
3191 +{
3192 + u32 base = host->base;
3193 + u32 sglen = dma->sglen;
3194 + //u32 i, j, num, bdlen, arg, xfersz;
3195 + u32 j, num, bdlen;
3196 + u8 blkpad, dwpad, chksum;
3197 + struct scatterlist *sg = dma->sg;
3198 + gpd_t *gpd;
3199 + bd_t *bd;
3200 +
3201 + switch (dma->mode) {
3202 + case MSDC_MODE_DMA_BASIC:
3203 + BUG_ON(dma->xfersz > 65535);
3204 + BUG_ON(dma->sglen != 1);
3205 + sdr_write32(MSDC_DMA_SA, PHYSADDR(sg_dma_address(sg)));
3206 + sdr_set_field(MSDC_DMA_CTRL, MSDC_DMA_CTRL_LASTBUF, 1);
3207 +//#if defined (CONFIG_RALINK_MT7620)
3208 + if (ralink_soc == MT762X_SOC_MT7620A)
3209 + sdr_set_field(MSDC_DMA_CTRL, MSDC_DMA_CTRL_XFERSZ, sg_dma_len(sg));
3210 +//#elif defined (CONFIG_RALINK_MT7621) || defined (CONFIG_RALINK_MT7628)
3211 + else
3212 + sdr_write32((volatile u32*)(RALINK_MSDC_BASE+0xa8), sg_dma_len(sg));
3213 +//#endif
3214 + sdr_set_field(MSDC_DMA_CTRL, MSDC_DMA_CTRL_BRUSTSZ, dma->burstsz);
3215 + sdr_set_field(MSDC_DMA_CTRL, MSDC_DMA_CTRL_MODE, 0);
3216 + break;
3217 + case MSDC_MODE_DMA_DESC:
3218 + blkpad = (dma->flags & DMA_FLAG_PAD_BLOCK) ? 1 : 0;
3219 + dwpad = (dma->flags & DMA_FLAG_PAD_DWORD) ? 1 : 0;
3220 + chksum = (dma->flags & DMA_FLAG_EN_CHKSUM) ? 1 : 0;
3221 +
3222 + /* calculate the required number of gpd */
3223 + num = (sglen + MAX_BD_PER_GPD - 1) / MAX_BD_PER_GPD;
3224 + BUG_ON(num !=1 );
3225 +
3226 + gpd = dma->gpd;
3227 + bd = dma->bd;
3228 + bdlen = sglen;
3229 +
3230 + /* modify gpd*/
3231 + //gpd->intr = 0;
3232 + gpd->hwo = 1; /* hw will clear it */
3233 + gpd->bdp = 1;
3234 + gpd->chksum = 0; /* need to clear first. */
3235 + gpd->chksum = (chksum ? msdc_dma_calcs((u8 *)gpd, 16) : 0);
3236 +
3237 + /* modify bd*/
3238 + for (j = 0; j < bdlen; j++) {
3239 + msdc_init_bd(&bd[j], blkpad, dwpad, sg_dma_address(sg), sg_dma_len(sg));
3240 + if(j == bdlen - 1) {
3241 + bd[j].eol = 1; /* the last bd */
3242 + } else {
3243 + bd[j].eol = 0;
3244 + }
3245 + bd[j].chksum = 0; /* checksume need to clear first */
3246 + bd[j].chksum = (chksum ? msdc_dma_calcs((u8 *)(&bd[j]), 16) : 0);
3247 + sg++;
3248 + }
3249 +
3250 + dma->used_gpd += 2;
3251 + dma->used_bd += bdlen;
3252 +
3253 + sdr_set_field(MSDC_DMA_CFG, MSDC_DMA_CFG_DECSEN, chksum);
3254 + sdr_set_field(MSDC_DMA_CTRL, MSDC_DMA_CTRL_BRUSTSZ, dma->burstsz);
3255 + sdr_set_field(MSDC_DMA_CTRL, MSDC_DMA_CTRL_MODE, 1);
3256 +
3257 + sdr_write32(MSDC_DMA_SA, PHYSADDR((u32)dma->gpd_addr));
3258 + break;
3259 +
3260 + default:
3261 + break;
3262 + }
3263 +
3264 + N_MSG(DMA, "DMA_CTRL = 0x%x", sdr_read32(MSDC_DMA_CTRL));
3265 + N_MSG(DMA, "DMA_CFG = 0x%x", sdr_read32(MSDC_DMA_CFG));
3266 + N_MSG(DMA, "DMA_SA = 0x%x", sdr_read32(MSDC_DMA_SA));
3267 +
3268 + return 0;
3269 +}
3270 +
3271 +static void msdc_dma_setup(struct msdc_host *host, struct msdc_dma *dma,
3272 + struct scatterlist *sg, unsigned int sglen)
3273 +{
3274 + BUG_ON(sglen > MAX_BD_NUM); /* not support currently */
3275 +
3276 + dma->sg = sg;
3277 + dma->flags = DMA_FLAG_EN_CHKSUM;
3278 + //dma->flags = DMA_FLAG_NONE; /* CHECKME */
3279 + dma->sglen = sglen;
3280 + dma->xfersz = host->xfer_size;
3281 + dma->burstsz = MSDC_BRUST_64B;
3282 +
3283 + if (sglen == 1 && sg_dma_len(sg) <= MAX_DMA_CNT)
3284 + dma->mode = MSDC_MODE_DMA_BASIC;
3285 + else
3286 + dma->mode = MSDC_MODE_DMA_DESC;
3287 +
3288 + N_MSG(DMA, "DMA mode<%d> sglen<%d> xfersz<%d>", dma->mode, dma->sglen, dma->xfersz);
3289 +
3290 + msdc_dma_config(host, dma);
3291 +
3292 + /*if (dma->mode == MSDC_MODE_DMA_DESC) {
3293 + //msdc_dma_dump(host, dma);
3294 + } */
3295 +}
3296 +
3297 +/* set block number before send command */
3298 +static void msdc_set_blknum(struct msdc_host *host, u32 blknum)
3299 +{
3300 + u32 base = host->base;
3301 +
3302 + sdr_write32(SDC_BLK_NUM, blknum);
3303 +}
3304 +
3305 +static int msdc_do_request(struct mmc_host*mmc, struct mmc_request*mrq)
3306 +{
3307 + struct msdc_host *host = mmc_priv(mmc);
3308 + struct mmc_command *cmd;
3309 + struct mmc_data *data;
3310 + u32 base = host->base;
3311 + //u32 intsts = 0;
3312 + unsigned int left=0;
3313 + int dma = 0, read = 1, dir = DMA_FROM_DEVICE, send_type=0;
3314 +
3315 + #define SND_DAT 0
3316 + #define SND_CMD 1
3317 +
3318 + BUG_ON(mmc == NULL);
3319 + BUG_ON(mrq == NULL);
3320 +
3321 + host->error = 0;
3322 + atomic_set(&host->abort, 0);
3323 +
3324 + cmd = mrq->cmd;
3325 + data = mrq->cmd->data;
3326 +
3327 +#if 0 /* --- by chhung */
3328 + //if(host->id ==1){
3329 + N_MSG(OPS, "enable clock!");
3330 + msdc_ungate_clock(host->id);
3331 + //}
3332 +#endif /* end of --- */
3333 +
3334 + if (!data) {
3335 + send_type=SND_CMD;
3336 + if (msdc_do_command(host, cmd, 1, CMD_TIMEOUT) != 0) {
3337 + goto done;
3338 + }
3339 + } else {
3340 + BUG_ON(data->blksz > HOST_MAX_BLKSZ);
3341 + send_type=SND_DAT;
3342 +
3343 + data->error = 0;
3344 + read = data->flags & MMC_DATA_READ ? 1 : 0;
3345 + host->data = data;
3346 + host->xfer_size = data->blocks * data->blksz;
3347 + host->blksz = data->blksz;
3348 +
3349 + /* deside the transfer mode */
3350 + if (drv_mode[host->id] == MODE_PIO) {
3351 + host->dma_xfer = dma = 0;
3352 + } else if (drv_mode[host->id] == MODE_DMA) {
3353 + host->dma_xfer = dma = 1;
3354 + } else if (drv_mode[host->id] == MODE_SIZE_DEP) {
3355 + host->dma_xfer = dma = ((host->xfer_size >= dma_size[host->id]) ? 1 : 0);
3356 + }
3357 +
3358 + if (read) {
3359 + if ((host->timeout_ns != data->timeout_ns) ||
3360 + (host->timeout_clks != data->timeout_clks)) {
3361 + msdc_set_timeout(host, data->timeout_ns, data->timeout_clks);
3362 + }
3363 + }
3364 +
3365 + msdc_set_blknum(host, data->blocks);
3366 + //msdc_clr_fifo(); /* no need */
3367 +
3368 + if (dma) {
3369 + msdc_dma_on(); /* enable DMA mode first!! */
3370 + init_completion(&host->xfer_done);
3371 +
3372 + /* start the command first*/
3373 + if (msdc_command_start(host, cmd, 1, CMD_TIMEOUT) != 0)
3374 + goto done;
3375 +
3376 + dir = read ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
3377 + (void)dma_map_sg(mmc_dev(mmc), data->sg, data->sg_len, dir);
3378 + msdc_dma_setup(host, &host->dma, data->sg, data->sg_len);
3379 +
3380 + /* then wait command done */
3381 + if (msdc_command_resp(host, cmd, 1, CMD_TIMEOUT) != 0)
3382 + goto done;
3383 +
3384 + /* for read, the data coming too fast, then CRC error
3385 + start DMA no business with CRC. */
3386 + //init_completion(&host->xfer_done);
3387 + msdc_dma_start(host);
3388 +
3389 + spin_unlock(&host->lock);
3390 + if(!wait_for_completion_timeout(&host->xfer_done, DAT_TIMEOUT)){
3391 + ERR_MSG("XXX CMD<%d> wait xfer_done<%d> timeout!!", cmd->opcode, data->blocks * data->blksz);
3392 + ERR_MSG(" DMA_SA = 0x%x", sdr_read32(MSDC_DMA_SA));
3393 + ERR_MSG(" DMA_CA = 0x%x", sdr_read32(MSDC_DMA_CA));
3394 + ERR_MSG(" DMA_CTRL = 0x%x", sdr_read32(MSDC_DMA_CTRL));
3395 + ERR_MSG(" DMA_CFG = 0x%x", sdr_read32(MSDC_DMA_CFG));
3396 + data->error = (unsigned int)-ETIMEDOUT;
3397 +
3398 + msdc_reset();
3399 + msdc_clr_fifo();
3400 + msdc_clr_int();
3401 + }
3402 + spin_lock(&host->lock);
3403 + msdc_dma_stop(host);
3404 + } else {
3405 + /* Firstly: send command */
3406 + if (msdc_do_command(host, cmd, 1, CMD_TIMEOUT) != 0) {
3407 + goto done;
3408 + }
3409 +
3410 + /* Secondly: pio data phase */
3411 + if (read) {
3412 + if (msdc_pio_read(host, data)){
3413 + goto done;
3414 + }
3415 + } else {
3416 + if (msdc_pio_write(host, data)) {
3417 + goto done;
3418 + }
3419 + }
3420 +
3421 + /* For write case: make sure contents in fifo flushed to device */
3422 + if (!read) {
3423 + while (1) {
3424 + left=msdc_txfifocnt();
3425 + if (left == 0) {
3426 + break;
3427 + }
3428 + if (msdc_pio_abort(host, data, jiffies + DAT_TIMEOUT)) {
3429 + break;
3430 + /* Fix me: what about if data error, when stop ? how to? */
3431 + }
3432 + }
3433 + } else {
3434 + /* Fix me: read case: need to check CRC error */
3435 + }
3436 +
3437 + /* For write case: SDCBUSY and Xfer_Comp will assert when DAT0 not busy.
3438 + For read case : SDCBUSY and Xfer_Comp will assert when last byte read out from FIFO.
3439 + */
3440 +
3441 + /* try not to wait xfer_comp interrupt.
3442 + the next command will check SDC_BUSY.
3443 + SDC_BUSY means xfer_comp assert
3444 + */
3445 +
3446 + } // PIO mode
3447 +
3448 + /* Last: stop transfer */
3449 + if (data->stop){
3450 + if (msdc_do_command(host, data->stop, 0, CMD_TIMEOUT) != 0) {
3451 + goto done;
3452 + }
3453 + }
3454 + }
3455 +
3456 +done:
3457 + if (data != NULL) {
3458 + host->data = NULL;
3459 + host->dma_xfer = 0;
3460 + if (dma != 0) {
3461 + msdc_dma_off();
3462 + host->dma.used_bd = 0;
3463 + host->dma.used_gpd = 0;
3464 + dma_unmap_sg(mmc_dev(mmc), data->sg, data->sg_len, dir);
3465 + }
3466 + host->blksz = 0;
3467 +
3468 +#if 0 // don't stop twice!
3469 + if(host->hw->flags & MSDC_REMOVABLE && data->error) {
3470 + msdc_abort_data(host);
3471 + /* reset in IRQ, stop command has issued. -> No need */
3472 + }
3473 +#endif
3474 +
3475 + N_MSG(OPS, "CMD<%d> data<%s %s> blksz<%d> block<%d> error<%d>",cmd->opcode, (dma? "dma":"pio"),
3476 + (read ? "read ":"write") ,data->blksz, data->blocks, data->error);
3477 + }
3478 +
3479 +#if 0 /* --- by chhung */
3480 +#if 1
3481 + //if(host->id==1) {
3482 + if(send_type==SND_CMD) {
3483 + if(cmd->opcode == MMC_SEND_STATUS) {
3484 + if((cmd->resp[0] & CARD_READY_FOR_DATA) ||(CARD_CURRENT_STATE(cmd->resp[0]) != 7)){
3485 + N_MSG(OPS,"disable clock, CMD13 IDLE");
3486 + msdc_gate_clock(host->id);
3487 + }
3488 + } else {
3489 + N_MSG(OPS,"disable clock, CMD<%d>", cmd->opcode);
3490 + msdc_gate_clock(host->id);
3491 + }
3492 + } else {
3493 + if(read) {
3494 + N_MSG(OPS,"disable clock!!! Read CMD<%d>",cmd->opcode);
3495 + msdc_gate_clock(host->id);
3496 + }
3497 + }
3498 + //}
3499 +#else
3500 + msdc_gate_clock(host->id);
3501 +#endif
3502 +#endif /* end of --- */
3503 +
3504 + if (mrq->cmd->error) host->error = 0x001;
3505 + if (mrq->data && mrq->data->error) host->error |= 0x010;
3506 + if (mrq->stop && mrq->stop->error) host->error |= 0x100;
3507 +
3508 + //if (host->error) ERR_MSG("host->error<%d>", host->error);
3509 +
3510 + return host->error;
3511 +}
3512 +
3513 +static int msdc_app_cmd(struct mmc_host *mmc, struct msdc_host *host)
3514 +{
3515 + struct mmc_command cmd;
3516 + struct mmc_request mrq;
3517 + u32 err;
3518 +
3519 + memset(&cmd, 0, sizeof(struct mmc_command));
3520 + cmd.opcode = MMC_APP_CMD;
3521 +#if 0 /* bug: we meet mmc->card is null when ACMD6 */
3522 + cmd.arg = mmc->card->rca << 16;
3523 +#else
3524 + cmd.arg = host->app_cmd_arg;
3525 +#endif
3526 + cmd.flags = MMC_RSP_SPI_R1 | MMC_RSP_R1 | MMC_CMD_AC;
3527 +
3528 + memset(&mrq, 0, sizeof(struct mmc_request));
3529 + mrq.cmd = &cmd; cmd.mrq = &mrq;
3530 + cmd.data = NULL;
3531 +
3532 + err = msdc_do_command(host, &cmd, 0, CMD_TIMEOUT);
3533 + return err;
3534 +}
3535 +
3536 +static int msdc_tune_cmdrsp(struct msdc_host*host, struct mmc_command *cmd)
3537 +{
3538 + int result = -1;
3539 + u32 base = host->base;
3540 + u32 rsmpl, cur_rsmpl, orig_rsmpl;
3541 + u32 rrdly, cur_rrdly = 0xffffffff, orig_rrdly;
3542 + u32 skip = 1;
3543 +
3544 + /* ==== don't support 3.0 now ====
3545 + 1: R_SMPL[1]
3546 + 2: PAD_CMD_RESP_RXDLY[26:22]
3547 + ==========================*/
3548 +
3549 + // save the previous tune result
3550 + sdr_get_field(MSDC_IOCON, MSDC_IOCON_RSPL, orig_rsmpl);
3551 + sdr_get_field(MSDC_PAD_TUNE, MSDC_PAD_TUNE_CMDRRDLY, orig_rrdly);
3552 +
3553 + rrdly = 0;
3554 + do {
3555 + for (rsmpl = 0; rsmpl < 2; rsmpl++) {
3556 + /* Lv1: R_SMPL[1] */
3557 + cur_rsmpl = (orig_rsmpl + rsmpl) % 2;
3558 + if (skip == 1) {
3559 + skip = 0;
3560 + continue;
3561 + }
3562 + sdr_set_field(MSDC_IOCON, MSDC_IOCON_RSPL, cur_rsmpl);
3563 +
3564 + if (host->app_cmd) {
3565 + result = msdc_app_cmd(host->mmc, host);
3566 + if (result) {
3567 + ERR_MSG("TUNE_CMD app_cmd<%d> failed: RESP_RXDLY<%d>,R_SMPL<%d>",
3568 + host->mrq->cmd->opcode, cur_rrdly, cur_rsmpl);
3569 + continue;
3570 + }
3571 + }
3572 + result = msdc_do_command(host, cmd, 0, CMD_TIMEOUT); // not tune.
3573 + ERR_MSG("TUNE_CMD<%d> %s PAD_CMD_RESP_RXDLY[26:22]<%d> R_SMPL[1]<%d>", cmd->opcode,
3574 + (result == 0) ? "PASS" : "FAIL", cur_rrdly, cur_rsmpl);
3575 +
3576 + if (result == 0) {
3577 + return 0;
3578 + }
3579 + if (result != (unsigned int)(-EIO)) {
3580 + ERR_MSG("TUNE_CMD<%d> Error<%d> not -EIO", cmd->opcode, result);
3581 + return result;
3582 + }
3583 +
3584 + /* should be EIO */
3585 + if (sdr_read32(SDC_CMD) & 0x1800) { /* check if has data phase */
3586 + msdc_abort_data(host);
3587 + }
3588 + }
3589 +
3590 + /* Lv2: PAD_CMD_RESP_RXDLY[26:22] */
3591 + cur_rrdly = (orig_rrdly + rrdly + 1) % 32;
3592 + sdr_set_field(MSDC_PAD_TUNE, MSDC_PAD_TUNE_CMDRRDLY, cur_rrdly);
3593 + }while (++rrdly < 32);
3594 +
3595 + return result;
3596 +}
3597 +
3598 +/* Support SD2.0 Only */
3599 +static int msdc_tune_bread(struct mmc_host *mmc, struct mmc_request *mrq)
3600 +{
3601 + struct msdc_host *host = mmc_priv(mmc);
3602 + u32 base = host->base;
3603 + u32 ddr=0;
3604 + u32 dcrc=0;
3605 + u32 rxdly, cur_rxdly0, cur_rxdly1;
3606 + u32 dsmpl, cur_dsmpl, orig_dsmpl;
3607 + u32 cur_dat0, cur_dat1, cur_dat2, cur_dat3;
3608 + u32 cur_dat4, cur_dat5, cur_dat6, cur_dat7;
3609 + u32 orig_dat0, orig_dat1, orig_dat2, orig_dat3;
3610 + u32 orig_dat4, orig_dat5, orig_dat6, orig_dat7;
3611 + int result = -1;
3612 + u32 skip = 1;
3613 +
3614 + sdr_get_field(MSDC_IOCON, MSDC_IOCON_DSPL, orig_dsmpl);
3615 +
3616 + /* Tune Method 2. */
3617 + sdr_set_field(MSDC_IOCON, MSDC_IOCON_DDLSEL, 1);
3618 +
3619 + rxdly = 0;
3620 + do {
3621 + for (dsmpl = 0; dsmpl < 2; dsmpl++) {
3622 + cur_dsmpl = (orig_dsmpl + dsmpl) % 2;
3623 + if (skip == 1) {
3624 + skip = 0;
3625 + continue;
3626 + }
3627 + sdr_set_field(MSDC_IOCON, MSDC_IOCON_DSPL, cur_dsmpl);
3628 +
3629 + if (host->app_cmd) {
3630 + result = msdc_app_cmd(host->mmc, host);
3631 + if (result) {
3632 + ERR_MSG("TUNE_BREAD app_cmd<%d> failed", host->mrq->cmd->opcode);
3633 + continue;
3634 + }
3635 + }
3636 + result = msdc_do_request(mmc,mrq);
3637 +
3638 + sdr_get_field(SDC_DCRC_STS, SDC_DCRC_STS_POS|SDC_DCRC_STS_NEG, dcrc); /* RO */
3639 + if (!ddr) dcrc &= ~SDC_DCRC_STS_NEG;
3640 + ERR_MSG("TUNE_BREAD<%s> dcrc<0x%x> DATRDDLY0/1<0x%x><0x%x> dsmpl<0x%x>",
3641 + (result == 0 && dcrc == 0) ? "PASS" : "FAIL", dcrc,
3642 + sdr_read32(MSDC_DAT_RDDLY0), sdr_read32(MSDC_DAT_RDDLY1), cur_dsmpl);
3643 +
3644 + /* Fix me: result is 0, but dcrc is still exist */
3645 + if (result == 0 && dcrc == 0) {
3646 + goto done;
3647 + } else {
3648 + /* there is a case: command timeout, and data phase not processed */
3649 + if (mrq->data->error != 0 && mrq->data->error != (unsigned int)(-EIO)) {
3650 + ERR_MSG("TUNE_READ: result<0x%x> cmd_error<%d> data_error<%d>",
3651 + result, mrq->cmd->error, mrq->data->error);
3652 + goto done;
3653 + }
3654 + }
3655 + }
3656 +
3657 + cur_rxdly0 = sdr_read32(MSDC_DAT_RDDLY0);
3658 + cur_rxdly1 = sdr_read32(MSDC_DAT_RDDLY1);
3659 +
3660 + /* E1 ECO. YD: Reverse */
3661 + if (sdr_read32(MSDC_ECO_VER) >= 4) {
3662 + orig_dat0 = (cur_rxdly0 >> 24) & 0x1F;
3663 + orig_dat1 = (cur_rxdly0 >> 16) & 0x1F;
3664 + orig_dat2 = (cur_rxdly0 >> 8) & 0x1F;
3665 + orig_dat3 = (cur_rxdly0 >> 0) & 0x1F;
3666 + orig_dat4 = (cur_rxdly1 >> 24) & 0x1F;
3667 + orig_dat5 = (cur_rxdly1 >> 16) & 0x1F;
3668 + orig_dat6 = (cur_rxdly1 >> 8) & 0x1F;
3669 + orig_dat7 = (cur_rxdly1 >> 0) & 0x1F;
3670 + } else {
3671 + orig_dat0 = (cur_rxdly0 >> 0) & 0x1F;
3672 + orig_dat1 = (cur_rxdly0 >> 8) & 0x1F;
3673 + orig_dat2 = (cur_rxdly0 >> 16) & 0x1F;
3674 + orig_dat3 = (cur_rxdly0 >> 24) & 0x1F;
3675 + orig_dat4 = (cur_rxdly1 >> 0) & 0x1F;
3676 + orig_dat5 = (cur_rxdly1 >> 8) & 0x1F;
3677 + orig_dat6 = (cur_rxdly1 >> 16) & 0x1F;
3678 + orig_dat7 = (cur_rxdly1 >> 24) & 0x1F;
3679 + }
3680 +
3681 + if (ddr) {
3682 + cur_dat0 = (dcrc & (1 << 0) || dcrc & (1 << 8)) ? ((orig_dat0 + 1) % 32) : orig_dat0;
3683 + cur_dat1 = (dcrc & (1 << 1) || dcrc & (1 << 9)) ? ((orig_dat1 + 1) % 32) : orig_dat1;
3684 + cur_dat2 = (dcrc & (1 << 2) || dcrc & (1 << 10)) ? ((orig_dat2 + 1) % 32) : orig_dat2;
3685 + cur_dat3 = (dcrc & (1 << 3) || dcrc & (1 << 11)) ? ((orig_dat3 + 1) % 32) : orig_dat3;
3686 + } else {
3687 + cur_dat0 = (dcrc & (1 << 0)) ? ((orig_dat0 + 1) % 32) : orig_dat0;
3688 + cur_dat1 = (dcrc & (1 << 1)) ? ((orig_dat1 + 1) % 32) : orig_dat1;
3689 + cur_dat2 = (dcrc & (1 << 2)) ? ((orig_dat2 + 1) % 32) : orig_dat2;
3690 + cur_dat3 = (dcrc & (1 << 3)) ? ((orig_dat3 + 1) % 32) : orig_dat3;
3691 + }
3692 + cur_dat4 = (dcrc & (1 << 4)) ? ((orig_dat4 + 1) % 32) : orig_dat4;
3693 + cur_dat5 = (dcrc & (1 << 5)) ? ((orig_dat5 + 1) % 32) : orig_dat5;
3694 + cur_dat6 = (dcrc & (1 << 6)) ? ((orig_dat6 + 1) % 32) : orig_dat6;
3695 + cur_dat7 = (dcrc & (1 << 7)) ? ((orig_dat7 + 1) % 32) : orig_dat7;
3696 +
3697 + cur_rxdly0 = (cur_dat0 << 24) | (cur_dat1 << 16) | (cur_dat2 << 8) | (cur_dat3 << 0);
3698 + cur_rxdly1 = (cur_dat4 << 24) | (cur_dat5 << 16) | (cur_dat6 << 8) | (cur_dat7 << 0);
3699 +
3700 + sdr_write32(MSDC_DAT_RDDLY0, cur_rxdly0);
3701 + sdr_write32(MSDC_DAT_RDDLY1, cur_rxdly1);
3702 +
3703 + } while (++rxdly < 32);
3704 +
3705 +done:
3706 + return result;
3707 +}
3708 +
3709 +static int msdc_tune_bwrite(struct mmc_host *mmc,struct mmc_request *mrq)
3710 +{
3711 + struct msdc_host *host = mmc_priv(mmc);
3712 + u32 base = host->base;
3713 +
3714 + u32 wrrdly, cur_wrrdly = 0xffffffff, orig_wrrdly;
3715 + u32 dsmpl, cur_dsmpl, orig_dsmpl;
3716 + u32 rxdly, cur_rxdly0;
3717 + u32 orig_dat0, orig_dat1, orig_dat2, orig_dat3;
3718 + u32 cur_dat0, cur_dat1, cur_dat2, cur_dat3;
3719 + int result = -1;
3720 + u32 skip = 1;
3721 +
3722 + // MSDC_IOCON_DDR50CKD need to check. [Fix me]
3723 +
3724 + sdr_get_field(MSDC_PAD_TUNE, MSDC_PAD_TUNE_DATWRDLY, orig_wrrdly);
3725 + sdr_get_field(MSDC_IOCON, MSDC_IOCON_DSPL, orig_dsmpl );
3726 +
3727 + /* Tune Method 2. just DAT0 */
3728 + sdr_set_field(MSDC_IOCON, MSDC_IOCON_DDLSEL, 1);
3729 + cur_rxdly0 = sdr_read32(MSDC_DAT_RDDLY0);
3730 +
3731 + /* E1 ECO. YD: Reverse */
3732 + if (sdr_read32(MSDC_ECO_VER) >= 4) {
3733 + orig_dat0 = (cur_rxdly0 >> 24) & 0x1F;
3734 + orig_dat1 = (cur_rxdly0 >> 16) & 0x1F;
3735 + orig_dat2 = (cur_rxdly0 >> 8) & 0x1F;
3736 + orig_dat3 = (cur_rxdly0 >> 0) & 0x1F;
3737 + } else {
3738 + orig_dat0 = (cur_rxdly0 >> 0) & 0x1F;
3739 + orig_dat1 = (cur_rxdly0 >> 8) & 0x1F;
3740 + orig_dat2 = (cur_rxdly0 >> 16) & 0x1F;
3741 + orig_dat3 = (cur_rxdly0 >> 24) & 0x1F;
3742 + }
3743 +
3744 + rxdly = 0;
3745 + do {
3746 + wrrdly = 0;
3747 + do {
3748 + for (dsmpl = 0; dsmpl < 2; dsmpl++) {
3749 + cur_dsmpl = (orig_dsmpl + dsmpl) % 2;
3750 + if (skip == 1) {
3751 + skip = 0;
3752 + continue;
3753 + }
3754 + sdr_set_field(MSDC_IOCON, MSDC_IOCON_DSPL, cur_dsmpl);
3755 +
3756 + if (host->app_cmd) {
3757 + result = msdc_app_cmd(host->mmc, host);
3758 + if (result) {
3759 + ERR_MSG("TUNE_BWRITE app_cmd<%d> failed", host->mrq->cmd->opcode);
3760 + continue;
3761 + }
3762 + }
3763 + result = msdc_do_request(mmc,mrq);
3764 +
3765 + ERR_MSG("TUNE_BWRITE<%s> DSPL<%d> DATWRDLY<%d> MSDC_DAT_RDDLY0<0x%x>",
3766 + result == 0 ? "PASS" : "FAIL",
3767 + cur_dsmpl, cur_wrrdly, cur_rxdly0);
3768 +
3769 + if (result == 0) {
3770 + goto done;
3771 + }
3772 + else {
3773 + /* there is a case: command timeout, and data phase not processed */
3774 + if (mrq->data->error != (unsigned int)(-EIO)) {
3775 + ERR_MSG("TUNE_READ: result<0x%x> cmd_error<%d> data_error<%d>",
3776 + result, mrq->cmd->error, mrq->data->error);
3777 + goto done;
3778 + }
3779 + }
3780 + }
3781 + cur_wrrdly = (orig_wrrdly + wrrdly + 1) % 32;
3782 + sdr_set_field(MSDC_PAD_TUNE, MSDC_PAD_TUNE_DATWRDLY, cur_wrrdly);
3783 + } while (++wrrdly < 32);
3784 +
3785 + cur_dat0 = (orig_dat0 + rxdly) % 32; /* only adjust bit-1 for crc */
3786 + cur_dat1 = orig_dat1;
3787 + cur_dat2 = orig_dat2;
3788 + cur_dat3 = orig_dat3;
3789 +
3790 + cur_rxdly0 = (cur_dat0 << 24) | (cur_dat1 << 16) | (cur_dat2 << 8) | (cur_dat3 << 0);
3791 + sdr_write32(MSDC_DAT_RDDLY0, cur_rxdly0);
3792 + } while (++rxdly < 32);
3793 +
3794 +done:
3795 + return result;
3796 +}
3797 +
3798 +static int msdc_get_card_status(struct mmc_host *mmc, struct msdc_host *host, u32 *status)
3799 +{
3800 + struct mmc_command cmd;
3801 + struct mmc_request mrq;
3802 + u32 err;
3803 +
3804 + memset(&cmd, 0, sizeof(struct mmc_command));
3805 + cmd.opcode = MMC_SEND_STATUS;
3806 + if (mmc->card) {
3807 + cmd.arg = mmc->card->rca << 16;
3808 + } else {
3809 + ERR_MSG("cmd13 mmc card is null");
3810 + cmd.arg = host->app_cmd_arg;
3811 + }
3812 + cmd.flags = MMC_RSP_SPI_R2 | MMC_RSP_R1 | MMC_CMD_AC;
3813 +
3814 + memset(&mrq, 0, sizeof(struct mmc_request));
3815 + mrq.cmd = &cmd; cmd.mrq = &mrq;
3816 + cmd.data = NULL;
3817 +
3818 + err = msdc_do_command(host, &cmd, 1, CMD_TIMEOUT);
3819 +
3820 + if (status) {
3821 + *status = cmd.resp[0];
3822 + }
3823 +
3824 + return err;
3825 +}
3826 +
3827 +static int msdc_check_busy(struct mmc_host *mmc, struct msdc_host *host)
3828 +{
3829 + u32 err = 0;
3830 + u32 status = 0;
3831 +
3832 + do {
3833 + err = msdc_get_card_status(mmc, host, &status);
3834 + if (err) return err;
3835 + /* need cmd12? */
3836 + ERR_MSG("cmd<13> resp<0x%x>", status);
3837 + } while (R1_CURRENT_STATE(status) == 7);
3838 +
3839 + return err;
3840 +}
3841 +
3842 +/* failed when msdc_do_request */
3843 +static int msdc_tune_request(struct mmc_host *mmc, struct mmc_request *mrq)
3844 +{
3845 + struct msdc_host *host = mmc_priv(mmc);
3846 + struct mmc_command *cmd;
3847 + struct mmc_data *data;
3848 + //u32 base = host->base;
3849 + int ret=0, read;
3850 +
3851 + cmd = mrq->cmd;
3852 + data = mrq->cmd->data;
3853 +
3854 + read = data->flags & MMC_DATA_READ ? 1 : 0;
3855 +
3856 + if (read) {
3857 + if (data->error == (unsigned int)(-EIO)) {
3858 + ret = msdc_tune_bread(mmc,mrq);
3859 + }
3860 + } else {
3861 + ret = msdc_check_busy(mmc, host);
3862 + if (ret){
3863 + ERR_MSG("XXX cmd13 wait program done failed");
3864 + return ret;
3865 + }
3866 + /* CRC and TO */
3867 + /* Fix me: don't care card status? */
3868 + ret = msdc_tune_bwrite(mmc,mrq);
3869 + }
3870 +
3871 + return ret;
3872 +}
3873 +
3874 +/* ops.request */
3875 +static void msdc_ops_request(struct mmc_host *mmc,struct mmc_request *mrq)
3876 +{
3877 + struct msdc_host *host = mmc_priv(mmc);
3878 +
3879 + //=== for sdio profile ===
3880 +#if 0 /* --- by chhung */
3881 + u32 old_H32, old_L32, new_H32, new_L32;
3882 + u32 ticks = 0, opcode = 0, sizes = 0, bRx = 0;
3883 +#endif /* end of --- */
3884 +
3885 + if(host->mrq){
3886 + ERR_MSG("XXX host->mrq<0x%.8x>", (int)host->mrq);
3887 + BUG();
3888 + }
3889 +
3890 + if (!is_card_present(host) || host->power_mode == MMC_POWER_OFF) {
3891 + ERR_MSG("cmd<%d> card<%d> power<%d>", mrq->cmd->opcode, is_card_present(host), host->power_mode);
3892 + mrq->cmd->error = (unsigned int)-ENOMEDIUM;
3893 +
3894 +#if 1
3895 + mrq->done(mrq); // call done directly.
3896 +#else
3897 + mrq->cmd->retries = 0; // please don't retry.
3898 + mmc_request_done(mmc, mrq);
3899 +#endif
3900 +
3901 + return;
3902 + }
3903 +
3904 + /* start to process */
3905 + spin_lock(&host->lock);
3906 +#if 0 /* --- by chhung */
3907 + if (sdio_pro_enable) { //=== for sdio profile ===
3908 + if (mrq->cmd->opcode == 52 || mrq->cmd->opcode == 53) {
3909 + GPT_GetCounter64(&old_L32, &old_H32);
3910 + }
3911 + }
3912 +#endif /* end of --- */
3913 +
3914 + host->mrq = mrq;
3915 +
3916 + if (msdc_do_request(mmc,mrq)) {
3917 + if(host->hw->flags & MSDC_REMOVABLE && mrq->data && mrq->data->error) {
3918 + msdc_tune_request(mmc,mrq);
3919 + }
3920 + }
3921 +
3922 + /* ==== when request done, check if app_cmd ==== */
3923 + if (mrq->cmd->opcode == MMC_APP_CMD) {
3924 + host->app_cmd = 1;
3925 + host->app_cmd_arg = mrq->cmd->arg; /* save the RCA */
3926 + } else {
3927 + host->app_cmd = 0;
3928 + //host->app_cmd_arg = 0;
3929 + }
3930 +
3931 + host->mrq = NULL;
3932 +
3933 +#if 0 /* --- by chhung */
3934 + //=== for sdio profile ===
3935 + if (sdio_pro_enable) {
3936 + if (mrq->cmd->opcode == 52 || mrq->cmd->opcode == 53) {
3937 + GPT_GetCounter64(&new_L32, &new_H32);
3938 + ticks = msdc_time_calc(old_L32, old_H32, new_L32, new_H32);
3939 +
3940 + opcode = mrq->cmd->opcode;
3941 + if (mrq->cmd->data) {
3942 + sizes = mrq->cmd->data->blocks * mrq->cmd->data->blksz;
3943 + bRx = mrq->cmd->data->flags & MMC_DATA_READ ? 1 : 0 ;
3944 + } else {
3945 + bRx = mrq->cmd->arg & 0x80000000 ? 1 : 0;
3946 + }
3947 +
3948 + if (!mrq->cmd->error) {
3949 + msdc_performance(opcode, sizes, bRx, ticks);
3950 + }
3951 + }
3952 + }
3953 +#endif /* end of --- */
3954 + spin_unlock(&host->lock);
3955 +
3956 + mmc_request_done(mmc, mrq);
3957 +
3958 + return;
3959 +}
3960 +
3961 +/* called by ops.set_ios */
3962 +static void msdc_set_buswidth(struct msdc_host *host, u32 width)
3963 +{
3964 + u32 base = host->base;
3965 + u32 val = sdr_read32(SDC_CFG);
3966 +
3967 + val &= ~SDC_CFG_BUSWIDTH;
3968 +
3969 + switch (width) {
3970 + default:
3971 + case MMC_BUS_WIDTH_1:
3972 + width = 1;
3973 + val |= (MSDC_BUS_1BITS << 16);
3974 + break;
3975 + case MMC_BUS_WIDTH_4:
3976 + val |= (MSDC_BUS_4BITS << 16);
3977 + break;
3978 + case MMC_BUS_WIDTH_8:
3979 + val |= (MSDC_BUS_8BITS << 16);
3980 + break;
3981 + }
3982 +
3983 + sdr_write32(SDC_CFG, val);
3984 +
3985 + N_MSG(CFG, "Bus Width = %d", width);
3986 +}
3987 +
3988 +/* ops.set_ios */
3989 +static void msdc_ops_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
3990 +{
3991 + struct msdc_host *host = mmc_priv(mmc);
3992 + struct msdc_hw *hw=host->hw;
3993 + u32 base = host->base;
3994 + u32 ddr = 0;
3995 +
3996 +#ifdef MT6575_SD_DEBUG
3997 + static char *vdd[] = {
3998 + "1.50v", "1.55v", "1.60v", "1.65v", "1.70v", "1.80v", "1.90v",
3999 + "2.00v", "2.10v", "2.20v", "2.30v", "2.40v", "2.50v", "2.60v",
4000 + "2.70v", "2.80v", "2.90v", "3.00v", "3.10v", "3.20v", "3.30v",
4001 + "3.40v", "3.50v", "3.60v"
4002 + };
4003 + static char *power_mode[] = {
4004 + "OFF", "UP", "ON"
4005 + };
4006 + static char *bus_mode[] = {
4007 + "UNKNOWN", "OPENDRAIN", "PUSHPULL"
4008 + };
4009 + static char *timing[] = {
4010 + "LEGACY", "MMC_HS", "SD_HS"
4011 + };
4012 +
4013 + N_MSG(CFG, "SET_IOS: CLK(%dkHz), BUS(%s), BW(%u), PWR(%s), VDD(%s), TIMING(%s)",
4014 + ios->clock / 1000, bus_mode[ios->bus_mode],
4015 + (ios->bus_width == MMC_BUS_WIDTH_4) ? 4 : 1,
4016 + power_mode[ios->power_mode], vdd[ios->vdd], timing[ios->timing]);
4017 +#endif
4018 +
4019 + msdc_set_buswidth(host, ios->bus_width);
4020 +
4021 + /* Power control ??? */
4022 + switch (ios->power_mode) {
4023 + case MMC_POWER_OFF:
4024 + case MMC_POWER_UP:
4025 + // msdc_set_power_mode(host, ios->power_mode); /* --- by chhung */
4026 + break;
4027 + case MMC_POWER_ON:
4028 + host->power_mode = MMC_POWER_ON;
4029 + break;
4030 + default:
4031 + break;
4032 + }
4033 +
4034 + /* Clock control */
4035 + if (host->mclk != ios->clock) {
4036 + if(ios->clock > 25000000) {
4037 + //if (!(host->hw->flags & MSDC_REMOVABLE)) {
4038 + INIT_MSG("SD data latch edge<%d>", hw->data_edge);
4039 + sdr_set_field(MSDC_IOCON, MSDC_IOCON_RSPL, hw->cmd_edge);
4040 + sdr_set_field(MSDC_IOCON, MSDC_IOCON_DSPL, hw->data_edge);
4041 + //} /* for tuning debug */
4042 + } else { /* default value */
4043 + sdr_write32(MSDC_IOCON, 0x00000000);
4044 + // sdr_write32(MSDC_DAT_RDDLY0, 0x00000000);
4045 + sdr_write32(MSDC_DAT_RDDLY0, 0x10101010); // for MT7620 E2 and afterward
4046 + sdr_write32(MSDC_DAT_RDDLY1, 0x00000000);
4047 + // sdr_write32(MSDC_PAD_TUNE, 0x00000000);
4048 + sdr_write32(MSDC_PAD_TUNE, 0x84101010); // for MT7620 E2 and afterward
4049 + }
4050 + msdc_set_mclk(host, ddr, ios->clock);
4051 + }
4052 +}
4053 +
4054 +/* ops.get_ro */
4055 +static int msdc_ops_get_ro(struct mmc_host *mmc)
4056 +{
4057 + struct msdc_host *host = mmc_priv(mmc);
4058 + u32 base = host->base;
4059 + unsigned long flags;
4060 + int ro = 0;
4061 +
4062 + if (host->hw->flags & MSDC_WP_PIN_EN) { /* set for card */
4063 + spin_lock_irqsave(&host->lock, flags);
4064 + ro = (sdr_read32(MSDC_PS) >> 31);
4065 + spin_unlock_irqrestore(&host->lock, flags);
4066 + }
4067 + return ro;
4068 +}
4069 +
4070 +/* ops.get_cd */
4071 +static int msdc_ops_get_cd(struct mmc_host *mmc)
4072 +{
4073 + struct msdc_host *host = mmc_priv(mmc);
4074 + u32 base = host->base;
4075 + unsigned long flags;
4076 + int present = 1;
4077 +
4078 + /* for sdio, MSDC_REMOVABLE not set, always return 1 */
4079 + if (!(host->hw->flags & MSDC_REMOVABLE)) {
4080 + /* For sdio, read H/W always get<1>, but may timeout some times */
4081 +#if 1
4082 + host->card_inserted = 1;
4083 + return 1;
4084 +#else
4085 + host->card_inserted = (host->pm_state.event == PM_EVENT_USER_RESUME) ? 1 : 0;
4086 + INIT_MSG("sdio ops_get_cd<%d>", host->card_inserted);
4087 + return host->card_inserted;
4088 +#endif
4089 + }
4090 +
4091 + /* MSDC_CD_PIN_EN set for card */
4092 + if (host->hw->flags & MSDC_CD_PIN_EN) {
4093 + spin_lock_irqsave(&host->lock, flags);
4094 +#if 0
4095 + present = host->card_inserted; /* why not read from H/W: Fix me*/
4096 +#else
4097 + present = (sdr_read32(MSDC_PS) & MSDC_PS_CDSTS) ? 0 : 1;
4098 + host->card_inserted = present;
4099 +#endif
4100 + spin_unlock_irqrestore(&host->lock, flags);
4101 + } else {
4102 + present = 0; /* TODO? Check DAT3 pins for card detection */
4103 + }
4104 +
4105 + INIT_MSG("ops_get_cd return<%d>", present);
4106 + return present;
4107 +}
4108 +
4109 +/* ops.enable_sdio_irq */
4110 +static void msdc_ops_enable_sdio_irq(struct mmc_host *mmc, int enable)
4111 +{
4112 + struct msdc_host *host = mmc_priv(mmc);
4113 + struct msdc_hw *hw = host->hw;
4114 + u32 base = host->base;
4115 + u32 tmp;
4116 +
4117 + if (hw->flags & MSDC_EXT_SDIO_IRQ) { /* yes for sdio */
4118 + if (enable) {
4119 + hw->enable_sdio_eirq(); /* combo_sdio_enable_eirq */
4120 + } else {
4121 + hw->disable_sdio_eirq(); /* combo_sdio_disable_eirq */
4122 + }
4123 + } else {
4124 + ERR_MSG("XXX "); /* so never enter here */
4125 + tmp = sdr_read32(SDC_CFG);
4126 + /* FIXME. Need to interrupt gap detection */
4127 + if (enable) {
4128 + tmp |= (SDC_CFG_SDIOIDE | SDC_CFG_SDIOINTWKUP);
4129 + } else {
4130 + tmp &= ~(SDC_CFG_SDIOIDE | SDC_CFG_SDIOINTWKUP);
4131 + }
4132 + sdr_write32(SDC_CFG, tmp);
4133 + }
4134 +}
4135 +
4136 +static struct mmc_host_ops mt_msdc_ops = {
4137 + .request = msdc_ops_request,
4138 + .set_ios = msdc_ops_set_ios,
4139 + .get_ro = msdc_ops_get_ro,
4140 + .get_cd = msdc_ops_get_cd,
4141 + .enable_sdio_irq = msdc_ops_enable_sdio_irq,
4142 +};
4143 +
4144 +/*--------------------------------------------------------------------------*/
4145 +/* interrupt handler */
4146 +/*--------------------------------------------------------------------------*/
4147 +static irqreturn_t msdc_irq(int irq, void *dev_id)
4148 +{
4149 + struct msdc_host *host = (struct msdc_host *)dev_id;
4150 + struct mmc_data *data = host->data;
4151 + struct mmc_command *cmd = host->cmd;
4152 + u32 base = host->base;
4153 +
4154 + u32 cmdsts = MSDC_INT_RSPCRCERR | MSDC_INT_CMDTMO | MSDC_INT_CMDRDY |
4155 + MSDC_INT_ACMDCRCERR | MSDC_INT_ACMDTMO | MSDC_INT_ACMDRDY |
4156 + MSDC_INT_ACMD19_DONE;
4157 + u32 datsts = MSDC_INT_DATCRCERR |MSDC_INT_DATTMO;
4158 +
4159 + u32 intsts = sdr_read32(MSDC_INT);
4160 + u32 inten = sdr_read32(MSDC_INTEN); inten &= intsts;
4161 +
4162 + sdr_write32(MSDC_INT, intsts); /* clear interrupts */
4163 + /* MSG will cause fatal error */
4164 +
4165 + /* card change interrupt */
4166 + if (intsts & MSDC_INT_CDSC){
4167 +#if defined CONFIG_MTK_MMC_CD_POLL
4168 + return IRQ_HANDLED;
4169 +#endif
4170 + IRQ_MSG("MSDC_INT_CDSC irq<0x%.8x>", intsts);
4171 +#if 0 /* ---/+++ by chhung: fix slot mechanical bounce issue */
4172 + tasklet_hi_schedule(&host->card_tasklet);
4173 +#else
4174 + schedule_delayed_work(&host->card_delaywork, HZ);
4175 +#endif
4176 + /* tuning when plug card ? */
4177 + }
4178 +
4179 + /* sdio interrupt */
4180 + if (intsts & MSDC_INT_SDIOIRQ){
4181 + IRQ_MSG("XXX MSDC_INT_SDIOIRQ"); /* seems not sdio irq */
4182 + //mmc_signal_sdio_irq(host->mmc);
4183 + }
4184 +
4185 + /* transfer complete interrupt */
4186 + if (data != NULL) {
4187 + if (inten & MSDC_INT_XFER_COMPL) {
4188 + data->bytes_xfered = host->dma.xfersz;
4189 + complete(&host->xfer_done);
4190 + }
4191 +
4192 + if (intsts & datsts) {
4193 + /* do basic reset, or stop command will sdc_busy */
4194 + msdc_reset();
4195 + msdc_clr_fifo();
4196 + msdc_clr_int();
4197 + atomic_set(&host->abort, 1); /* For PIO mode exit */
4198 +
4199 + if (intsts & MSDC_INT_DATTMO){
4200 + IRQ_MSG("XXX CMD<%d> MSDC_INT_DATTMO", host->mrq->cmd->opcode);
4201 + data->error = (unsigned int)-ETIMEDOUT;
4202 + }
4203 + else if (intsts & MSDC_INT_DATCRCERR){
4204 + IRQ_MSG("XXX CMD<%d> MSDC_INT_DATCRCERR, SDC_DCRC_STS<0x%x>", host->mrq->cmd->opcode, sdr_read32(SDC_DCRC_STS));
4205 + data->error = (unsigned int)-EIO;
4206 + }
4207 +
4208 + //if(sdr_read32(MSDC_INTEN) & MSDC_INT_XFER_COMPL) {
4209 + if (host->dma_xfer) {
4210 + complete(&host->xfer_done); /* Read CRC come fast, XFER_COMPL not enabled */
4211 + } /* PIO mode can't do complete, because not init */
4212 + }
4213 + }
4214 +
4215 + /* command interrupts */
4216 + if ((cmd != NULL) && (intsts & cmdsts)) {
4217 + if ((intsts & MSDC_INT_CMDRDY) || (intsts & MSDC_INT_ACMDRDY) ||
4218 + (intsts & MSDC_INT_ACMD19_DONE)) {
4219 + u32 *rsp = &cmd->resp[0];
4220 +
4221 + switch (host->cmd_rsp) {
4222 + case RESP_NONE:
4223 + break;
4224 + case RESP_R2:
4225 + *rsp++ = sdr_read32(SDC_RESP3); *rsp++ = sdr_read32(SDC_RESP2);
4226 + *rsp++ = sdr_read32(SDC_RESP1); *rsp++ = sdr_read32(SDC_RESP0);
4227 + break;
4228 + default: /* Response types 1, 3, 4, 5, 6, 7(1b) */
4229 + if ((intsts & MSDC_INT_ACMDRDY) || (intsts & MSDC_INT_ACMD19_DONE)) {
4230 + *rsp = sdr_read32(SDC_ACMD_RESP);
4231 + } else {
4232 + *rsp = sdr_read32(SDC_RESP0);
4233 + }
4234 + break;
4235 + }
4236 + } else if ((intsts & MSDC_INT_RSPCRCERR) || (intsts & MSDC_INT_ACMDCRCERR)) {
4237 + if(intsts & MSDC_INT_ACMDCRCERR){
4238 + IRQ_MSG("XXX CMD<%d> MSDC_INT_ACMDCRCERR",cmd->opcode);
4239 + }
4240 + else {
4241 + IRQ_MSG("XXX CMD<%d> MSDC_INT_RSPCRCERR",cmd->opcode);
4242 + }
4243 + cmd->error = (unsigned int)-EIO;
4244 + } else if ((intsts & MSDC_INT_CMDTMO) || (intsts & MSDC_INT_ACMDTMO)) {
4245 + if(intsts & MSDC_INT_ACMDTMO){
4246 + IRQ_MSG("XXX CMD<%d> MSDC_INT_ACMDTMO",cmd->opcode);
4247 + }
4248 + else {
4249 + IRQ_MSG("XXX CMD<%d> MSDC_INT_CMDTMO",cmd->opcode);
4250 + }
4251 + cmd->error = (unsigned int)-ETIMEDOUT;
4252 + msdc_reset();
4253 + msdc_clr_fifo();
4254 + msdc_clr_int();
4255 + }
4256 + complete(&host->cmd_done);
4257 + }
4258 +
4259 + /* mmc irq interrupts */
4260 + if (intsts & MSDC_INT_MMCIRQ) {
4261 + printk(KERN_INFO "msdc[%d] MMCIRQ: SDC_CSTS=0x%.8x\r\n", host->id, sdr_read32(SDC_CSTS));
4262 + }
4263 +
4264 +#ifdef MT6575_SD_DEBUG
4265 + {
4266 + msdc_int_reg *int_reg = (msdc_int_reg*)&intsts;
4267 + N_MSG(INT, "IRQ_EVT(0x%x): MMCIRQ(%d) CDSC(%d), ACRDY(%d), ACTMO(%d), ACCRE(%d) AC19DN(%d)",
4268 + intsts,
4269 + int_reg->mmcirq,
4270 + int_reg->cdsc,
4271 + int_reg->atocmdrdy,
4272 + int_reg->atocmdtmo,
4273 + int_reg->atocmdcrc,
4274 + int_reg->atocmd19done);
4275 + N_MSG(INT, "IRQ_EVT(0x%x): SDIO(%d) CMDRDY(%d), CMDTMO(%d), RSPCRC(%d), CSTA(%d)",
4276 + intsts,
4277 + int_reg->sdioirq,
4278 + int_reg->cmdrdy,
4279 + int_reg->cmdtmo,
4280 + int_reg->rspcrc,
4281 + int_reg->csta);
4282 + N_MSG(INT, "IRQ_EVT(0x%x): XFCMP(%d) DXDONE(%d), DATTMO(%d), DATCRC(%d), DMAEMP(%d)",
4283 + intsts,
4284 + int_reg->xfercomp,
4285 + int_reg->dxferdone,
4286 + int_reg->dattmo,
4287 + int_reg->datcrc,
4288 + int_reg->dmaqempty);
4289 +
4290 + }
4291 +#endif
4292 +
4293 + return IRQ_HANDLED;
4294 +}
4295 +
4296 +/*--------------------------------------------------------------------------*/
4297 +/* platform_driver members */
4298 +/*--------------------------------------------------------------------------*/
4299 +/* called by msdc_drv_probe/remove */
4300 +static void msdc_enable_cd_irq(struct msdc_host *host, int enable)
4301 +{
4302 + struct msdc_hw *hw = host->hw;
4303 + u32 base = host->base;
4304 +
4305 + /* for sdio, not set */
4306 + if ((hw->flags & MSDC_CD_PIN_EN) == 0) {
4307 + /* Pull down card detection pin since it is not avaiable */
4308 + /*
4309 + if (hw->config_gpio_pin)
4310 + hw->config_gpio_pin(MSDC_CD_PIN, GPIO_PULL_DOWN);
4311 + */
4312 + sdr_clr_bits(MSDC_PS, MSDC_PS_CDEN);
4313 + sdr_clr_bits(MSDC_INTEN, MSDC_INTEN_CDSC);
4314 + sdr_clr_bits(SDC_CFG, SDC_CFG_INSWKUP);
4315 + return;
4316 + }
4317 +
4318 + N_MSG(CFG, "CD IRQ Eanable(%d)", enable);
4319 +
4320 + if (enable) {
4321 + if (hw->enable_cd_eirq) { /* not set, never enter */
4322 + hw->enable_cd_eirq();
4323 + } else {
4324 + /* card detection circuit relies on the core power so that the core power
4325 + * shouldn't be turned off. Here adds a reference count to keep
4326 + * the core power alive.
4327 + */
4328 + //msdc_vcore_on(host); //did in msdc_init_hw()
4329 +
4330 + if (hw->config_gpio_pin) /* NULL */
4331 + hw->config_gpio_pin(MSDC_CD_PIN, GPIO_PULL_UP);
4332 +
4333 + sdr_set_field(MSDC_PS, MSDC_PS_CDDEBOUNCE, DEFAULT_DEBOUNCE);
4334 + sdr_set_bits(MSDC_PS, MSDC_PS_CDEN);
4335 + sdr_set_bits(MSDC_INTEN, MSDC_INTEN_CDSC);
4336 + sdr_set_bits(SDC_CFG, SDC_CFG_INSWKUP); /* not in document! Fix me */
4337 + }
4338 + } else {
4339 + if (hw->disable_cd_eirq) {
4340 + hw->disable_cd_eirq();
4341 + } else {
4342 + if (hw->config_gpio_pin) /* NULL */
4343 + hw->config_gpio_pin(MSDC_CD_PIN, GPIO_PULL_DOWN);
4344 +
4345 + sdr_clr_bits(SDC_CFG, SDC_CFG_INSWKUP);
4346 + sdr_clr_bits(MSDC_PS, MSDC_PS_CDEN);
4347 + sdr_clr_bits(MSDC_INTEN, MSDC_INTEN_CDSC);
4348 +
4349 + /* Here decreases a reference count to core power since card
4350 + * detection circuit is shutdown.
4351 + */
4352 + //msdc_vcore_off(host);
4353 + }
4354 + }
4355 +}
4356 +
4357 +/* called by msdc_drv_probe */
4358 +static void msdc_init_hw(struct msdc_host *host)
4359 +{
4360 + u32 base = host->base;
4361 + struct msdc_hw *hw = host->hw;
4362 +
4363 +#ifdef MT6575_SD_DEBUG
4364 + msdc_reg[host->id] = (struct msdc_regs *)host->base;
4365 +#endif
4366 +
4367 + /* Power on */
4368 +#if 0 /* --- by chhung */
4369 + msdc_vcore_on(host);
4370 + msdc_pin_reset(host, MSDC_PIN_PULL_UP);
4371 + msdc_select_clksrc(host, hw->clk_src);
4372 + enable_clock(PERI_MSDC0_PDN + host->id, "SD");
4373 + msdc_vdd_on(host);
4374 +#endif /* end of --- */
4375 + /* Configure to MMC/SD mode */
4376 + sdr_set_field(MSDC_CFG, MSDC_CFG_MODE, MSDC_SDMMC);
4377 +
4378 + /* Reset */
4379 + msdc_reset();
4380 + msdc_clr_fifo();
4381 +
4382 + /* Disable card detection */
4383 + sdr_clr_bits(MSDC_PS, MSDC_PS_CDEN);
4384 +
4385 + /* Disable and clear all interrupts */
4386 + sdr_clr_bits(MSDC_INTEN, sdr_read32(MSDC_INTEN));
4387 + sdr_write32(MSDC_INT, sdr_read32(MSDC_INT));
4388 +
4389 +#if 1
4390 + /* reset tuning parameter */
4391 + sdr_write32(MSDC_PAD_CTL0, 0x00090000);
4392 + sdr_write32(MSDC_PAD_CTL1, 0x000A0000);
4393 + sdr_write32(MSDC_PAD_CTL2, 0x000A0000);
4394 + // sdr_write32(MSDC_PAD_TUNE, 0x00000000);
4395 + sdr_write32(MSDC_PAD_TUNE, 0x84101010); // for MT7620 E2 and afterward
4396 + // sdr_write32(MSDC_DAT_RDDLY0, 0x00000000);
4397 + sdr_write32(MSDC_DAT_RDDLY0, 0x10101010); // for MT7620 E2 and afterward
4398 + sdr_write32(MSDC_DAT_RDDLY1, 0x00000000);
4399 + sdr_write32(MSDC_IOCON, 0x00000000);
4400 +#if 0 // use MT7620 default value: 0x403c004f
4401 + sdr_write32(MSDC_PATCH_BIT0, 0x003C000F); /* bit0 modified: Rx Data Clock Source: 1 -> 2.0*/
4402 +#endif
4403 +
4404 + if (sdr_read32(MSDC_ECO_VER) >= 4) {
4405 + if (host->id == 1) {
4406 + sdr_set_field(MSDC_PATCH_BIT1, MSDC_PATCH_BIT1_WRDAT_CRCS, 1);
4407 + sdr_set_field(MSDC_PATCH_BIT1, MSDC_PATCH_BIT1_CMD_RSP, 1);
4408 +
4409 + /* internal clock: latch read data */
4410 + sdr_set_bits(MSDC_PATCH_BIT0, MSDC_PATCH_BIT_CKGEN_CK);
4411 + }
4412 + }
4413 +#endif
4414 +
4415 + /* for safety, should clear SDC_CFG.SDIO_INT_DET_EN & set SDC_CFG.SDIO in
4416 + pre-loader,uboot,kernel drivers. and SDC_CFG.SDIO_INT_DET_EN will be only
4417 + set when kernel driver wants to use SDIO bus interrupt */
4418 + /* Configure to enable SDIO mode. it's must otherwise sdio cmd5 failed */
4419 + sdr_set_bits(SDC_CFG, SDC_CFG_SDIO);
4420 +
4421 + /* disable detect SDIO device interupt function */
4422 + sdr_clr_bits(SDC_CFG, SDC_CFG_SDIOIDE);
4423 +
4424 + /* eneable SMT for glitch filter */
4425 + sdr_set_bits(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKSMT);
4426 + sdr_set_bits(MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDSMT);
4427 + sdr_set_bits(MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATSMT);
4428 +
4429 +#if 1
4430 + /* set clk, cmd, dat pad driving */
4431 + sdr_set_field(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKDRVN, hw->clk_drv);
4432 + sdr_set_field(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKDRVP, hw->clk_drv);
4433 + sdr_set_field(MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDDRVN, hw->cmd_drv);
4434 + sdr_set_field(MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDDRVP, hw->cmd_drv);
4435 + sdr_set_field(MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATDRVN, hw->dat_drv);
4436 + sdr_set_field(MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATDRVP, hw->dat_drv);
4437 +#else
4438 + sdr_set_field(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKDRVN, 0);
4439 + sdr_set_field(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKDRVP, 0);
4440 + sdr_set_field(MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDDRVN, 0);
4441 + sdr_set_field(MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDDRVP, 0);
4442 + sdr_set_field(MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATDRVN, 0);
4443 + sdr_set_field(MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATDRVP, 0);
4444 +#endif
4445 +
4446 + /* set sampling edge */
4447 +
4448 + /* write crc timeout detection */
4449 + sdr_set_field(MSDC_PATCH_BIT0, 1 << 30, 1);
4450 +
4451 + /* Configure to default data timeout */
4452 + sdr_set_field(SDC_CFG, SDC_CFG_DTOC, DEFAULT_DTOC);
4453 +
4454 + msdc_set_buswidth(host, MMC_BUS_WIDTH_1);
4455 +
4456 + N_MSG(FUC, "init hardware done!");
4457 +}
4458 +
4459 +/* called by msdc_drv_remove */
4460 +static void msdc_deinit_hw(struct msdc_host *host)
4461 +{
4462 + u32 base = host->base;
4463 +
4464 + /* Disable and clear all interrupts */
4465 + sdr_clr_bits(MSDC_INTEN, sdr_read32(MSDC_INTEN));
4466 + sdr_write32(MSDC_INT, sdr_read32(MSDC_INT));
4467 +
4468 + /* Disable card detection */
4469 + msdc_enable_cd_irq(host, 0);
4470 + // msdc_set_power_mode(host, MMC_POWER_OFF); /* make sure power down */ /* --- by chhung */
4471 +}
4472 +
4473 +/* init gpd and bd list in msdc_drv_probe */
4474 +static void msdc_init_gpd_bd(struct msdc_host *host, struct msdc_dma *dma)
4475 +{
4476 + gpd_t *gpd = dma->gpd;
4477 + bd_t *bd = dma->bd;
4478 + bd_t *ptr, *prev;
4479 +
4480 + /* we just support one gpd */
4481 + int bdlen = MAX_BD_PER_GPD;
4482 +
4483 + /* init the 2 gpd */
4484 + memset(gpd, 0, sizeof(gpd_t) * 2);
4485 + //gpd->next = (void *)virt_to_phys(gpd + 1); /* pointer to a null gpd, bug! kmalloc <-> virt_to_phys */
4486 + //gpd->next = (dma->gpd_addr + 1); /* bug */
4487 + gpd->next = (void *)((u32)dma->gpd_addr + sizeof(gpd_t));
4488 +
4489 + //gpd->intr = 0;
4490 + gpd->bdp = 1; /* hwo, cs, bd pointer */
4491 + //gpd->ptr = (void*)virt_to_phys(bd);
4492 + gpd->ptr = (void *)dma->bd_addr; /* physical address */
4493 +
4494 + memset(bd, 0, sizeof(bd_t) * bdlen);
4495 + ptr = bd + bdlen - 1;
4496 + //ptr->eol = 1; /* 0 or 1 [Fix me]*/
4497 + //ptr->next = 0;
4498 +
4499 + while (ptr != bd) {
4500 + prev = ptr - 1;
4501 + prev->next = (void *)(dma->bd_addr + sizeof(bd_t) *(ptr - bd));
4502 + ptr = prev;
4503 + }
4504 +}
4505 +
4506 +static int msdc_drv_probe(struct platform_device *pdev)
4507 +{
4508 + struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
4509 + __iomem void *base;
4510 + struct mmc_host *mmc;
4511 + struct resource *mem;
4512 + struct msdc_host *host;
4513 + struct msdc_hw *hw;
4514 + int ret, irq;
4515 +
4516 + pdev->dev.platform_data = &msdc0_hw;
4517 +
4518 + /* Allocate MMC host for this device */
4519 + mmc = mmc_alloc_host(sizeof(struct msdc_host), &pdev->dev);
4520 + if (!mmc) return -ENOMEM;
4521 +
4522 + hw = (struct msdc_hw*)pdev->dev.platform_data;
4523 + mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
4524 + irq = platform_get_irq(pdev, 0);
4525 +
4526 + //BUG_ON((!hw) || (!mem) || (irq < 0)); /* --- by chhung */
4527 +
4528 + base = devm_request_and_ioremap(&pdev->dev, res);
4529 + if (IS_ERR(base))
4530 + return PTR_ERR(base);
4531 +
4532 + /* Set host parameters to mmc */
4533 + mmc->ops = &mt_msdc_ops;
4534 + mmc->f_min = HOST_MIN_MCLK;
4535 + mmc->f_max = HOST_MAX_MCLK;
4536 + mmc->ocr_avail = MSDC_OCR_AVAIL;
4537 +
4538 + /* For sd card: MSDC_SYS_SUSPEND | MSDC_WP_PIN_EN | MSDC_CD_PIN_EN | MSDC_REMOVABLE | MSDC_HIGHSPEED,
4539 + For sdio : MSDC_EXT_SDIO_IRQ | MSDC_HIGHSPEED */
4540 + if (hw->flags & MSDC_HIGHSPEED) {
4541 + mmc->caps = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED;
4542 + }
4543 + if (hw->data_pins == 4) { /* current data_pins are all 4*/
4544 + mmc->caps |= MMC_CAP_4_BIT_DATA;
4545 + } else if (hw->data_pins == 8) {
4546 + mmc->caps |= MMC_CAP_8_BIT_DATA;
4547 + }
4548 + if ((hw->flags & MSDC_SDIO_IRQ) || (hw->flags & MSDC_EXT_SDIO_IRQ))
4549 + mmc->caps |= MMC_CAP_SDIO_IRQ; /* yes for sdio */
4550 +
4551 +#if defined CONFIG_MTK_MMC_CD_POLL
4552 + mmc->caps |= MMC_CAP_NEEDS_POLL;
4553 +#endif
4554 +
4555 + /* MMC core transfer sizes tunable parameters */
4556 +#if LINUX_VERSION_CODE > KERNEL_VERSION(3,10,0)
4557 + mmc->max_segs = MAX_HW_SGMTS;
4558 +#else
4559 + mmc->max_hw_segs = MAX_HW_SGMTS;
4560 + mmc->max_phys_segs = MAX_PHY_SGMTS;
4561 +#endif
4562 + mmc->max_seg_size = MAX_SGMT_SZ;
4563 + mmc->max_blk_size = HOST_MAX_BLKSZ;
4564 + mmc->max_req_size = MAX_REQ_SZ;
4565 + mmc->max_blk_count = mmc->max_req_size;
4566 +
4567 + host = mmc_priv(mmc);
4568 + host->hw = hw;
4569 + host->mmc = mmc;
4570 + host->id = pdev->id;
4571 + host->error = 0;
4572 + host->irq = irq;
4573 + host->base = (unsigned long) base;
4574 + host->mclk = 0; /* mclk: the request clock of mmc sub-system */
4575 + host->hclk = hclks[hw->clk_src]; /* hclk: clock of clock source to msdc controller */
4576 + host->sclk = 0; /* sclk: the really clock after divition */
4577 + host->pm_state = PMSG_RESUME;
4578 + host->suspend = 0;
4579 + host->core_clkon = 0;
4580 + host->card_clkon = 0;
4581 + host->core_power = 0;
4582 + host->power_mode = MMC_POWER_OFF;
4583 +// host->card_inserted = hw->flags & MSDC_REMOVABLE ? 0 : 1;
4584 + host->timeout_ns = 0;
4585 + host->timeout_clks = DEFAULT_DTOC * 65536;
4586 +
4587 + host->mrq = NULL;
4588 + //init_MUTEX(&host->sem); /* we don't need to support multiple threads access */
4589 +
4590 + host->dma.used_gpd = 0;
4591 + host->dma.used_bd = 0;
4592 +
4593 + /* using dma_alloc_coherent*/ /* todo: using 1, for all 4 slots */
4594 + host->dma.gpd = dma_alloc_coherent(NULL, MAX_GPD_NUM * sizeof(gpd_t), &host->dma.gpd_addr, GFP_KERNEL);
4595 + host->dma.bd = dma_alloc_coherent(NULL, MAX_BD_NUM * sizeof(bd_t), &host->dma.bd_addr, GFP_KERNEL);
4596 + BUG_ON((!host->dma.gpd) || (!host->dma.bd));
4597 + msdc_init_gpd_bd(host, &host->dma);
4598 + /*for emmc*/
4599 + msdc_6575_host[pdev->id] = host;
4600 +
4601 +#if 0
4602 + tasklet_init(&host->card_tasklet, msdc_tasklet_card, (ulong)host);
4603 +#else
4604 + INIT_DELAYED_WORK(&host->card_delaywork, msdc_tasklet_card);
4605 +#endif
4606 + spin_lock_init(&host->lock);
4607 + msdc_init_hw(host);
4608 +
4609 + ret = request_irq((unsigned int)irq, msdc_irq, IRQF_TRIGGER_LOW, dev_name(&pdev->dev), host);
4610 + if (ret) goto release;
4611 + // mt65xx_irq_unmask(irq); /* --- by chhung */
4612 +
4613 + if (hw->flags & MSDC_CD_PIN_EN) { /* not set for sdio */
4614 + if (hw->request_cd_eirq) { /* not set for MT6575 */
4615 + hw->request_cd_eirq(msdc_eirq_cd, (void*)host); /* msdc_eirq_cd will not be used! */
4616 + }
4617 + }
4618 +
4619 + if (hw->request_sdio_eirq) /* set to combo_sdio_request_eirq() for WIFI */
4620 + hw->request_sdio_eirq(msdc_eirq_sdio, (void*)host); /* msdc_eirq_sdio() will be called when EIRQ */
4621 +
4622 + if (hw->register_pm) {/* yes for sdio */
4623 +#ifdef CONFIG_PM
4624 + hw->register_pm(msdc_pm, (void*)host); /* combo_sdio_register_pm() */
4625 +#endif
4626 + if(hw->flags & MSDC_SYS_SUSPEND) { /* will not set for WIFI */
4627 + ERR_MSG("MSDC_SYS_SUSPEND and register_pm both set");
4628 + }
4629 + //mmc->pm_flags |= MMC_PM_IGNORE_PM_NOTIFY; /* pm not controlled by system but by client. */ /* --- by chhung */
4630 + }
4631 +
4632 + platform_set_drvdata(pdev, mmc);
4633 +
4634 + ret = mmc_add_host(mmc);
4635 + if (ret) goto free_irq;
4636 +
4637 + /* Config card detection pin and enable interrupts */
4638 + if (hw->flags & MSDC_CD_PIN_EN) { /* set for card */
4639 + msdc_enable_cd_irq(host, 1);
4640 + } else {
4641 + msdc_enable_cd_irq(host, 0);
4642 + }
4643 +
4644 + return 0;
4645 +
4646 +free_irq:
4647 + free_irq(irq, host);
4648 +release:
4649 + platform_set_drvdata(pdev, NULL);
4650 + msdc_deinit_hw(host);
4651 +
4652 +#if 0
4653 + tasklet_kill(&host->card_tasklet);
4654 +#else
4655 + cancel_delayed_work_sync(&host->card_delaywork);
4656 +#endif
4657 +
4658 + if (mem)
4659 + release_mem_region(mem->start, mem->end - mem->start + 1);
4660 +
4661 + mmc_free_host(mmc);
4662 +
4663 + return ret;
4664 +}
4665 +
4666 +/* 4 device share one driver, using "drvdata" to show difference */
4667 +static int msdc_drv_remove(struct platform_device *pdev)
4668 +{
4669 + struct mmc_host *mmc;
4670 + struct msdc_host *host;
4671 + struct resource *mem;
4672 +
4673 + mmc = platform_get_drvdata(pdev);
4674 + BUG_ON(!mmc);
4675 +
4676 + host = mmc_priv(mmc);
4677 + BUG_ON(!host);
4678 +
4679 + ERR_MSG("removed !!!");
4680 +
4681 + platform_set_drvdata(pdev, NULL);
4682 + mmc_remove_host(host->mmc);
4683 + msdc_deinit_hw(host);
4684 +
4685 +#if 0
4686 + tasklet_kill(&host->card_tasklet);
4687 +#else
4688 + cancel_delayed_work_sync(&host->card_delaywork);
4689 +#endif
4690 + free_irq(host->irq, host);
4691 +
4692 + dma_free_coherent(NULL, MAX_GPD_NUM * sizeof(gpd_t), host->dma.gpd, host->dma.gpd_addr);
4693 + dma_free_coherent(NULL, MAX_BD_NUM * sizeof(bd_t), host->dma.bd, host->dma.bd_addr);
4694 +
4695 + mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
4696 +
4697 + if (mem)
4698 + release_mem_region(mem->start, mem->end - mem->start + 1);
4699 +
4700 + mmc_free_host(host->mmc);
4701 +
4702 + return 0;
4703 +}
4704 +
4705 +/* Fix me: Power Flow */
4706 +#ifdef CONFIG_PM
4707 +static int msdc_drv_suspend(struct platform_device *pdev, pm_message_t state)
4708 +{
4709 + int ret = 0;
4710 + struct mmc_host *mmc = platform_get_drvdata(pdev);
4711 + struct msdc_host *host = mmc_priv(mmc);
4712 +
4713 + if (mmc && state.event == PM_EVENT_SUSPEND && (host->hw->flags & MSDC_SYS_SUSPEND)) { /* will set for card */
4714 + msdc_pm(state, (void*)host);
4715 + }
4716 +
4717 + return ret;
4718 +}
4719 +
4720 +static int msdc_drv_resume(struct platform_device *pdev)
4721 +{
4722 + int ret = 0;
4723 + struct mmc_host *mmc = platform_get_drvdata(pdev);
4724 + struct msdc_host *host = mmc_priv(mmc);
4725 + struct pm_message state;
4726 +
4727 + state.event = PM_EVENT_RESUME;
4728 + if (mmc && (host->hw->flags & MSDC_SYS_SUSPEND)) {/* will set for card */
4729 + msdc_pm(state, (void*)host);
4730 + }
4731 +
4732 + /* This mean WIFI not controller by PM */
4733 +
4734 + return ret;
4735 +}
4736 +#endif
4737 +
4738 +static const struct of_device_id mt7620a_sdhci_match[] = {
4739 + { .compatible = "ralink,mt7620a-sdhci" },
4740 + {},
4741 +};
4742 +MODULE_DEVICE_TABLE(of, rt288x_wdt_match);
4743 +
4744 +static struct platform_driver mt_msdc_driver = {
4745 + .probe = msdc_drv_probe,
4746 + .remove = msdc_drv_remove,
4747 +#ifdef CONFIG_PM
4748 + .suspend = msdc_drv_suspend,
4749 + .resume = msdc_drv_resume,
4750 +#endif
4751 + .driver = {
4752 + .name = DRV_NAME,
4753 + .owner = THIS_MODULE,
4754 + .of_match_table = mt7620a_sdhci_match,
4755 + },
4756 +};
4757 +
4758 +/*--------------------------------------------------------------------------*/
4759 +/* module init/exit */
4760 +/*--------------------------------------------------------------------------*/
4761 +static int __init mt_msdc_init(void)
4762 +{
4763 + int ret;
4764 +/* +++ by chhung */
4765 + u32 reg;
4766 +
4767 +#if defined (CONFIG_MTD_ANY_RALINK)
4768 + extern int ra_check_flash_type(void);
4769 + if(ra_check_flash_type() == 2) { /* NAND */
4770 + printk("%s: !!!!! SDXC Module Initialize Fail !!!!!", __func__);
4771 + return 0;
4772 + }
4773 +#endif
4774 + printk("MTK MSDC device init.\n");
4775 + mtk_sd_device.dev.platform_data = &msdc0_hw;
4776 +if (ralink_soc == MT762X_SOC_MT7620A || ralink_soc == MT762X_SOC_MT7621AT) {
4777 +//#if defined (CONFIG_RALINK_MT7620) || defined (CONFIG_RALINK_MT7621)
4778 + reg = sdr_read32((volatile u32*)(RALINK_SYSCTL_BASE + 0x60)) & ~(0x3<<18);
4779 +//#if defined (CONFIG_RALINK_MT7620)
4780 + if (ralink_soc == MT762X_SOC_MT7620A)
4781 + reg |= 0x1<<18;
4782 +//#endif
4783 +} else {
4784 +//#elif defined (CONFIG_RALINK_MT7628)
4785 + /* TODO: maybe omitted when RAether already toggle AGPIO_CFG */
4786 + reg = sdr_read32((volatile u32*)(RALINK_SYSCTL_BASE + 0x3c));
4787 + reg |= 0x1e << 16;
4788 + sdr_write32((volatile u32*)(RALINK_SYSCTL_BASE + 0x3c), reg);
4789 +
4790 + reg = sdr_read32((volatile u32*)(RALINK_SYSCTL_BASE + 0x60)) & ~(0x3<<10);
4791 +#if defined (CONFIG_MTK_MMC_EMMC_8BIT)
4792 + reg |= 0x3<<26 | 0x3<<28 | 0x3<<30;
4793 + msdc0_hw.data_pins = 8,
4794 +#endif
4795 +//#endif
4796 +}
4797 + sdr_write32((volatile u32*)(RALINK_SYSCTL_BASE + 0x60), reg);
4798 + platform_device_register(&mtk_sd_device);
4799 +/* end of +++ */
4800 +
4801 + ret = platform_driver_register(&mt_msdc_driver);
4802 + if (ret) {
4803 + printk(KERN_ERR DRV_NAME ": Can't register driver");
4804 + return ret;
4805 + }
4806 + printk(KERN_INFO DRV_NAME ": MediaTek MT6575 MSDC Driver\n");
4807 +
4808 +#if defined (MT6575_SD_DEBUG)
4809 + msdc_debug_proc_init();
4810 +#endif
4811 + return 0;
4812 +}
4813 +
4814 +static void __exit mt_msdc_exit(void)
4815 +{
4816 + platform_device_unregister(&mtk_sd_device);
4817 + platform_driver_unregister(&mt_msdc_driver);
4818 +}
4819 +
4820 +module_init(mt_msdc_init);
4821 +module_exit(mt_msdc_exit);
4822 +MODULE_LICENSE("GPL");
4823 +MODULE_DESCRIPTION("MediaTek MT6575 SD/MMC Card Driver");
4824 +MODULE_AUTHOR("Infinity Chen <infinity.chen@mediatek.com>");
4825 +
4826 +EXPORT_SYMBOL(msdc_6575_host);
4827 --
4828 1.7.10.4
4829
OpenWrt Source Repository