1 --- a/arch/mips/include/asm/mach-ralink/mt7620.h
2 +++ b/arch/mips/include/asm/mach-ralink/mt7620.h
4 #ifndef _MT7620_REGS_H_
5 #define _MT7620_REGS_H_
7 -enum mt762x_soc_type {
8 - MT762X_SOC_UNKNOWN = 0,
11 - MT762X_SOC_MT7628AN,
13 -extern enum mt762x_soc_type mt762x_soc;
15 #define MT7620_SYSC_BASE 0x10000000
17 #define SYSC_REG_CHIP_NAME0 0x00
18 --- a/arch/mips/include/asm/mach-ralink/ralink_regs.h
19 +++ b/arch/mips/include/asm/mach-ralink/ralink_regs.h
21 #ifndef _RALINK_REGS_H_
22 #define _RALINK_REGS_H_
24 +enum ralink_soc_type {
33 + MT762X_SOC_MT7621AT,
34 + MT762X_SOC_MT7628AN,
36 +extern enum ralink_soc_type ralink_soc;
38 extern __iomem void *rt_sysc_membase;
39 extern __iomem void *rt_memc_membase;
41 --- a/arch/mips/include/asm/mach-ralink/rt305x.h
42 +++ b/arch/mips/include/asm/mach-ralink/rt305x.h
44 #ifndef _RT305X_REGS_H_
45 #define _RT305X_REGS_H_
47 -enum rt305x_soc_type {
48 - RT305X_SOC_UNKNOWN = 0,
56 -extern enum rt305x_soc_type rt305x_soc;
57 +extern enum ralink_soc_type ralink_soc;
59 static inline int soc_is_rt3050(void)
61 - return rt305x_soc == RT305X_SOC_RT3050;
62 + return ralink_soc == RT305X_SOC_RT3050;
65 static inline int soc_is_rt3052(void)
67 - return rt305x_soc == RT305X_SOC_RT3052;
68 + return ralink_soc == RT305X_SOC_RT3052;
71 static inline int soc_is_rt305x(void)
72 @@ -41,17 +32,17 @@ static inline int soc_is_rt305x(void)
74 static inline int soc_is_rt3350(void)
76 - return rt305x_soc == RT305X_SOC_RT3350;
77 + return ralink_soc == RT305X_SOC_RT3350;
80 static inline int soc_is_rt3352(void)
82 - return rt305x_soc == RT305X_SOC_RT3352;
83 + return ralink_soc == RT305X_SOC_RT3352;
86 static inline int soc_is_rt5350(void)
88 - return rt305x_soc == RT305X_SOC_RT5350;
89 + return ralink_soc == RT305X_SOC_RT5350;
92 #define RT305X_SYSC_BASE 0x10000000
93 --- a/arch/mips/ralink/mt7620.c
94 +++ b/arch/mips/ralink/mt7620.c
96 #define CLKCFG_FFRAC_MASK 0x001f
97 #define CLKCFG_FFRAC_USB_VAL 0x0003
99 -enum mt762x_soc_type mt762x_soc;
101 /* does the board have sdram or ddram */
102 static int dram_type;
104 @@ -375,7 +373,7 @@ void __init ralink_clk_init(void)
105 #define RINT(x) ((x) / 1000000)
106 #define RFRAC(x) (((x) / 1000) % 1000)
108 - if (mt762x_soc == MT762X_SOC_MT7628AN) {
109 + if (ralink_soc == MT762X_SOC_MT7628AN) {
110 if (xtal_rate == MHZ(40))
113 @@ -418,7 +416,7 @@ void __init ralink_clk_init(void)
114 ralink_clk_add("10000c00.uartlite", periph_rate);
115 ralink_clk_add("10180000.wmac", xtal_rate);
117 - if (IS_ENABLED(CONFIG_USB) && mt762x_soc != MT762X_SOC_MT7628AN) {
118 + if (IS_ENABLED(CONFIG_USB) && ralink_soc != MT762X_SOC_MT7628AN) {
120 * When the CPU goes into sleep mode, the BUS clock will be too low for
121 * USB to function properly
122 @@ -506,11 +504,11 @@ void prom_soc_init(struct ralink_soc_inf
124 if (n0 == MT7620_CHIP_NAME0 && n1 == MT7620_CHIP_NAME1) {
126 - mt762x_soc = MT762X_SOC_MT7620A;
127 + ralink_soc = MT762X_SOC_MT7620A;
129 soc_info->compatible = "ralink,mt7620a-soc";
131 - mt762x_soc = MT762X_SOC_MT7620N;
132 + ralink_soc = MT762X_SOC_MT7620N;
134 soc_info->compatible = "ralink,mt7620n-soc";
136 @@ -518,7 +516,7 @@ void prom_soc_init(struct ralink_soc_inf
139 } else if (n0 == MT7620_CHIP_NAME0 && n1 == MT7628_CHIP_NAME1) {
140 - mt762x_soc = MT762X_SOC_MT7628AN;
141 + ralink_soc = MT762X_SOC_MT7628AN;
143 soc_info->compatible = "ralink,mt7628an-soc";
145 @@ -535,7 +533,7 @@ void prom_soc_init(struct ralink_soc_inf
146 dram_type = (cfg0 >> SYSCFG0_DRAM_TYPE_SHIFT) & SYSCFG0_DRAM_TYPE_MASK;
148 soc_info->mem_base = MT7620_DRAM_BASE;
149 - if (mt762x_soc == MT762X_SOC_MT7628AN)
150 + if (ralink_soc == MT762X_SOC_MT7628AN)
151 mt7628_dram_init(soc_info);
153 mt7620_dram_init(soc_info);
154 @@ -548,7 +546,7 @@ void prom_soc_init(struct ralink_soc_inf
155 pr_info("Digital PMU set to %s control\n",
156 (pmu1 & DIG_SW_SEL) ? ("sw") : ("hw"));
158 - if (mt762x_soc == MT762X_SOC_MT7628AN)
159 + if (ralink_soc == MT762X_SOC_MT7628AN)
160 rt2880_pinmux_data = mt7628an_pinmux_data;
162 rt2880_pinmux_data = mt7620a_pinmux_data;
163 --- a/arch/mips/ralink/rt305x.c
164 +++ b/arch/mips/ralink/rt305x.c
169 -enum rt305x_soc_type rt305x_soc;
171 static struct rt2880_pmx_func i2c_func[] = { FUNC("i2c", 0, 1, 2) };
172 static struct rt2880_pmx_func spi_func[] = { FUNC("spi", 0, 3, 4) };
173 static struct rt2880_pmx_func uartf_func[] = {
174 @@ -234,24 +232,24 @@ void prom_soc_init(struct ralink_soc_inf
176 icache_sets = (read_c0_config1() >> 22) & 7;
177 if (icache_sets == 1) {
178 - rt305x_soc = RT305X_SOC_RT3050;
179 + ralink_soc = RT305X_SOC_RT3050;
181 soc_info->compatible = "ralink,rt3050-soc";
183 - rt305x_soc = RT305X_SOC_RT3052;
184 + ralink_soc = RT305X_SOC_RT3052;
186 soc_info->compatible = "ralink,rt3052-soc";
188 } else if (n0 == RT3350_CHIP_NAME0 && n1 == RT3350_CHIP_NAME1) {
189 - rt305x_soc = RT305X_SOC_RT3350;
190 + ralink_soc = RT305X_SOC_RT3350;
192 soc_info->compatible = "ralink,rt3350-soc";
193 } else if (n0 == RT3352_CHIP_NAME0 && n1 == RT3352_CHIP_NAME1) {
194 - rt305x_soc = RT305X_SOC_RT3352;
195 + ralink_soc = RT305X_SOC_RT3352;
197 soc_info->compatible = "ralink,rt3352-soc";
198 } else if (n0 == RT5350_CHIP_NAME0 && n1 == RT5350_CHIP_NAME1) {
199 - rt305x_soc = RT305X_SOC_RT5350;
200 + ralink_soc = RT305X_SOC_RT5350;
202 soc_info->compatible = "ralink,rt5350-soc";
204 --- a/arch/mips/ralink/prom.c
205 +++ b/arch/mips/ralink/prom.c
207 #include <asm/bootinfo.h>
208 #include <asm/addrspace.h>
210 +#include <asm/mach-ralink/ralink_regs.h>
214 struct ralink_soc_info soc_info;
215 +enum ralink_soc_type ralink_soc;
216 +EXPORT_SYMBOL_GPL(ralink_soc);
218 const char *get_system_type(void)
220 --- a/arch/mips/ralink/mt7621.c
221 +++ b/arch/mips/ralink/mt7621.c
222 @@ -175,6 +175,7 @@ void prom_soc_init(struct ralink_soc_inf
223 soc_info->mem_size_min = MT7621_DDR2_SIZE_MIN;
224 soc_info->mem_size_max = MT7621_DDR2_SIZE_MAX;
225 soc_info->mem_base = MT7621_DRAM_BASE;
226 + ralink_soc = MT762X_SOC_MT7621AT;
228 rt2880_pinmux_data = mt7621_pinmux_data;