target/linux/ramips/patches-3.14/0111-i2c-MIPS-add-mt7621-I2C-driver.patch

   1 Index: linux-3.14.30/drivers/i2c/busses/Kconfig
   2 ===================================================================
   3 --- linux-3.14.30.orig/drivers/i2c/busses/Kconfig       2015-03-11 16:46:46.963996212 +0800
   4 +++ linux-3.14.30/drivers/i2c/busses/Kconfig    2015-03-12 10:40:34.849574512 +0800
   5 @@ -663,6 +663,10 @@
   6         tristate "Ralink I2C Controller"
   7         select OF_I2C
   8
   9 +config I2C_MT7621
  10 +       tristate "Mt7621 I2C Controller"
  11 +       select OF_I2C
  12 +
  13  config HAVE_S3C2410_I2C
  14         bool
  15         help
  16 Index: linux-3.14.30/drivers/i2c/busses/Makefile
  17 ===================================================================
  18 --- linux-3.14.30.orig/drivers/i2c/busses/Makefile      2015-03-11 16:46:46.967996212 +0800
  19 +++ linux-3.14.30/drivers/i2c/busses/Makefile   2015-03-11 17:52:43.008121712 +0800
  20 @@ -64,6 +64,7 @@
  21  obj-$(CONFIG_I2C_PXA)          += i2c-pxa.o
  22  obj-$(CONFIG_I2C_PXA_PCI)      += i2c-pxa-pci.o
  23  obj-$(CONFIG_I2C_RALINK)       += i2c-ralink.o
  24 +obj-$(CONFIG_I2C_MT7621)       += i2c-mt7621.o
  25  obj-$(CONFIG_I2C_RIIC)         += i2c-riic.o
  26  obj-$(CONFIG_I2C_S3C2410)      += i2c-s3c2410.o
  27  obj-$(CONFIG_I2C_S6000)                += i2c-s6000.o
  28 Index: linux-3.14.30/drivers/i2c/busses/i2c-mt7621.c
  29 ===================================================================
  30 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
  31 +++ linux-3.14.30/drivers/i2c/busses/i2c-mt7621.c       2015-03-12 11:45:00.449759139 +0800
  32 @@ -0,0 +1,358 @@
  33 +/*
  34 + * drivers/i2c/busses/i2c-mt7621.c
  35 + *
  36 + * Copyright (C) 2013 Steven Liu <steven_liu@mediatek.com>
  37 + *
  38 + * Improve driver for i2cdetect from i2c-tools to detect i2c devices on the bus.
  39 + * (C) 2014 Sittisak <sittisaks@hotmail.com>
  40 + *
  41 + * This software is licensed under the terms of the GNU General Public
  42 + * License version 2, as published by the Free Software Foundation, and
  43 + * may be copied, distributed, and modified under those terms.
  44 + *
  45 + * This program is distributed in the hope that it will be useful,
  46 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  47 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  48 + * GNU General Public License for more details.
  49 + *
  50 + */
  51 +
  52 +#include <linux/interrupt.h>
  53 +#include <linux/kernel.h>
  54 +#include <linux/module.h>
  55 +#include <linux/reset.h>
  56 +#include <linux/delay.h>
  57 +#include <linux/slab.h>
  58 +#include <linux/init.h>
  59 +#include <linux/errno.h>
  60 +#include <linux/platform_device.h>
  61 +#include <linux/i2c.h>
  62 +#include <linux/io.h>
  63 +#include <linux/err.h>
  64 +
  65 +#include <asm/mach-ralink/ralink_regs.h>
  66 +
  67 +#define REG_CONFIG_REG                       0x00
  68 +#define REG_CLKDIV_REG                       0x04
  69 +#define REG_DEVADDR_REG                      0x08
  70 +#define REG_ADDR_REG                         0x0C
  71 +#define REG_DATAOUT_REG                      0x10
  72 +#define REG_DATAIN_REG                       0x14
  73 +#define REG_STATUS_REG                       0x18
  74 +#define REG_STARTXFR_REG                     0x1C
  75 +#define REG_BYTECNT_REG                      0x20
  76 +#define REG_SM0_IS_AUTOMODE                  0x28
  77 +#define REG_SM0CTL0                          0x40
  78 +
  79 +
  80 +#define I2C_STARTERR                         0x10
  81 +#define I2C_ACKERR                           0x08
  82 +#define I2C_DATARDY                          0x04
  83 +#define I2C_SDOEMPTY                         0x02
  84 +#define I2C_BUSY                             0x01
  85 +
  86 +/* I2C_CFG register bit field */
  87 +#define I2C_CFG_ADDRLEN_8                    (7<<5)    /* 8 bits */
  88 +#define I2C_CFG_DEVADLEN_7                   (6<<2)
  89 +#define I2C_CFG_ADDRDIS                      (1<<1)
  90 +#define I2C_CFG_DEVADDIS                     (1<<0)
  91 +
  92 +#define I2C_CFG_DEFAULT        (I2C_CFG_ADDRLEN_8 | \
  93 +               I2C_CFG_DEVADLEN_7 | \
  94 +               I2C_CFG_ADDRDIS)
  95 +
  96 +#define I2C_RETRY                            0x1000
  97 +
  98 +#define CLKDIV_VALUE                         333
  99 +#define i2c_busy_loop                        (CLKDIV_VALUE*30)
 100 +
 101 +#define READ_CMD                             0x01
 102 +#define WRITE_CMD                            0x00
 103 +#define READ_BLOCK                           16
 104 +
 105 +#define I2C_OFFSET                           0x900
 106 +#define RSTCTRL_OFFSET                       0x34
 107 +
 108 +#define MT7621_REG(x)                        (*((volatile u32 *)(x)))
 109 +
 110 +struct i2c_algo_mt7621_data{
 111 +    u32 ioaddr;
 112 +    wait_queue_head_t waitq;
 113 +    spinlock_t lock;
 114 +    int id;
 115 +};
 116 +/***********************************************************/
 117 +
 118 +static unsigned long clkdiv_value = CLKDIV_VALUE;
 119 +
 120 +static void __iomem *memsysctlbase;
 121 +static void __iomem *membase;
 122 +static struct i2c_adapter *adapter;
 123 +static int i2c_id;
 124 +
 125 +static void rt_i2c_w32(u32 val, unsigned reg)
 126 +{
 127 +       iowrite32(val, membase + reg);
 128 +}
 129 +
 130 +static u32 rt_i2c_r32(unsigned reg)
 131 +{
 132 +       return ioread32(membase + reg);
 133 +}
 134 +
 135 +static void mt7621_i2c_reset(void)
 136 +{
 137 +       u32 val;
 138 +       val = MT7621_REG(RSTCTRL_OFFSET+memsysctlbase);
 139 +       val = val | (1<<16);
 140 +       MT7621_REG(RSTCTRL_OFFSET+memsysctlbase) = val;
 141 +       val = val & ~(1<<16);
 142 +       MT7621_REG(RSTCTRL_OFFSET+memsysctlbase) = val;
 143 +       udelay(500);
 144 +}
 145 +static void mt7621_i2c_enable(struct i2c_msg *msg)
 146 +{
 147 +       rt_i2c_w32(msg->addr,REG_DEVADDR_REG);
 148 +       rt_i2c_w32(0,REG_ADDR_REG);
 149 +}
 150 +
 151 +static void i2c_master_init(void)
 152 +{
 153 +       u32 value;
 154 +       /*set mt7621 i2c mode*/
 155 +       (*((volatile u32*)(memsysctlbase+0x60))) &=~0x4;
 156 +
 157 +       mt7621_i2c_reset();
 158 +       rt_i2c_w32(I2C_CFG_DEFAULT,REG_CONFIG_REG);
 159 +
 160 +       value  = 1<< 31;
 161 +       value |= 1<<28;
 162 +       value |= clkdiv_value <<16;
 163 +       value |= 1<<6;
 164 +       value |= 1<<1;
 165 +       rt_i2c_w32(value,REG_SM0CTL0);
 166 +       rt_i2c_w32(1,REG_SM0_IS_AUTOMODE);//auto mode
 167 +}
 168 +
 169 +
 170 +static inline int rt_i2c_wait_rx_done(void)
 171 +{
 172 +       int i=0;
 173 +       while((!(rt_i2c_r32(REG_STATUS_REG) & I2C_DATARDY)) && (i<i2c_busy_loop))
 174 +               i++;
 175 +       if(i>=i2c_busy_loop){
 176 +               pr_err("err,wait for idle timeout");
 177 +               return -ETIMEDOUT;
 178 +       }
 179 +       return 0;
 180 +}
 181 +
 182 +static inline int rt_i2c_wait_idle(void)
 183 +{
 184 +       int i=0;
 185 +       while((rt_i2c_r32(REG_STATUS_REG) & I2C_BUSY) && (i<i2c_busy_loop))
 186 +               i++;
 187 +       if(i>=i2c_busy_loop){
 188 +               pr_err("err,wait for idle timeout");
 189 +               return -ETIMEDOUT;
 190 +       }
 191 +       return 0;
 192 +}
 193 +
 194 +static inline int rt_i2c_wait_tx_done(void)
 195 +{
 196 +       int i=0;
 197 +       while((!(rt_i2c_r32(REG_STATUS_REG) & I2C_SDOEMPTY)) && (i<i2c_busy_loop))
 198 +               i++;
 199 +       if(i>=i2c_busy_loop){
 200 +               pr_err("err,wait for idle timeout");
 201 +               return -ETIMEDOUT;
 202 +       }
 203 +       return 0;
 204 +}
 205 +
 206 +static int rt_i2c_handle_msg(struct i2c_adapter *a, struct i2c_msg* msg)
 207 +{
 208 +       int i = 0, j = 0, pos = 0;
 209 +       int nblock = msg->len / READ_BLOCK;
 210 +        int rem = msg->len % READ_BLOCK;
 211 +
 212 +       if (msg->flags & I2C_M_TEN) {
 213 +               printk("10 bits addr not supported\n");
 214 +               return -EINVAL;
 215 +       }
 216 +
 217 +       if (msg->flags & I2C_M_RD) {
 218 +               for (i = 0; i < nblock; i++) {
 219 +                       if (rt_i2c_wait_idle())
 220 +                               goto ERR_TIMEOUT;
 221 +                       rt_i2c_w32(READ_BLOCK - 1, REG_BYTECNT_REG);
 222 +                       rt_i2c_w32(READ_CMD, REG_STARTXFR_REG);
 223 +                       for (j = 0; j < READ_BLOCK; j++) {
 224 +                               if (rt_i2c_wait_rx_done())
 225 +                                   goto ERR_TIMEOUT;
 226 +                               msg->buf[pos++] = rt_i2c_r32(REG_DATAIN_REG);
 227 +                       }
 228 +               }
 229 +
 230 +               if (rt_i2c_wait_idle()) {
 231 +                   goto ERR_TIMEOUT;
 232 +               }
 233 +
 234 +               rt_i2c_w32(rem - 1, REG_BYTECNT_REG);
 235 +               rt_i2c_w32(READ_CMD, REG_STARTXFR_REG);
 236 +
 237 +               for (i = 0; i < rem; i++) {
 238 +                       if (rt_i2c_wait_rx_done())
 239 +                               goto ERR_TIMEOUT;
 240 +                               msg->buf[pos++] = rt_i2c_r32(REG_DATAIN_REG);
 241 +               }
 242 +       } else {
 243 +               if (rt_i2c_wait_idle()) {
 244 +                       goto ERR_TIMEOUT;
 245 +               }
 246 +               rt_i2c_w32(msg->len - 1, REG_BYTECNT_REG);
 247 +               for (i = 0; i < msg->len; i++) {
 248 +                       rt_i2c_w32(msg->buf[i], REG_DATAOUT_REG);
 249 +                       if(i == 0)
 250 +                               rt_i2c_w32(WRITE_CMD, REG_STARTXFR_REG);
 251 +
 252 +                       if (rt_i2c_wait_tx_done())
 253 +                               goto ERR_TIMEOUT;
 254 +               }
 255 +       }
 256 +
 257 +       return 0;
 258 +ERR_TIMEOUT:
 259 +       return -ETIMEDOUT;
 260 +}
 261 +
 262 +static int rt_i2c_master_xfer(struct i2c_adapter *a, struct i2c_msg *m, int n)
 263 +{
 264 +       int i = 0;
 265 +       int ret = 0;
 266 +       i2c_master_init();
 267 +       mt7621_i2c_enable(m);
 268 +
 269 +       for (i = 0; i != n && ret==0; i++) {
 270 +               ret = rt_i2c_handle_msg(a, &m[i]);
 271 +
 272 +               if (ret) {
 273 +                       return ret;
 274 +               }
 275 +       }
 276 +
 277 +       return i;
 278 +}
 279 +
 280 +static u32 rt_i2c_func(struct i2c_adapter *a)
 281 +{
 282 +       return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
 283 +}
 284 +
 285 +static const struct i2c_algorithm rt_i2c_algo = {
 286 +       .master_xfer    = rt_i2c_master_xfer,
 287 +       .functionality  = rt_i2c_func,
 288 +};
 289 +
 290 +static int rt_i2c_probe(struct platform_device *pdev)
 291 +{
 292 +       struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 293 +       int ret;
 294 +       struct i2c_algo_mt7621_data *adapter_data;
 295 +
 296 +       adapter = kzalloc(sizeof(struct i2c_adapter), GFP_KERNEL);
 297 +       if (!adapter) {
 298 +               dev_err(&pdev->dev, "failed to allocate i2c_adapter\n");
 299 +               ret =  -ENOMEM;
 300 +               goto out;
 301 +       }
 302 +       adapter_data = kzalloc(sizeof(struct i2c_algo_mt7621_data), GFP_KERNEL);
 303 +       if (!adapter_data) {
 304 +               ret = -ENOMEM;
 305 +               goto free_adapter;
 306 +       }
 307 +
 308 +       membase = devm_request_and_ioremap(&pdev->dev, res);
 309 +       if (IS_ERR(membase)){
 310 +               ret = -EBUSY;
 311 +               goto free_both;
 312 +       }
 313 +       memsysctlbase = membase - I2C_OFFSET;
 314 +
 315 +       adapter_data->id = i2c_id++;
 316 +       strlcpy(adapter->name, dev_name(&pdev->dev), sizeof(adapter->name));
 317 +
 318 +       adapter->owner = THIS_MODULE;
 319 +       adapter->nr = pdev->id;
 320 +       adapter->timeout = HZ;
 321 +       adapter->algo = &rt_i2c_algo;
 322 +       adapter->class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
 323 +       adapter->dev.parent = &pdev->dev;
 324 +       adapter->dev.of_node = pdev->dev.of_node;
 325 +
 326 +       init_waitqueue_head(&adapter_data->waitq);
 327 +       spin_lock_init(&adapter_data->lock);
 328 +
 329 +       platform_set_drvdata(pdev, adapter);
 330 +       adapter->algo_data = adapter_data;
 331 +
 332 +       ret = i2c_add_numbered_adapter(adapter);
 333 +       if (ret)
 334 +               return ret;
 335 +
 336 +       printk("MT7621A i2c add adapter is ok\n");
 337 +
 338 +       return 0;
 339 +free_both:
 340 +       kfree(adapter_data);
 341 +       free_adapter:
 342 +       kfree(adapter);
 343 +out:
 344 +       return ret;
 345 +}
 346 +
 347 +static int rt_i2c_remove(struct platform_device *pdev)
 348 +{
 349 +       struct i2c_algo_mt7621_data *adapter_data = (struct i2c_algo_mt7621_data *)adapter->algo_data;
 350 +       release_mem_region((resource_size_t)membase,0x100);
 351 +       kfree(adapter_data);
 352 +       kfree(adapter);
 353 +       platform_set_drvdata(pdev, NULL);
 354 +
 355 +       return 0;
 356 +}
 357 +
 358 +static const struct of_device_id i2c_rt_dt_ids[] = {
 359 +       { .compatible = "ralink,i2c-mt7621", },
 360 +       { /* sentinel */ }
 361 +};
 362 +
 363 +MODULE_DEVICE_TABLE(of, i2c_rt_dt_ids);
 364 +
 365 +static struct platform_driver rt_i2c_driver = {
 366 +       .probe          = rt_i2c_probe,
 367 +       .remove         = rt_i2c_remove,
 368 +       .driver         = {
 369 +               .owner  = THIS_MODULE,
 370 +               .name   = "i2c-mt7621",
 371 +               .of_match_table = i2c_rt_dt_ids,
 372 +       },
 373 +};
 374 +
 375 +static int __init i2c_rt_init (void)
 376 +{
 377 +       return platform_driver_register(&rt_i2c_driver);
 378 +}
 379 +
 380 +static void __exit i2c_rt_exit (void)
 381 +{
 382 +       platform_driver_unregister(&rt_i2c_driver);
 383 +}
 384 +module_init (i2c_rt_init);
 385 +module_exit (i2c_rt_exit);
 386 +
 387 +MODULE_AUTHOR("Steven Liu <steven_liu@mediatek.com>");
 388 +MODULE_DESCRIPTION("MT7621 I2c host driver");
 389 +MODULE_LICENSE("GPL");
 390 +MODULE_ALIAS("platform:MT7621-I2C");