1 From c8c69923236f2f3f184ddcc7eb41c113b5cc3223 Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Sun, 27 Jul 2014 10:57:40 +0100
4 Subject: [PATCH 12/57] MIPS: ralink: add MT7621 support
6 Signed-off-by: John Crispin <blogic@openwrt.org>
8 arch/mips/include/asm/gic.h | 4 +
9 arch/mips/include/asm/mach-ralink/irq.h | 9 +
10 arch/mips/include/asm/mach-ralink/mt7621.h | 39 ++++
11 arch/mips/kernel/vmlinux.lds.S | 1 +
12 arch/mips/ralink/Kconfig | 18 ++
13 arch/mips/ralink/Makefile | 7 +-
14 arch/mips/ralink/Platform | 5 +
15 arch/mips/ralink/irq-gic.c | 271 ++++++++++++++++++++++++++++
16 arch/mips/ralink/malta-amon.c | 81 +++++++++
17 arch/mips/ralink/mt7621.c | 183 +++++++++++++++++++
18 10 files changed, 617 insertions(+), 1 deletion(-)
19 create mode 100644 arch/mips/include/asm/mach-ralink/irq.h
20 create mode 100644 arch/mips/include/asm/mach-ralink/mt7621.h
21 create mode 100644 arch/mips/ralink/irq-gic.c
22 create mode 100644 arch/mips/ralink/malta-amon.c
23 create mode 100644 arch/mips/ralink/mt7621.c
26 +++ b/arch/mips/include/asm/mach-ralink/irq.h
28 +#ifndef __ASM_MACH_RALINK_IRQ_H
29 +#define __ASM_MACH_RALINK_IRQ_H
31 +#define GIC_NUM_INTRS 64
34 +#include_next <irq.h>
38 +++ b/arch/mips/include/asm/mach-ralink/mt7621.h
41 + * This program is free software; you can redistribute it and/or modify it
42 + * under the terms of the GNU General Public License version 2 as published
43 + * by the Free Software Foundation.
45 + * Parts of this file are based on Ralink's 2.6.21 BSP
47 + * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
48 + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
49 + * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
52 +#ifndef _MT7621_REGS_H_
53 +#define _MT7621_REGS_H_
55 +#define MT7621_SYSC_BASE 0x1E000000
57 +#define SYSC_REG_CHIP_NAME0 0x00
58 +#define SYSC_REG_CHIP_NAME1 0x04
59 +#define SYSC_REG_CHIP_REV 0x0c
60 +#define SYSC_REG_SYSTEM_CONFIG0 0x10
61 +#define SYSC_REG_SYSTEM_CONFIG1 0x14
63 +#define CHIP_REV_PKG_MASK 0x1
64 +#define CHIP_REV_PKG_SHIFT 16
65 +#define CHIP_REV_VER_MASK 0xf
66 +#define CHIP_REV_VER_SHIFT 8
67 +#define CHIP_REV_ECO_MASK 0xf
69 +#define MT7621_DRAM_BASE 0x0
70 +#define MT7621_DDR2_SIZE_MIN 32
71 +#define MT7621_DDR2_SIZE_MAX 256
73 +#define MT7621_CHIP_NAME0 0x3637544D
74 +#define MT7621_CHIP_NAME1 0x20203132
76 +#define MIPS_GIC_IRQ_BASE (MIPS_CPU_IRQ_BASE + 8)
79 --- a/arch/mips/kernel/vmlinux.lds.S
80 +++ b/arch/mips/kernel/vmlinux.lds.S
81 @@ -51,6 +51,7 @@ SECTIONS
83 _text = .; /* Text and read-only data */
85 + /*. = . + 0x8000; */
89 --- a/arch/mips/ralink/Kconfig
90 +++ b/arch/mips/ralink/Kconfig
91 @@ -12,6 +12,11 @@ config RALINK_ILL_ACC
98 + depends on !SOC_MT7621
101 prompt "Ralink SoC selection"
103 @@ -33,6 +38,15 @@ choice
109 + select MIPS_CPU_SCACHE
110 + select SYS_SUPPORTS_MULTITHREADING
111 + select SYS_SUPPORTS_SMP
112 + select SYS_SUPPORTS_MIPS_CMP
119 @@ -64,6 +78,10 @@ choice
120 depends on SOC_MT7620
123 + config DTB_MT7621_EVAL
124 + bool "MT7621 eval kit"
125 + depends on SOC_MT7621
130 --- a/arch/mips/ralink/Makefile
131 +++ b/arch/mips/ralink/Makefile
133 # Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
134 # Copyright (C) 2013 John Crispin <blogic@openwrt.org>
136 -obj-y := prom.o of.o reset.o clk.o irq.o timer.o
137 +obj-y := prom.o of.o reset.o clk.o timer.o
139 obj-$(CONFIG_CLKEVT_RT3352) += cevt-rt3352.o
141 obj-$(CONFIG_RALINK_ILL_ACC) += ill_acc.o
143 +obj-$(CONFIG_IRQ_INTC) += irq.o
144 +obj-$(CONFIG_IRQ_GIC) += irq-gic.o
145 +obj-$(CONFIG_MIPS_MT_SMP) += malta-amon.o
147 obj-$(CONFIG_SOC_RT288X) += rt288x.o
148 obj-$(CONFIG_SOC_RT305X) += rt305x.o
149 obj-$(CONFIG_SOC_RT3883) += rt3883.o
150 obj-$(CONFIG_SOC_MT7620) += mt7620.o
151 +obj-$(CONFIG_SOC_MT7621) += mt7621.o
153 obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
155 --- a/arch/mips/ralink/Platform
156 +++ b/arch/mips/ralink/Platform
157 @@ -27,3 +27,8 @@ cflags-$(CONFIG_SOC_RT3883) += -I$(srctr
159 load-$(CONFIG_SOC_MT7620) += 0xffffffff80000000
160 cflags-$(CONFIG_SOC_MT7620) += -I$(srctree)/arch/mips/include/asm/mach-ralink/mt7620
164 +load-$(CONFIG_SOC_MT7621) += 0xffffffff80001000
165 +cflags-$(CONFIG_SOC_MT7621) += -I$(srctree)/arch/mips/include/asm/mach-ralink/mt7621
167 +++ b/arch/mips/ralink/irq-gic.c
169 +#include <linux/init.h>
170 +#include <linux/sched.h>
171 +#include <linux/slab.h>
172 +#include <linux/interrupt.h>
173 +#include <linux/kernel_stat.h>
174 +#include <linux/hardirq.h>
175 +#include <linux/preempt.h>
176 +#include <linux/irqdomain.h>
177 +#include <linux/of_platform.h>
178 +#include <linux/of_address.h>
179 +#include <linux/of_irq.h>
181 +#include <asm/irq_cpu.h>
182 +#include <asm/mipsregs.h>
184 +#include <asm/irq.h>
185 +#include <asm/setup.h>
187 +#include <asm/gic.h>
189 +#include <asm/mach-ralink/mt7621.h>
190 +#define GIC_BASE_ADDR 0x1fbc0000
192 +unsigned long _gcmp_base;
193 +static int gic_resched_int_base = 56;
194 +static int gic_call_int_base = 60;
195 +static struct irq_chip *irq_gic;
196 +static struct gic_intr_map gic_intr_map[GIC_NUM_INTRS];
198 +#if defined(CONFIG_MIPS_MT_SMP)
199 +static int gic_resched_int_base;
200 +static int gic_call_int_base;
202 +#define GIC_RESCHED_INT(cpu) (gic_resched_int_base+(cpu))
203 +#define GIC_CALL_INT(cpu) (gic_call_int_base+(cpu))
205 +static irqreturn_t ipi_resched_interrupt(int irq, void *dev_id)
209 + return IRQ_HANDLED;
213 +ipi_call_interrupt(int irq, void *dev_id)
215 + smp_call_function_interrupt();
217 + return IRQ_HANDLED;
220 +static struct irqaction irq_resched = {
221 + .handler = ipi_resched_interrupt,
222 + .flags = IRQF_DISABLED|IRQF_PERCPU,
223 + .name = "ipi resched"
226 +static struct irqaction irq_call = {
227 + .handler = ipi_call_interrupt,
228 + .flags = IRQF_DISABLED|IRQF_PERCPU,
239 + for (i = 0; i < ARRAY_SIZE(gic_intr_map); i++) {
240 + gic_intr_map[i].cpunum = 0;
241 + gic_intr_map[i].pin = GIC_CPU_INT0;
242 + gic_intr_map[i].polarity = GIC_POL_POS;
243 + gic_intr_map[i].trigtype = GIC_TRIG_LEVEL;
244 + gic_intr_map[i].flags = 0;
247 +#if defined(CONFIG_MIPS_MT_SMP)
251 + gic_call_int_base = ARRAY_SIZE(gic_intr_map) - nr_cpu_ids;
252 + gic_resched_int_base = gic_call_int_base - nr_cpu_ids;
254 + i = gic_resched_int_base;
256 + for (cpu = 0; cpu < nr_cpu_ids; cpu++) {
257 + gic_intr_map[i + cpu].cpunum = cpu;
258 + gic_intr_map[i + cpu].pin = GIC_CPU_INT1;
259 + gic_intr_map[i + cpu].trigtype = GIC_TRIG_EDGE;
261 + gic_intr_map[i + cpu + nr_cpu_ids].cpunum = cpu;
262 + gic_intr_map[i + cpu + nr_cpu_ids].pin = GIC_CPU_INT2;
263 + gic_intr_map[i + cpu + nr_cpu_ids].trigtype = GIC_TRIG_EDGE;
270 +gic_irq_ack(struct irq_data *d)
272 + int irq = (d->irq - gic_irq_base);
274 + GIC_CLR_INTR_MASK(irq);
276 + if (gic_irq_flags[irq] & GIC_TRIG_EDGE)
277 + GICWRITE(GIC_REG(SHARED, GIC_SH_WEDGE), irq);
281 +gic_finish_irq(struct irq_data *d)
283 + GIC_SET_INTR_MASK(d->irq - gic_irq_base);
287 +gic_platform_init(int irqs, struct irq_chip *irq_controller)
289 + irq_gic = irq_controller;
293 +gic_irqdispatch(void)
295 + unsigned int irq = gic_get_int();
297 + if (likely(irq < GIC_NUM_INTRS))
298 + do_IRQ(MIPS_GIC_IRQ_BASE + irq);
300 + pr_debug("Spurious GIC Interrupt!\n");
301 + spurious_interrupt();
307 +vi_timer_irqdispatch(void)
309 + do_IRQ(cp0_compare_irq);
312 +#if defined(CONFIG_MIPS_MT_SMP)
314 +plat_ipi_call_int_xlate(unsigned int cpu)
316 + return GIC_CALL_INT(cpu);
320 +plat_ipi_resched_int_xlate(unsigned int cpu)
322 + return GIC_RESCHED_INT(cpu);
327 +plat_irq_dispatch(void)
329 + unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
331 + if (unlikely(!pending)) {
332 + pr_err("Spurious CP0 Interrupt!\n");
333 + spurious_interrupt();
335 + if (pending & CAUSEF_IP7)
336 + do_IRQ(cp0_compare_irq);
338 + if (pending & (CAUSEF_IP4 | CAUSEF_IP3 | CAUSEF_IP2))
343 +unsigned int __cpuinit
344 +get_c0_compare_int(void)
346 + return CP0_LEGACY_COMPARE_IRQ;
350 +gic_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
352 + irq_set_chip_and_handler(irq, irq_gic,
353 +#if defined(CONFIG_MIPS_MT_SMP)
354 + (hw >= gic_resched_int_base) ?
355 + handle_percpu_irq :
362 +static const struct irq_domain_ops irq_domain_ops = {
363 + .xlate = irq_domain_xlate_onecell,
368 +of_gic_init(struct device_node *node,
369 + struct device_node *parent)
371 + struct irq_domain *domain;
372 + struct resource gcmp = { 0 }, gic = { 0 };
373 + unsigned int gic_rev;
376 + if (of_address_to_resource(node, 0, &gic))
377 + panic("Failed to get gic memory range");
378 + if (request_mem_region(gic.start, resource_size(&gic),
380 + panic("Failed to request gic memory");
381 + if (of_address_to_resource(node, 2, &gcmp))
382 + panic("Failed to get gic memory range");
383 + if (request_mem_region(gcmp.start, resource_size(&gcmp),
385 + panic("Failed to request gcmp memory");
387 + _gcmp_base = (unsigned long) ioremap_nocache(gcmp.start, resource_size(&gcmp));
389 + panic("Failed to remap gcmp memory\n");
391 + /* tell the gcmp where to find the gic */
392 + write_gcr_gic_base(GIC_BASE_ADDR | CM_GCR_GIC_BASE_GICEN_MSK);
394 + if (cpu_has_vint) {
395 + set_vi_handler(2, gic_irqdispatch);
396 + set_vi_handler(3, gic_irqdispatch);
397 + set_vi_handler(4, gic_irqdispatch);
398 + set_vi_handler(7, vi_timer_irqdispatch);
403 + gic_init(gic.start, resource_size(&gic), gic_intr_map,
404 + ARRAY_SIZE(gic_intr_map), MIPS_GIC_IRQ_BASE);
406 + GICREAD(GIC_REG(SHARED, GIC_SH_REVISIONID), gic_rev);
407 + pr_info("gic: revision %d.%d\n", (gic_rev >> 8) & 0xff, gic_rev & 0xff);
409 + domain = irq_domain_add_legacy(node, GIC_NUM_INTRS, MIPS_GIC_IRQ_BASE,
410 + 0, &irq_domain_ops, NULL);
412 + panic("Failed to add irqdomain");
414 +#if defined(CONFIG_MIPS_MT_SMP)
415 + for (i = 0; i < nr_cpu_ids; i++) {
416 + setup_irq(MIPS_GIC_IRQ_BASE + GIC_RESCHED_INT(i), &irq_resched);
417 + setup_irq(MIPS_GIC_IRQ_BASE + GIC_CALL_INT(i), &irq_call);
421 + change_c0_status(ST0_IM, STATUSF_IP7 | STATUSF_IP4 | STATUSF_IP3 |
426 +static struct of_device_id __initdata of_irq_ids[] = {
427 + { .compatible = "mti,cpu-interrupt-controller", .data = mips_cpu_intc_init },
428 + { .compatible = "ralink,mt7621-gic", .data = of_gic_init },
435 + of_irq_init(of_irq_ids);
438 +++ b/arch/mips/ralink/malta-amon.c
441 + * Copyright (C) 2007 MIPS Technologies, Inc.
442 + * All rights reserved.
444 + * This program is free software; you can distribute it and/or modify it
445 + * under the terms of the GNU General Public License (Version 2) as
446 + * published by the Free Software Foundation.
448 + * This program is distributed in the hope it will be useful, but WITHOUT
449 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
450 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
451 + * for more details.
453 + * You should have received a copy of the GNU General Public License along
454 + * with this program; if not, write to the Free Software Foundation, Inc.,
455 + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
457 + * Arbitrary Monitor interface
460 +#include <linux/kernel.h>
461 +#include <linux/init.h>
462 +#include <linux/smp.h>
464 +#include <asm/addrspace.h>
465 +#include <asm/mips-boards/launch.h>
466 +#include <asm/mipsmtregs.h>
468 +int amon_cpu_avail(int cpu)
470 + struct cpulaunch *launch = (struct cpulaunch *)CKSEG0ADDR(CPULAUNCH);
472 + if (cpu < 0 || cpu >= NCPULAUNCH) {
473 + pr_debug("avail: cpu%d is out of range\n", cpu);
478 + if (!(launch->flags & LAUNCH_FREADY)) {
479 + pr_debug("avail: cpu%d is not ready\n", cpu);
482 + if (launch->flags & (LAUNCH_FGO|LAUNCH_FGONE)) {
483 + pr_debug("avail: too late.. cpu%d is already gone\n", cpu);
490 +void amon_cpu_start(int cpu,
491 + unsigned long pc, unsigned long sp,
492 + unsigned long gp, unsigned long a0)
494 + volatile struct cpulaunch *launch =
495 + (struct cpulaunch *)CKSEG0ADDR(CPULAUNCH);
497 + if (!amon_cpu_avail(cpu))
499 + if (cpu == smp_processor_id()) {
500 + pr_debug("launch: I am cpu%d!\n", cpu);
505 + pr_debug("launch: starting cpu%d\n", cpu);
512 + smp_wmb(); /* Target must see parameters before go */
513 + launch->flags |= LAUNCH_FGO;
514 + smp_wmb(); /* Target must see go before we poll */
516 + while ((launch->flags & LAUNCH_FGONE) == 0)
518 + smp_rmb(); /* Target will be updating flags soon */
519 + pr_debug("launch: cpu%d gone!\n", cpu);
522 +++ b/arch/mips/ralink/mt7621.c
525 + * This program is free software; you can redistribute it and/or modify it
526 + * under the terms of the GNU General Public License version 2 as published
527 + * by the Free Software Foundation.
529 + * Parts of this file are based on Ralink's 2.6.21 BSP
531 + * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
532 + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
533 + * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
536 +#include <linux/kernel.h>
537 +#include <linux/init.h>
538 +#include <linux/module.h>
540 +#include <asm/mipsregs.h>
541 +#include <asm/smp-ops.h>
542 +#include <asm/mips-cm.h>
543 +#include <asm/mips-cpc.h>
544 +#include <asm/mach-ralink/ralink_regs.h>
545 +#include <asm/mach-ralink/mt7621.h>
551 +#define SYSC_REG_SYSCFG 0x10
552 +#define SYSC_REG_CPLL_CLKCFG0 0x2c
553 +#define SYSC_REG_CUR_CLK_STS 0x44
554 +#define CPU_CLK_SEL (BIT(30) | BIT(31))
556 +#define MT7621_GPIO_MODE_UART1 1
557 +#define MT7621_GPIO_MODE_I2C 2
558 +#define MT7621_GPIO_MODE_UART3_MASK 0x3
559 +#define MT7621_GPIO_MODE_UART3_SHIFT 3
560 +#define MT7621_GPIO_MODE_UART3_GPIO 1
561 +#define MT7621_GPIO_MODE_UART2_MASK 0x3
562 +#define MT7621_GPIO_MODE_UART2_SHIFT 5
563 +#define MT7621_GPIO_MODE_UART2_GPIO 1
564 +#define MT7621_GPIO_MODE_JTAG 7
565 +#define MT7621_GPIO_MODE_WDT_MASK 0x3
566 +#define MT7621_GPIO_MODE_WDT_SHIFT 8
567 +#define MT7621_GPIO_MODE_WDT_GPIO 1
568 +#define MT7621_GPIO_MODE_PCIE_RST 0
569 +#define MT7621_GPIO_MODE_PCIE_REF 2
570 +#define MT7621_GPIO_MODE_PCIE_MASK 0x3
571 +#define MT7621_GPIO_MODE_PCIE_SHIFT 10
572 +#define MT7621_GPIO_MODE_PCIE_GPIO 1
573 +#define MT7621_GPIO_MODE_MDIO_MASK 0x3
574 +#define MT7621_GPIO_MODE_MDIO_SHIFT 12
575 +#define MT7621_GPIO_MODE_MDIO_GPIO 1
576 +#define MT7621_GPIO_MODE_RGMII1 14
577 +#define MT7621_GPIO_MODE_RGMII2 15
578 +#define MT7621_GPIO_MODE_SPI_MASK 0x3
579 +#define MT7621_GPIO_MODE_SPI_SHIFT 16
580 +#define MT7621_GPIO_MODE_SPI_GPIO 1
581 +#define MT7621_GPIO_MODE_SDHCI_MASK 0x3
582 +#define MT7621_GPIO_MODE_SDHCI_SHIFT 18
583 +#define MT7621_GPIO_MODE_SDHCI_GPIO 1
585 +static struct rt2880_pmx_func uart1_grp[] = { FUNC("uart1", 0, 1, 2) };
586 +static struct rt2880_pmx_func i2c_grp[] = { FUNC("i2c", 0, 3, 2) };
587 +static struct rt2880_pmx_func uart3_grp[] = {
588 + FUNC("uart3", 0, 5, 4),
589 + FUNC("i2s", 2, 5, 4),
590 + FUNC("spdif3", 3, 5, 4),
592 +static struct rt2880_pmx_func uart2_grp[] = {
593 + FUNC("uart2", 0, 9, 4),
594 + FUNC("pcm", 2, 9, 4),
595 + FUNC("spdif2", 3, 9, 4),
597 +static struct rt2880_pmx_func jtag_grp[] = { FUNC("jtag", 0, 13, 5) };
598 +static struct rt2880_pmx_func wdt_grp[] = {
599 + FUNC("wdt rst", 0, 18, 1),
600 + FUNC("wdt refclk", 2, 18, 1),
602 +static struct rt2880_pmx_func pcie_rst_grp[] = {
603 + FUNC("pcie rst", MT7621_GPIO_MODE_PCIE_RST, 19, 1),
604 + FUNC("pcie refclk", MT7621_GPIO_MODE_PCIE_REF, 19, 1)
606 +static struct rt2880_pmx_func mdio_grp[] = { FUNC("mdio", 0, 20, 2) };
607 +static struct rt2880_pmx_func rgmii2_grp[] = { FUNC("rgmii2", 0, 22, 12) };
608 +static struct rt2880_pmx_func spi_grp[] = {
609 + FUNC("spi", 0, 34, 7),
610 + FUNC("nand1", 2, 34, 7),
612 +static struct rt2880_pmx_func sdhci_grp[] = {
613 + FUNC("sdhci", 0, 41, 8),
614 + FUNC("nand2", 2, 41, 8),
616 +static struct rt2880_pmx_func rgmii1_grp[] = { FUNC("rgmii1", 0, 49, 12) };
618 +static struct rt2880_pmx_group mt7621_pinmux_data[] = {
619 + GRP("uart1", uart1_grp, 1, MT7621_GPIO_MODE_UART1),
620 + GRP("i2c", i2c_grp, 1, MT7621_GPIO_MODE_I2C),
621 + GRP_G("uart3", uart3_grp, MT7621_GPIO_MODE_UART3_MASK,
622 + MT7621_GPIO_MODE_UART3_GPIO, MT7621_GPIO_MODE_UART3_SHIFT),
623 + GRP_G("uart2", uart2_grp, MT7621_GPIO_MODE_UART2_MASK,
624 + MT7621_GPIO_MODE_UART2_GPIO, MT7621_GPIO_MODE_UART2_SHIFT),
625 + GRP("jtag", jtag_grp, 1, MT7621_GPIO_MODE_JTAG),
626 + GRP_G("wdt", wdt_grp, MT7621_GPIO_MODE_WDT_MASK,
627 + MT7621_GPIO_MODE_WDT_GPIO, MT7621_GPIO_MODE_WDT_SHIFT),
628 + GRP_G("pcie", pcie_rst_grp, MT7621_GPIO_MODE_PCIE_MASK,
629 + MT7621_GPIO_MODE_PCIE_GPIO, MT7621_GPIO_MODE_PCIE_SHIFT),
630 + GRP_G("mdio", mdio_grp, MT7621_GPIO_MODE_MDIO_MASK,
631 + MT7621_GPIO_MODE_MDIO_GPIO, MT7621_GPIO_MODE_MDIO_SHIFT),
632 + GRP("rgmii2", rgmii2_grp, 1, MT7621_GPIO_MODE_RGMII2),
633 + GRP_G("spi", spi_grp, MT7621_GPIO_MODE_SPI_MASK,
634 + MT7621_GPIO_MODE_SPI_GPIO, MT7621_GPIO_MODE_SPI_SHIFT),
635 + GRP_G("sdhci", sdhci_grp, MT7621_GPIO_MODE_SDHCI_MASK,
636 + MT7621_GPIO_MODE_SDHCI_GPIO, MT7621_GPIO_MODE_SDHCI_SHIFT),
637 + GRP("rgmii1", rgmii1_grp, 1, MT7621_GPIO_MODE_RGMII1),
641 +void __init ralink_clk_init(void)
646 + u32 clk_sts, syscfg;
647 + u8 clk_sel = 0, xtal_mode;
650 + if ((rt_sysc_r32(SYSC_REG_CPLL_CLKCFG0) & CPU_CLK_SEL) != 0)
655 + clk_sts = rt_sysc_r32(SYSC_REG_CUR_CLK_STS);
656 + cpu_fdiv = ((clk_sts >> 8) & 0x1F);
657 + cpu_ffrac = (clk_sts & 0x1F);
658 + cpu_clk = (500 * cpu_ffrac / cpu_fdiv) * 1000 * 1000;
662 + fbdiv = ((rt_sysc_r32(0x648) >> 4) & 0x7F) + 1;
663 + syscfg = rt_sysc_r32(SYSC_REG_SYSCFG);
664 + xtal_mode = (syscfg >> 6) & 0x7;
665 + if(xtal_mode >= 6) { //25Mhz Xtal
666 + cpu_clk = 25 * fbdiv * 1000 * 1000;
667 + } else if(xtal_mode >=3) { //40Mhz Xtal
668 + cpu_clk = 40 * fbdiv * 1000 * 1000;
669 + } else { // 20Mhz Xtal
670 + cpu_clk = 20 * fbdiv * 1000 * 1000;
674 + cpu_clk = 880000000;
675 + ralink_clk_add("cpu", cpu_clk);
676 + ralink_clk_add("1e000b00.spi", 50000000);
677 + ralink_clk_add("1e000c00.uartlite", 50000000);
678 + ralink_clk_add("1e000d00.uart", 50000000);
681 +void __init ralink_of_remap(void)
683 + rt_sysc_membase = plat_of_remap_node("mtk,mt7621-sysc");
684 + rt_memc_membase = plat_of_remap_node("mtk,mt7621-memc");
686 + if (!rt_sysc_membase || !rt_memc_membase)
687 + panic("Failed to remap core resources");
690 +void prom_soc_init(struct ralink_soc_info *soc_info)
692 + void __iomem *sysc = (void __iomem *) KSEG1ADDR(MT7621_SYSC_BASE);
693 + unsigned char *name = NULL;
698 + n0 = __raw_readl(sysc + SYSC_REG_CHIP_NAME0);
699 + n1 = __raw_readl(sysc + SYSC_REG_CHIP_NAME1);
701 + if (n0 == MT7621_CHIP_NAME0 && n1 == MT7621_CHIP_NAME1) {
703 + soc_info->compatible = "mtk,mt7621-soc";
705 + panic("mt7621: unknown SoC, n0:%08x n1:%08x\n", n0, n1);
708 + rev = __raw_readl(sysc + SYSC_REG_CHIP_REV);
710 + snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN,
711 + "Mediatek %s ver:%u eco:%u",
713 + (rev >> CHIP_REV_VER_SHIFT) & CHIP_REV_VER_MASK,
714 + (rev & CHIP_REV_ECO_MASK));
716 + soc_info->mem_size_min = MT7621_DDR2_SIZE_MIN;
717 + soc_info->mem_size_max = MT7621_DDR2_SIZE_MAX;
718 + soc_info->mem_base = MT7621_DRAM_BASE;
720 + rt2880_pinmux_data = mt7621_pinmux_data;
722 + /* Early detection of CMP support */
726 + if (!register_cps_smp_ops())
728 + if (!register_cmp_smp_ops())
730 + if (!register_vsmp_smp_ops())
733 --- a/arch/mips/kernel/mips-cm.c
734 +++ b/arch/mips/kernel/mips-cm.c
735 @@ -105,7 +105,7 @@ int mips_cm_probe(void)
736 write_gcr_base(base_reg);
738 /* disable CM regions */
739 - write_gcr_reg0_base(CM_GCR_REGn_BASE_BASEADDR_MSK);
740 +/* write_gcr_reg0_base(CM_GCR_REGn_BASE_BASEADDR_MSK);
741 write_gcr_reg0_mask(CM_GCR_REGn_MASK_ADDRMASK_MSK);
742 write_gcr_reg1_base(CM_GCR_REGn_BASE_BASEADDR_MSK);
743 write_gcr_reg1_mask(CM_GCR_REGn_MASK_ADDRMASK_MSK);
744 @@ -113,7 +113,7 @@ int mips_cm_probe(void)
745 write_gcr_reg2_mask(CM_GCR_REGn_MASK_ADDRMASK_MSK);
746 write_gcr_reg3_base(CM_GCR_REGn_BASE_BASEADDR_MSK);
747 write_gcr_reg3_mask(CM_GCR_REGn_MASK_ADDRMASK_MSK);
750 /* probe for an L2-only sync region */
751 mips_cm_probe_l2sync();