1 From 2809b31770d7fd934a748692e1922a5e613f06e5 Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Sun, 20 Jan 2013 22:03:46 +0100
4 Subject: [PATCH 08/14] MIPS: ralink: adds support for RT305x SoC family
6 Add support code for rt3050, rt3052, rt3350, rt3352 and rt5350 SOC.
8 The code detects the SoC and registers the clk / pinmux settings.
10 Signed-off-by: John Crispin <blogic@openwrt.org>
11 Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
12 Patchwork: http://patchwork.linux-mips.org/patch/4896/
14 arch/mips/include/asm/mach-ralink/rt305x.h | 139 ++++++++++++++++
15 arch/mips/ralink/rt305x.c | 242 ++++++++++++++++++++++++++++
16 2 files changed, 381 insertions(+)
17 create mode 100644 arch/mips/include/asm/mach-ralink/rt305x.h
18 create mode 100644 arch/mips/ralink/rt305x.c
20 diff --git a/arch/mips/include/asm/mach-ralink/rt305x.h b/arch/mips/include/asm/mach-ralink/rt305x.h
22 index 0000000..7d344f2
24 +++ b/arch/mips/include/asm/mach-ralink/rt305x.h
27 + * This program is free software; you can redistribute it and/or modify it
28 + * under the terms of the GNU General Public License version 2 as published
29 + * by the Free Software Foundation.
31 + * Parts of this file are based on Ralink's 2.6.21 BSP
33 + * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
34 + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
35 + * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
38 +#ifndef _RT305X_REGS_H_
39 +#define _RT305X_REGS_H_
41 +enum rt305x_soc_type {
42 + RT305X_SOC_UNKNOWN = 0,
50 +extern enum rt305x_soc_type rt305x_soc;
52 +static inline int soc_is_rt3050(void)
54 + return rt305x_soc == RT305X_SOC_RT3050;
57 +static inline int soc_is_rt3052(void)
59 + return rt305x_soc == RT305X_SOC_RT3052;
62 +static inline int soc_is_rt305x(void)
64 + return soc_is_rt3050() || soc_is_rt3052();
67 +static inline int soc_is_rt3350(void)
69 + return rt305x_soc == RT305X_SOC_RT3350;
72 +static inline int soc_is_rt3352(void)
74 + return rt305x_soc == RT305X_SOC_RT3352;
77 +static inline int soc_is_rt5350(void)
79 + return rt305x_soc == RT305X_SOC_RT5350;
82 +#define RT305X_SYSC_BASE 0x10000000
84 +#define SYSC_REG_CHIP_NAME0 0x00
85 +#define SYSC_REG_CHIP_NAME1 0x04
86 +#define SYSC_REG_CHIP_ID 0x0c
87 +#define SYSC_REG_SYSTEM_CONFIG 0x10
89 +#define RT3052_CHIP_NAME0 0x30335452
90 +#define RT3052_CHIP_NAME1 0x20203235
92 +#define RT3350_CHIP_NAME0 0x33335452
93 +#define RT3350_CHIP_NAME1 0x20203035
95 +#define RT3352_CHIP_NAME0 0x33335452
96 +#define RT3352_CHIP_NAME1 0x20203235
98 +#define RT5350_CHIP_NAME0 0x33355452
99 +#define RT5350_CHIP_NAME1 0x20203035
101 +#define CHIP_ID_ID_MASK 0xff
102 +#define CHIP_ID_ID_SHIFT 8
103 +#define CHIP_ID_REV_MASK 0xff
105 +#define RT305X_SYSCFG_CPUCLK_SHIFT 18
106 +#define RT305X_SYSCFG_CPUCLK_MASK 0x1
107 +#define RT305X_SYSCFG_CPUCLK_LOW 0x0
108 +#define RT305X_SYSCFG_CPUCLK_HIGH 0x1
110 +#define RT305X_SYSCFG_SRAM_CS0_MODE_SHIFT 2
111 +#define RT305X_SYSCFG_CPUCLK_MASK 0x1
112 +#define RT305X_SYSCFG_SRAM_CS0_MODE_WDT 0x1
114 +#define RT3352_SYSCFG0_CPUCLK_SHIFT 8
115 +#define RT3352_SYSCFG0_CPUCLK_MASK 0x1
116 +#define RT3352_SYSCFG0_CPUCLK_LOW 0x0
117 +#define RT3352_SYSCFG0_CPUCLK_HIGH 0x1
119 +#define RT5350_SYSCFG0_CPUCLK_SHIFT 8
120 +#define RT5350_SYSCFG0_CPUCLK_MASK 0x3
121 +#define RT5350_SYSCFG0_CPUCLK_360 0x0
122 +#define RT5350_SYSCFG0_CPUCLK_320 0x2
123 +#define RT5350_SYSCFG0_CPUCLK_300 0x3
125 +/* multi function gpio pins */
126 +#define RT305X_GPIO_I2C_SD 1
127 +#define RT305X_GPIO_I2C_SCLK 2
128 +#define RT305X_GPIO_SPI_EN 3
129 +#define RT305X_GPIO_SPI_CLK 4
130 +/* GPIO 7-14 is shared between UART0, PCM and I2S interfaces */
131 +#define RT305X_GPIO_7 7
132 +#define RT305X_GPIO_10 10
133 +#define RT305X_GPIO_14 14
134 +#define RT305X_GPIO_UART1_TXD 15
135 +#define RT305X_GPIO_UART1_RXD 16
136 +#define RT305X_GPIO_JTAG_TDO 17
137 +#define RT305X_GPIO_JTAG_TDI 18
138 +#define RT305X_GPIO_MDIO_MDC 22
139 +#define RT305X_GPIO_MDIO_MDIO 23
140 +#define RT305X_GPIO_SDRAM_MD16 24
141 +#define RT305X_GPIO_SDRAM_MD31 39
142 +#define RT305X_GPIO_GE0_TXD0 40
143 +#define RT305X_GPIO_GE0_RXCLK 51
145 +#define RT305X_GPIO_MODE_I2C BIT(0)
146 +#define RT305X_GPIO_MODE_SPI BIT(1)
147 +#define RT305X_GPIO_MODE_UART0_SHIFT 2
148 +#define RT305X_GPIO_MODE_UART0_MASK 0x7
149 +#define RT305X_GPIO_MODE_UART0(x) ((x) << RT305X_GPIO_MODE_UART0_SHIFT)
150 +#define RT305X_GPIO_MODE_UARTF 0x0
151 +#define RT305X_GPIO_MODE_PCM_UARTF 0x1
152 +#define RT305X_GPIO_MODE_PCM_I2S 0x2
153 +#define RT305X_GPIO_MODE_I2S_UARTF 0x3
154 +#define RT305X_GPIO_MODE_PCM_GPIO 0x4
155 +#define RT305X_GPIO_MODE_GPIO_UARTF 0x5
156 +#define RT305X_GPIO_MODE_GPIO_I2S 0x6
157 +#define RT305X_GPIO_MODE_GPIO 0x7
158 +#define RT305X_GPIO_MODE_UART1 BIT(5)
159 +#define RT305X_GPIO_MODE_JTAG BIT(6)
160 +#define RT305X_GPIO_MODE_MDIO BIT(7)
161 +#define RT305X_GPIO_MODE_SDRAM BIT(8)
162 +#define RT305X_GPIO_MODE_RGMII BIT(9)
165 diff --git a/arch/mips/ralink/rt305x.c b/arch/mips/ralink/rt305x.c
167 index 0000000..0a4bbdc
169 +++ b/arch/mips/ralink/rt305x.c
172 + * This program is free software; you can redistribute it and/or modify it
173 + * under the terms of the GNU General Public License version 2 as published
174 + * by the Free Software Foundation.
176 + * Parts of this file are based on Ralink's 2.6.21 BSP
178 + * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
179 + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
180 + * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
183 +#include <linux/kernel.h>
184 +#include <linux/init.h>
185 +#include <linux/module.h>
187 +#include <asm/mipsregs.h>
188 +#include <asm/mach-ralink/ralink_regs.h>
189 +#include <asm/mach-ralink/rt305x.h>
193 +enum rt305x_soc_type rt305x_soc;
195 +struct ralink_pinmux_grp mode_mux[] = {
198 + .mask = RT305X_GPIO_MODE_I2C,
199 + .gpio_first = RT305X_GPIO_I2C_SD,
200 + .gpio_last = RT305X_GPIO_I2C_SCLK,
203 + .mask = RT305X_GPIO_MODE_SPI,
204 + .gpio_first = RT305X_GPIO_SPI_EN,
205 + .gpio_last = RT305X_GPIO_SPI_CLK,
207 + .name = "uartlite",
208 + .mask = RT305X_GPIO_MODE_UART1,
209 + .gpio_first = RT305X_GPIO_UART1_TXD,
210 + .gpio_last = RT305X_GPIO_UART1_RXD,
213 + .mask = RT305X_GPIO_MODE_JTAG,
214 + .gpio_first = RT305X_GPIO_JTAG_TDO,
215 + .gpio_last = RT305X_GPIO_JTAG_TDI,
218 + .mask = RT305X_GPIO_MODE_MDIO,
219 + .gpio_first = RT305X_GPIO_MDIO_MDC,
220 + .gpio_last = RT305X_GPIO_MDIO_MDIO,
223 + .mask = RT305X_GPIO_MODE_SDRAM,
224 + .gpio_first = RT305X_GPIO_SDRAM_MD16,
225 + .gpio_last = RT305X_GPIO_SDRAM_MD31,
228 + .mask = RT305X_GPIO_MODE_RGMII,
229 + .gpio_first = RT305X_GPIO_GE0_TXD0,
230 + .gpio_last = RT305X_GPIO_GE0_RXCLK,
234 +struct ralink_pinmux_grp uart_mux[] = {
237 + .mask = RT305X_GPIO_MODE_UARTF,
238 + .gpio_first = RT305X_GPIO_7,
239 + .gpio_last = RT305X_GPIO_14,
241 + .name = "pcm uartf",
242 + .mask = RT305X_GPIO_MODE_PCM_UARTF,
243 + .gpio_first = RT305X_GPIO_7,
244 + .gpio_last = RT305X_GPIO_14,
247 + .mask = RT305X_GPIO_MODE_PCM_I2S,
248 + .gpio_first = RT305X_GPIO_7,
249 + .gpio_last = RT305X_GPIO_14,
251 + .name = "i2s uartf",
252 + .mask = RT305X_GPIO_MODE_I2S_UARTF,
253 + .gpio_first = RT305X_GPIO_7,
254 + .gpio_last = RT305X_GPIO_14,
256 + .name = "pcm gpio",
257 + .mask = RT305X_GPIO_MODE_PCM_GPIO,
258 + .gpio_first = RT305X_GPIO_10,
259 + .gpio_last = RT305X_GPIO_14,
261 + .name = "gpio uartf",
262 + .mask = RT305X_GPIO_MODE_GPIO_UARTF,
263 + .gpio_first = RT305X_GPIO_7,
264 + .gpio_last = RT305X_GPIO_14,
266 + .name = "gpio i2s",
267 + .mask = RT305X_GPIO_MODE_GPIO_I2S,
268 + .gpio_first = RT305X_GPIO_7,
269 + .gpio_last = RT305X_GPIO_14,
272 + .mask = RT305X_GPIO_MODE_GPIO,
276 +void rt305x_wdt_reset(void)
280 + /* enable WDT reset output on pin SRAM_CS_N */
281 + t = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG);
282 + t |= RT305X_SYSCFG_SRAM_CS0_MODE_WDT <<
283 + RT305X_SYSCFG_SRAM_CS0_MODE_SHIFT;
284 + rt_sysc_w32(t, SYSC_REG_SYSTEM_CONFIG);
287 +struct ralink_pinmux gpio_pinmux = {
290 + .uart_shift = RT305X_GPIO_MODE_UART0_SHIFT,
291 + .wdt_reset = rt305x_wdt_reset,
294 +void __init ralink_clk_init(void)
296 + unsigned long cpu_rate, sys_rate, wdt_rate, uart_rate;
297 + u32 t = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG);
299 + if (soc_is_rt305x() || soc_is_rt3350()) {
300 + t = (t >> RT305X_SYSCFG_CPUCLK_SHIFT) &
301 + RT305X_SYSCFG_CPUCLK_MASK;
303 + case RT305X_SYSCFG_CPUCLK_LOW:
304 + cpu_rate = 320000000;
306 + case RT305X_SYSCFG_CPUCLK_HIGH:
307 + cpu_rate = 384000000;
310 + sys_rate = uart_rate = wdt_rate = cpu_rate / 3;
311 + } else if (soc_is_rt3352()) {
312 + t = (t >> RT3352_SYSCFG0_CPUCLK_SHIFT) &
313 + RT3352_SYSCFG0_CPUCLK_MASK;
315 + case RT3352_SYSCFG0_CPUCLK_LOW:
316 + cpu_rate = 384000000;
318 + case RT3352_SYSCFG0_CPUCLK_HIGH:
319 + cpu_rate = 400000000;
322 + sys_rate = wdt_rate = cpu_rate / 3;
323 + uart_rate = 40000000;
324 + } else if (soc_is_rt5350()) {
325 + t = (t >> RT5350_SYSCFG0_CPUCLK_SHIFT) &
326 + RT5350_SYSCFG0_CPUCLK_MASK;
328 + case RT5350_SYSCFG0_CPUCLK_360:
329 + cpu_rate = 360000000;
330 + sys_rate = cpu_rate / 3;
332 + case RT5350_SYSCFG0_CPUCLK_320:
333 + cpu_rate = 320000000;
334 + sys_rate = cpu_rate / 4;
336 + case RT5350_SYSCFG0_CPUCLK_300:
337 + cpu_rate = 300000000;
338 + sys_rate = cpu_rate / 3;
343 + uart_rate = 40000000;
344 + wdt_rate = sys_rate;
349 + ralink_clk_add("cpu", cpu_rate);
350 + ralink_clk_add("10000b00.spi", sys_rate);
351 + ralink_clk_add("10000100.timer", wdt_rate);
352 + ralink_clk_add("10000500.uart", uart_rate);
353 + ralink_clk_add("10000c00.uartlite", uart_rate);
356 +void __init ralink_of_remap(void)
358 + rt_sysc_membase = plat_of_remap_node("ralink,rt3050-sysc");
359 + rt_memc_membase = plat_of_remap_node("ralink,rt3050-memc");
361 + if (!rt_sysc_membase || !rt_memc_membase)
362 + panic("Failed to remap core resources");
365 +void prom_soc_init(struct ralink_soc_info *soc_info)
367 + void __iomem *sysc = (void __iomem *) KSEG1ADDR(RT305X_SYSC_BASE);
368 + unsigned char *name;
373 + n0 = __raw_readl(sysc + SYSC_REG_CHIP_NAME0);
374 + n1 = __raw_readl(sysc + SYSC_REG_CHIP_NAME1);
376 + if (n0 == RT3052_CHIP_NAME0 && n1 == RT3052_CHIP_NAME1) {
377 + unsigned long icache_sets;
379 + icache_sets = (read_c0_config1() >> 22) & 7;
380 + if (icache_sets == 1) {
381 + rt305x_soc = RT305X_SOC_RT3050;
383 + soc_info->compatible = "ralink,rt3050-soc";
385 + rt305x_soc = RT305X_SOC_RT3052;
387 + soc_info->compatible = "ralink,rt3052-soc";
389 + } else if (n0 == RT3350_CHIP_NAME0 && n1 == RT3350_CHIP_NAME1) {
390 + rt305x_soc = RT305X_SOC_RT3350;
392 + soc_info->compatible = "ralink,rt3350-soc";
393 + } else if (n0 == RT3352_CHIP_NAME0 && n1 == RT3352_CHIP_NAME1) {
394 + rt305x_soc = RT305X_SOC_RT3352;
396 + soc_info->compatible = "ralink,rt3352-soc";
397 + } else if (n0 == RT5350_CHIP_NAME0 && n1 == RT5350_CHIP_NAME1) {
398 + rt305x_soc = RT305X_SOC_RT5350;
400 + soc_info->compatible = "ralink,rt5350-soc";
402 + panic("rt305x: unknown SoC, n0:%08x n1:%08x\n", n0, n1);
405 + id = __raw_readl(sysc + SYSC_REG_CHIP_ID);
407 + snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN,
408 + "Ralink %s id:%u rev:%u",
410 + (id >> CHIP_ID_ID_SHIFT) & CHIP_ID_ID_MASK,
411 + (id & CHIP_ID_REV_MASK));