target/linux/ramips/patches-3.8/0013-MIPS-add-irqdomain-support-for-the-CPU-IRQ-controlle.patch

   1 From 0916b46962cbcac9465d253d0a398435b3965fd5 Mon Sep 17 00:00:00 2001
   2 From: Gabor Juhos <juhosg@openwrt.org>
   3 Date: Thu, 31 Jan 2013 12:20:43 +0000
   4 Subject: [PATCH 13/14] MIPS: add irqdomain support for the CPU IRQ controller
   5
   6 Add code to load a irq_domain for the MIPS IRQ controller from a devicetree
   7 file.
   8
   9 Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
  10 Signed-off-by: John Crispin <blogic@openwrt.org>
  11 Acked-by: David Daney <david.daney@cavium.com>
  12 Patchwork: http://patchwork.linux-mips.org/patch/4902/
  13 ---
  14  arch/mips/include/asm/irq_cpu.h |    6 ++++++
  15  arch/mips/kernel/irq_cpu.c      |   42 +++++++++++++++++++++++++++++++++++++++
  16  2 files changed, 48 insertions(+)
  17
  18 --- a/arch/mips/include/asm/irq_cpu.h
  19 +++ b/arch/mips/include/asm/irq_cpu.h
  20 @@ -17,4 +17,10 @@ extern void mips_cpu_irq_init(void);
  21  extern void rm7k_cpu_irq_init(void);
  22  extern void rm9k_cpu_irq_init(void);
  23
  24 +#ifdef CONFIG_IRQ_DOMAIN
  25 +struct device_node;
  26 +extern int mips_cpu_intc_init(struct device_node *of_node,
  27 +                             struct device_node *parent);
  28 +#endif
  29 +
  30  #endif /* _ASM_IRQ_CPU_H */
  31 --- a/arch/mips/kernel/irq_cpu.c
  32 +++ b/arch/mips/kernel/irq_cpu.c
  33 @@ -31,6 +31,7 @@
  34  #include <linux/interrupt.h>
  35  #include <linux/kernel.h>
  36  #include <linux/irq.h>
  37 +#include <linux/irqdomain.h>
  38
  39  #include <asm/irq_cpu.h>
  40  #include <asm/mipsregs.h>
  41 @@ -113,3 +114,44 @@ void __init mips_cpu_irq_init(void)
  42                 irq_set_chip_and_handler(i, &mips_cpu_irq_controller,
  43                                          handle_percpu_irq);
  44  }
  45 +
  46 +#ifdef CONFIG_IRQ_DOMAIN
  47 +static int mips_cpu_intc_map(struct irq_domain *d, unsigned int irq,
  48 +                            irq_hw_number_t hw)
  49 +{
  50 +       static struct irq_chip *chip;
  51 +
  52 +       if (hw < 2 && cpu_has_mipsmt) {
  53 +               /* Software interrupts are used for MT/CMT IPI */
  54 +               chip = &mips_mt_cpu_irq_controller;
  55 +       } else {
  56 +               chip = &mips_cpu_irq_controller;
  57 +       }
  58 +
  59 +       irq_set_chip_and_handler(irq, chip, handle_percpu_irq);
  60 +
  61 +       return 0;
  62 +}
  63 +
  64 +static const struct irq_domain_ops mips_cpu_intc_irq_domain_ops = {
  65 +       .map = mips_cpu_intc_map,
  66 +       .xlate = irq_domain_xlate_onecell,
  67 +};
  68 +
  69 +int __init mips_cpu_intc_init(struct device_node *of_node,
  70 +                             struct device_node *parent)
  71 +{
  72 +       struct irq_domain *domain;
  73 +
  74 +       /* Mask interrupts. */
  75 +       clear_c0_status(ST0_IM);
  76 +       clear_c0_cause(CAUSEF_IP);
  77 +
  78 +       domain = irq_domain_add_legacy(of_node, 8, MIPS_CPU_IRQ_BASE, 0,
  79 +                                      &mips_cpu_intc_irq_domain_ops, NULL);
  80 +       if (!domain)
  81 +               panic("Failed to add irqdomain for MIPS CPU\n");
  82 +
  83 +       return 0;
  84 +}
  85 +#endif /* CONFIG_IRQ_DOMAIN */