1 From 2a0d9878985bb3274bb61535f76ea293991635a9 Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Sun, 27 Jan 2013 09:17:20 +0100
4 Subject: [PATCH 27/79] MIPS: ralink: adds support for RT2880 SoC family
6 Add support code for rt2880 SOC.
8 The code detects the SoC and registers the clk / pinmux settings.
10 Signed-off-by: John Crispin <blogic@openwrt.org>
11 Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
12 Patchwork: http://patchwork.linux-mips.org/patch/5176/
14 arch/mips/Kconfig | 2 +-
15 arch/mips/include/asm/mach-ralink/rt288x.h | 49 ++++++++++
16 arch/mips/ralink/Kconfig | 3 +
17 arch/mips/ralink/Makefile | 1 +
18 arch/mips/ralink/Platform | 5 +
19 arch/mips/ralink/rt288x.c | 139 ++++++++++++++++++++++++++++
20 6 files changed, 198 insertions(+), 1 deletion(-)
21 create mode 100644 arch/mips/include/asm/mach-ralink/rt288x.h
22 create mode 100644 arch/mips/ralink/rt288x.c
24 diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
25 index b5081b5..b5fd476 100644
26 --- a/arch/mips/Kconfig
27 +++ b/arch/mips/Kconfig
28 @@ -1177,7 +1177,7 @@ config BOOT_ELF32
30 config MIPS_L1_CACHE_SHIFT
32 - default "4" if MACH_DECSTATION || MIKROTIK_RB532 || PMC_MSP4200_EVAL
33 + default "4" if MACH_DECSTATION || MIKROTIK_RB532 || PMC_MSP4200_EVAL || SOC_RT288X
34 default "6" if MIPS_CPU_SCACHE
35 default "7" if SGI_IP22 || SGI_IP27 || SGI_IP28 || SNI_RM || CPU_CAVIUM_OCTEON
37 diff --git a/arch/mips/include/asm/mach-ralink/rt288x.h b/arch/mips/include/asm/mach-ralink/rt288x.h
39 index 0000000..ad8b42d
41 +++ b/arch/mips/include/asm/mach-ralink/rt288x.h
44 + * This program is free software; you can redistribute it and/or modify it
45 + * under the terms of the GNU General Public License version 2 as published
46 + * by the Free Software Foundation.
48 + * Parts of this file are based on Ralink's 2.6.21 BSP
50 + * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
51 + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
52 + * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
55 +#ifndef _RT288X_REGS_H_
56 +#define _RT288X_REGS_H_
58 +#define RT2880_SYSC_BASE 0x00300000
60 +#define SYSC_REG_CHIP_NAME0 0x00
61 +#define SYSC_REG_CHIP_NAME1 0x04
62 +#define SYSC_REG_CHIP_ID 0x0c
63 +#define SYSC_REG_SYSTEM_CONFIG 0x10
64 +#define SYSC_REG_CLKCFG 0x30
66 +#define RT2880_CHIP_NAME0 0x38325452
67 +#define RT2880_CHIP_NAME1 0x20203038
69 +#define CHIP_ID_ID_MASK 0xff
70 +#define CHIP_ID_ID_SHIFT 8
71 +#define CHIP_ID_REV_MASK 0xff
73 +#define SYSTEM_CONFIG_CPUCLK_SHIFT 20
74 +#define SYSTEM_CONFIG_CPUCLK_MASK 0x3
75 +#define SYSTEM_CONFIG_CPUCLK_250 0x0
76 +#define SYSTEM_CONFIG_CPUCLK_266 0x1
77 +#define SYSTEM_CONFIG_CPUCLK_280 0x2
78 +#define SYSTEM_CONFIG_CPUCLK_300 0x3
80 +#define RT2880_GPIO_MODE_I2C BIT(0)
81 +#define RT2880_GPIO_MODE_UART0 BIT(1)
82 +#define RT2880_GPIO_MODE_SPI BIT(2)
83 +#define RT2880_GPIO_MODE_UART1 BIT(3)
84 +#define RT2880_GPIO_MODE_JTAG BIT(4)
85 +#define RT2880_GPIO_MODE_MDIO BIT(5)
86 +#define RT2880_GPIO_MODE_SDRAM BIT(6)
87 +#define RT2880_GPIO_MODE_PCI BIT(7)
89 +#define CLKCFG_SRAM_CS_N_WDT BIT(9)
92 diff --git a/arch/mips/ralink/Kconfig b/arch/mips/ralink/Kconfig
93 index a0b0197..6723b94 100644
94 --- a/arch/mips/ralink/Kconfig
95 +++ b/arch/mips/ralink/Kconfig
96 @@ -6,6 +6,9 @@ choice
98 Select Ralink MIPS SoC type.
105 select USB_ARCH_HAS_HCD
106 diff --git a/arch/mips/ralink/Makefile b/arch/mips/ralink/Makefile
107 index 939757f..6d826f2 100644
108 --- a/arch/mips/ralink/Makefile
109 +++ b/arch/mips/ralink/Makefile
112 obj-y := prom.o of.o reset.o clk.o irq.o
114 +obj-$(CONFIG_SOC_RT288X) += rt288x.o
115 obj-$(CONFIG_SOC_RT305X) += rt305x.o
117 obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
118 diff --git a/arch/mips/ralink/Platform b/arch/mips/ralink/Platform
119 index 6babd65..3f49e51 100644
120 --- a/arch/mips/ralink/Platform
121 +++ b/arch/mips/ralink/Platform
122 @@ -5,6 +5,11 @@ core-$(CONFIG_RALINK) += arch/mips/ralink/
123 cflags-$(CONFIG_RALINK) += -I$(srctree)/arch/mips/include/asm/mach-ralink
128 +load-$(CONFIG_SOC_RT288X) += 0xffffffff88000000
133 load-$(CONFIG_SOC_RT305X) += 0xffffffff80000000
134 diff --git a/arch/mips/ralink/rt288x.c b/arch/mips/ralink/rt288x.c
136 index 0000000..1e0788e
138 +++ b/arch/mips/ralink/rt288x.c
141 + * This program is free software; you can redistribute it and/or modify it
142 + * under the terms of the GNU General Public License version 2 as published
143 + * by the Free Software Foundation.
145 + * Parts of this file are based on Ralink's 2.6.21 BSP
147 + * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
148 + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
149 + * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
152 +#include <linux/kernel.h>
153 +#include <linux/init.h>
154 +#include <linux/module.h>
156 +#include <asm/mipsregs.h>
157 +#include <asm/mach-ralink/ralink_regs.h>
158 +#include <asm/mach-ralink/rt288x.h>
162 +static struct ralink_pinmux_grp mode_mux[] = {
165 + .mask = RT2880_GPIO_MODE_I2C,
170 + .mask = RT2880_GPIO_MODE_SPI,
174 + .name = "uartlite",
175 + .mask = RT2880_GPIO_MODE_UART0,
180 + .mask = RT2880_GPIO_MODE_JTAG,
185 + .mask = RT2880_GPIO_MODE_MDIO,
190 + .mask = RT2880_GPIO_MODE_SDRAM,
195 + .mask = RT2880_GPIO_MODE_PCI,
201 +static void rt288x_wdt_reset(void)
205 + /* enable WDT reset output on pin SRAM_CS_N */
206 + t = rt_sysc_r32(SYSC_REG_CLKCFG);
207 + t |= CLKCFG_SRAM_CS_N_WDT;
208 + rt_sysc_w32(t, SYSC_REG_CLKCFG);
211 +struct ralink_pinmux rt_gpio_pinmux = {
213 + .wdt_reset = rt288x_wdt_reset,
216 +void __init ralink_clk_init(void)
218 + unsigned long cpu_rate;
219 + u32 t = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG);
220 + t = ((t >> SYSTEM_CONFIG_CPUCLK_SHIFT) & SYSTEM_CONFIG_CPUCLK_MASK);
223 + case SYSTEM_CONFIG_CPUCLK_250:
224 + cpu_rate = 250000000;
226 + case SYSTEM_CONFIG_CPUCLK_266:
227 + cpu_rate = 266666667;
229 + case SYSTEM_CONFIG_CPUCLK_280:
230 + cpu_rate = 280000000;
232 + case SYSTEM_CONFIG_CPUCLK_300:
233 + cpu_rate = 300000000;
237 + ralink_clk_add("cpu", cpu_rate);
238 + ralink_clk_add("300100.timer", cpu_rate / 2);
239 + ralink_clk_add("300120.watchdog", cpu_rate / 2);
240 + ralink_clk_add("300500.uart", cpu_rate / 2);
241 + ralink_clk_add("300c00.uartlite", cpu_rate / 2);
242 + ralink_clk_add("400000.ethernet", cpu_rate / 2);
245 +void __init ralink_of_remap(void)
247 + rt_sysc_membase = plat_of_remap_node("ralink,rt2880-sysc");
248 + rt_memc_membase = plat_of_remap_node("ralink,rt2880-memc");
250 + if (!rt_sysc_membase || !rt_memc_membase)
251 + panic("Failed to remap core resources");
254 +void prom_soc_init(struct ralink_soc_info *soc_info)
256 + void __iomem *sysc = (void __iomem *) KSEG1ADDR(RT2880_SYSC_BASE);
262 + n0 = __raw_readl(sysc + SYSC_REG_CHIP_NAME0);
263 + n1 = __raw_readl(sysc + SYSC_REG_CHIP_NAME1);
264 + id = __raw_readl(sysc + SYSC_REG_CHIP_ID);
266 + if (n0 == RT2880_CHIP_NAME0 && n1 == RT2880_CHIP_NAME1) {
267 + soc_info->compatible = "ralink,r2880-soc";
270 + panic("rt288x: unknown SoC, n0:%08x n1:%08x", n0, n1);
273 + snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN,
274 + "Ralink %s id:%u rev:%u",
276 + (id >> CHIP_ID_ID_SHIFT) & CHIP_ID_ID_MASK,
277 + (id & CHIP_ID_REV_MASK));