1 From de5e1cd11d62d2e1a00210b757dad35e1372963b Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Tue, 22 Jan 2013 18:24:34 +0100
4 Subject: [PATCH 57/79] GPIO: MIPS: ralink: adds ralink gpio support
6 Add gpio driver for Ralink SoC. This driver makes the gpio core on
7 RT2880, RT305x, rt3352, rt3662, rt3883, rt5350 and mt7620 work.
9 Signed-off-by: John Crispin <blogic@openwrt.org>
11 arch/mips/Kconfig | 1 +
12 arch/mips/include/asm/mach-ralink/gpio.h | 24 +++
13 drivers/gpio/Kconfig | 6 +
14 drivers/gpio/Makefile | 1 +
15 drivers/gpio/gpio-ralink.c | 326 ++++++++++++++++++++++++++++++
16 5 files changed, 358 insertions(+)
17 create mode 100644 arch/mips/include/asm/mach-ralink/gpio.h
18 create mode 100644 drivers/gpio/gpio-ralink.c
20 diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
21 index b5fd476..2498972 100644
22 --- a/arch/mips/Kconfig
23 +++ b/arch/mips/Kconfig
24 @@ -449,6 +449,7 @@ config RALINK
25 select SYS_HAS_EARLY_PRINTK
26 select HAVE_MACH_CLKDEV
28 + select ARCH_REQUIRE_GPIOLIB
31 bool "SGI IP22 (Indy/Indigo2)"
32 diff --git a/arch/mips/include/asm/mach-ralink/gpio.h b/arch/mips/include/asm/mach-ralink/gpio.h
34 index 0000000..f68ee16
36 +++ b/arch/mips/include/asm/mach-ralink/gpio.h
39 + * Ralink SoC GPIO API support
41 + * Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
42 + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
44 + * This program is free software; you can redistribute it and/or modify it
45 + * under the terms of the GNU General Public License version 2 as published
46 + * by the Free Software Foundation.
50 +#ifndef __ASM_MACH_RALINK_GPIO_H
51 +#define __ASM_MACH_RALINK_GPIO_H
53 +#define ARCH_NR_GPIOS 128
54 +#include <asm-generic/gpio.h>
56 +#define gpio_get_value __gpio_get_value
57 +#define gpio_set_value __gpio_set_value
58 +#define gpio_cansleep __gpio_cansleep
59 +#define gpio_to_irq __gpio_to_irq
61 +#endif /* __ASM_MACH_RALINK_GPIO_H */
62 diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
63 index 682de75..2e6e81c 100644
64 --- a/drivers/gpio/Kconfig
65 +++ b/drivers/gpio/Kconfig
66 @@ -201,6 +201,12 @@ config GPIO_PXA
68 Say yes here to support the PXA GPIO device
71 + bool "Ralink GPIO Support"
74 + Say yes here to support the Ralink SoC GPIO device
76 config GPIO_SPEAR_SPICS
77 bool "ST SPEAr13xx SPI Chip Select as GPIO support"
79 diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
80 index c5aebd0..a00adfc 100644
81 --- a/drivers/gpio/Makefile
82 +++ b/drivers/gpio/Makefile
83 @@ -54,6 +54,7 @@ obj-$(CONFIG_GPIO_PCF857X) += gpio-pcf857x.o
84 obj-$(CONFIG_GPIO_PCH) += gpio-pch.o
85 obj-$(CONFIG_GPIO_PL061) += gpio-pl061.o
86 obj-$(CONFIG_GPIO_PXA) += gpio-pxa.o
87 +obj-$(CONFIG_GPIO_RALINK) += gpio-ralink.o
88 obj-$(CONFIG_GPIO_RC5T583) += gpio-rc5t583.o
89 obj-$(CONFIG_GPIO_RDC321X) += gpio-rdc321x.o
90 obj-$(CONFIG_PLAT_SAMSUNG) += gpio-samsung.o
91 diff --git a/drivers/gpio/gpio-ralink.c b/drivers/gpio/gpio-ralink.c
93 index 0000000..12984f1
95 +++ b/drivers/gpio/gpio-ralink.c
98 + * This program is free software; you can redistribute it and/or modify it
99 + * under the terms of the GNU General Public License version 2 as published
100 + * by the Free Software Foundation.
102 + * Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
103 + * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
106 +#include <linux/module.h>
107 +#include <linux/io.h>
108 +#include <linux/gpio.h>
109 +#include <linux/spinlock.h>
110 +#include <linux/platform_device.h>
111 +#include <linux/of_irq.h>
112 +#include <linux/irqdomain.h>
113 +#include <linux/interrupt.h>
115 +enum ralink_gpio_reg {
129 +struct ralink_gpio_chip {
130 + struct gpio_chip chip;
131 + u8 regs[GPIO_REG_MAX];
134 + void __iomem *membase;
135 + struct irq_domain *domain;
143 +static struct irq_domain *irq_map[MAP_MAX];
144 +static int irq_map_count;
145 +static atomic_t irq_refcount = ATOMIC_INIT(0);
147 +static inline struct ralink_gpio_chip *to_ralink_gpio(struct gpio_chip *chip)
149 + struct ralink_gpio_chip *rg;
151 + rg = container_of(chip, struct ralink_gpio_chip, chip);
156 +static inline void rt_gpio_w32(struct ralink_gpio_chip *rg, u8 reg, u32 val)
158 + iowrite32(val, rg->membase + rg->regs[reg]);
161 +static inline u32 rt_gpio_r32(struct ralink_gpio_chip *rg, u8 reg)
163 + return ioread32(rg->membase + rg->regs[reg]);
166 +static void ralink_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
168 + struct ralink_gpio_chip *rg = to_ralink_gpio(chip);
170 + rt_gpio_w32(rg, (value) ? GPIO_REG_SET : GPIO_REG_RESET, BIT(offset));
173 +static int ralink_gpio_get(struct gpio_chip *chip, unsigned offset)
175 + struct ralink_gpio_chip *rg = to_ralink_gpio(chip);
177 + return !!(rt_gpio_r32(rg, GPIO_REG_DATA) & BIT(offset));
180 +static int ralink_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
182 + struct ralink_gpio_chip *rg = to_ralink_gpio(chip);
183 + unsigned long flags;
186 + spin_lock_irqsave(&rg->lock, flags);
187 + t = rt_gpio_r32(rg, GPIO_REG_DIR);
189 + rt_gpio_w32(rg, GPIO_REG_DIR, t);
190 + spin_unlock_irqrestore(&rg->lock, flags);
195 +static int ralink_gpio_direction_output(struct gpio_chip *chip,
196 + unsigned offset, int value)
198 + struct ralink_gpio_chip *rg = to_ralink_gpio(chip);
199 + unsigned long flags;
202 + spin_lock_irqsave(&rg->lock, flags);
203 + ralink_gpio_set(chip, offset, value);
204 + t = rt_gpio_r32(rg, GPIO_REG_DIR);
206 + rt_gpio_w32(rg, GPIO_REG_DIR, t);
207 + spin_unlock_irqrestore(&rg->lock, flags);
212 +static int ralink_gpio_to_irq(struct gpio_chip *chip, unsigned pin)
214 + struct ralink_gpio_chip *rg = to_ralink_gpio(chip);
219 + ralink_gpio_direction_input(chip, pin);
221 + return irq_create_mapping(rg->domain, pin);
224 +static void ralink_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
228 + for (i = 0; i < irq_map_count; i++) {
229 + struct irq_domain *domain = irq_map[i];
230 + struct ralink_gpio_chip *rg = (struct ralink_gpio_chip *) domain->host_data;
231 + unsigned long pending = rt_gpio_r32(rg, GPIO_REG_INT);
234 + for_each_set_bit(bit, &pending, rg->chip.ngpio) {
235 + u32 map = irq_find_mapping(domain, bit);
236 + generic_handle_irq(map);
237 + rt_gpio_w32(rg, GPIO_REG_INT, BIT(bit));
242 +static void ralink_gpio_irq_unmask(struct irq_data *d)
244 + struct ralink_gpio_chip *rg = (struct ralink_gpio_chip *) d->domain->host_data;
245 + u32 val = rt_gpio_r32(rg, GPIO_REG_RENA);
246 + unsigned long flags;
248 + spin_lock_irqsave(&rg->lock, flags);
249 + rt_gpio_w32(rg, GPIO_REG_RENA, val | (BIT(d->hwirq) & rg->rising));
250 + rt_gpio_w32(rg, GPIO_REG_FENA, val | (BIT(d->hwirq) & rg->falling));
251 + spin_unlock_irqrestore(&rg->lock, flags);
254 +static void ralink_gpio_irq_mask(struct irq_data *d)
256 + struct ralink_gpio_chip *rg = (struct ralink_gpio_chip *) d->domain->host_data;
257 + u32 val = rt_gpio_r32(rg, GPIO_REG_RENA);
258 + unsigned long flags;
260 + spin_lock_irqsave(&rg->lock, flags);
261 + rt_gpio_w32(rg, GPIO_REG_FENA, val & ~BIT(d->hwirq));
262 + rt_gpio_w32(rg, GPIO_REG_RENA, val & ~BIT(d->hwirq));
263 + spin_unlock_irqrestore(&rg->lock, flags);
266 +static int ralink_gpio_irq_type(struct irq_data *d, unsigned int type)
268 + struct ralink_gpio_chip *rg = (struct ralink_gpio_chip *) d->domain->host_data;
269 + u32 mask = BIT(d->hwirq);
271 + if (type == IRQ_TYPE_PROBE) {
272 + if ((rg->rising | rg->falling) & mask)
275 + type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_RISING;
278 + if (type & IRQ_TYPE_EDGE_RISING)
279 + rg->rising |= mask;
281 + rg->rising &= mask;
283 + if (type & IRQ_TYPE_EDGE_RISING)
284 + rg->falling |= mask;
286 + rg->falling &= mask;
291 +static struct irq_chip ralink_gpio_irq_chip = {
293 + .irq_unmask = ralink_gpio_irq_unmask,
294 + .irq_mask = ralink_gpio_irq_mask,
295 + .irq_mask_ack = ralink_gpio_irq_mask,
296 + .irq_set_type = ralink_gpio_irq_type,
299 +static int gpio_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
301 + irq_set_chip_and_handler(irq, &ralink_gpio_irq_chip, handle_level_irq);
302 + irq_set_handler_data(irq, d);
307 +static const struct irq_domain_ops irq_domain_ops = {
308 + .xlate = irq_domain_xlate_onecell,
312 +static void ralink_gpio_irq_init(struct device_node *np, struct ralink_gpio_chip *rg)
314 + if (irq_map_count >= MAP_MAX)
317 + rg->irq = irq_of_parse_and_map(np, 0);
321 + rg->domain = irq_domain_add_linear(np, rg->chip.ngpio, &irq_domain_ops, rg);
323 + dev_err(rg->chip.dev, "irq_domain_add_linear failed\n");
327 + irq_map[irq_map_count++] = rg->domain;
329 + rt_gpio_w32(rg, GPIO_REG_RENA, 0x0);
330 + rt_gpio_w32(rg, GPIO_REG_FENA, 0x0);
332 + if (!atomic_read(&irq_refcount))
333 + irq_set_chained_handler(rg->irq, ralink_gpio_irq_handler);
334 + atomic_inc(&irq_refcount);
336 + dev_info(rg->chip.dev, "registering %d irq handlers\n", rg->chip.ngpio);
339 +static int ralink_gpio_probe(struct platform_device *pdev)
341 + struct device_node *np = pdev->dev.of_node;
342 + struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
343 + struct ralink_gpio_chip *rg;
344 + const __be32 *ngpio, *gpiobase;
347 + dev_err(&pdev->dev, "failed to find resource\n");
351 + rg = devm_kzalloc(&pdev->dev,
352 + sizeof(struct ralink_gpio_chip), GFP_KERNEL);
356 + rg->membase = devm_request_and_ioremap(&pdev->dev, res);
357 + if (!rg->membase) {
358 + dev_err(&pdev->dev, "cannot remap I/O memory region\n");
362 + if (of_property_read_u8_array(np, "ralink,register-map",
363 + rg->regs, GPIO_REG_MAX)) {
364 + dev_err(&pdev->dev, "failed to read register definition\n");
368 + ngpio = of_get_property(np, "ralink,num-gpios", NULL);
370 + dev_err(&pdev->dev, "failed to read number of pins\n");
374 + gpiobase = of_get_property(np, "ralink,gpio-base", NULL);
376 + rg->chip.base = be32_to_cpu(*gpiobase);
378 + rg->chip.base = -1;
380 + spin_lock_init(&rg->lock);
382 + rg->chip.dev = &pdev->dev;
383 + rg->chip.label = dev_name(&pdev->dev);
384 + rg->chip.of_node = np;
385 + rg->chip.ngpio = be32_to_cpu(*ngpio);
386 + rg->chip.direction_input = ralink_gpio_direction_input;
387 + rg->chip.direction_output = ralink_gpio_direction_output;
388 + rg->chip.get = ralink_gpio_get;
389 + rg->chip.set = ralink_gpio_set;
390 + rg->chip.to_irq = ralink_gpio_to_irq;
392 + /* set polarity to low for all lines */
393 + rt_gpio_w32(rg, GPIO_REG_POL, 0);
395 + dev_info(&pdev->dev, "registering %d gpios\n", rg->chip.ngpio);
397 + ralink_gpio_irq_init(np, rg);
399 + return gpiochip_add(&rg->chip);
402 +static const struct of_device_id ralink_gpio_match[] = {
403 + { .compatible = "ralink,rt2880-gpio" },
406 +MODULE_DEVICE_TABLE(of, ralink_gpio_match);
408 +static struct platform_driver ralink_gpio_driver = {
409 + .probe = ralink_gpio_probe,
411 + .name = "rt2880_gpio",
412 + .owner = THIS_MODULE,
413 + .of_match_table = ralink_gpio_match,
417 +static int __init ralink_gpio_init(void)
419 + return platform_driver_register(&ralink_gpio_driver);
422 +subsys_initcall(ralink_gpio_init);