1 From f63a0ea6c115e7b78bce70d78aaa813615e3d434 Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Sun, 27 Jan 2013 09:17:20 +0100
4 Subject: [PATCH 107/121] MIPS: ralink: adds support for RT2880 SoC family
6 Add support code for rt2880 SOC.
8 The code detects the SoC and registers the clk / pinmux settings.
10 Signed-off-by: John Crispin <blogic@openwrt.org>
12 arch/mips/Kconfig | 2 +-
13 arch/mips/include/asm/mach-ralink/rt288x.h | 49 ++++++++++
14 arch/mips/ralink/Kconfig | 3 +
15 arch/mips/ralink/Makefile | 1 +
16 arch/mips/ralink/Platform | 5 +
17 arch/mips/ralink/rt288x.c | 141 ++++++++++++++++++++++++++++
18 6 files changed, 200 insertions(+), 1 deletion(-)
19 create mode 100644 arch/mips/include/asm/mach-ralink/rt288x.h
20 create mode 100644 arch/mips/ralink/rt288x.c
22 diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
23 index cd2e21f..490d769 100644
24 --- a/arch/mips/Kconfig
25 +++ b/arch/mips/Kconfig
26 @@ -1152,7 +1152,7 @@ config BOOT_ELF32
28 config MIPS_L1_CACHE_SHIFT
30 - default "4" if MACH_DECSTATION || MIKROTIK_RB532 || PMC_MSP4200_EVAL
31 + default "4" if MACH_DECSTATION || MIKROTIK_RB532 || PMC_MSP4200_EVAL || SOC_RT288X
32 default "6" if MIPS_CPU_SCACHE
33 default "7" if SGI_IP22 || SGI_IP27 || SGI_IP28 || SNI_RM || CPU_CAVIUM_OCTEON
35 diff --git a/arch/mips/include/asm/mach-ralink/rt288x.h b/arch/mips/include/asm/mach-ralink/rt288x.h
37 index 0000000..ad8b42d
39 +++ b/arch/mips/include/asm/mach-ralink/rt288x.h
42 + * This program is free software; you can redistribute it and/or modify it
43 + * under the terms of the GNU General Public License version 2 as published
44 + * by the Free Software Foundation.
46 + * Parts of this file are based on Ralink's 2.6.21 BSP
48 + * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
49 + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
50 + * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
53 +#ifndef _RT288X_REGS_H_
54 +#define _RT288X_REGS_H_
56 +#define RT2880_SYSC_BASE 0x00300000
58 +#define SYSC_REG_CHIP_NAME0 0x00
59 +#define SYSC_REG_CHIP_NAME1 0x04
60 +#define SYSC_REG_CHIP_ID 0x0c
61 +#define SYSC_REG_SYSTEM_CONFIG 0x10
62 +#define SYSC_REG_CLKCFG 0x30
64 +#define RT2880_CHIP_NAME0 0x38325452
65 +#define RT2880_CHIP_NAME1 0x20203038
67 +#define CHIP_ID_ID_MASK 0xff
68 +#define CHIP_ID_ID_SHIFT 8
69 +#define CHIP_ID_REV_MASK 0xff
71 +#define SYSTEM_CONFIG_CPUCLK_SHIFT 20
72 +#define SYSTEM_CONFIG_CPUCLK_MASK 0x3
73 +#define SYSTEM_CONFIG_CPUCLK_250 0x0
74 +#define SYSTEM_CONFIG_CPUCLK_266 0x1
75 +#define SYSTEM_CONFIG_CPUCLK_280 0x2
76 +#define SYSTEM_CONFIG_CPUCLK_300 0x3
78 +#define RT2880_GPIO_MODE_I2C BIT(0)
79 +#define RT2880_GPIO_MODE_UART0 BIT(1)
80 +#define RT2880_GPIO_MODE_SPI BIT(2)
81 +#define RT2880_GPIO_MODE_UART1 BIT(3)
82 +#define RT2880_GPIO_MODE_JTAG BIT(4)
83 +#define RT2880_GPIO_MODE_MDIO BIT(5)
84 +#define RT2880_GPIO_MODE_SDRAM BIT(6)
85 +#define RT2880_GPIO_MODE_PCI BIT(7)
87 +#define CLKCFG_SRAM_CS_N_WDT BIT(9)
90 diff --git a/arch/mips/ralink/Kconfig b/arch/mips/ralink/Kconfig
91 index a0b0197..6723b94 100644
92 --- a/arch/mips/ralink/Kconfig
93 +++ b/arch/mips/ralink/Kconfig
94 @@ -6,6 +6,9 @@ choice
96 Select Ralink MIPS SoC type.
103 select USB_ARCH_HAS_HCD
104 diff --git a/arch/mips/ralink/Makefile b/arch/mips/ralink/Makefile
105 index 39ef249..ce83bfc 100644
106 --- a/arch/mips/ralink/Makefile
107 +++ b/arch/mips/ralink/Makefile
110 obj-y := prom.o of.o reset.o clk.o irq.o pinmux.o
112 +obj-$(CONFIG_SOC_RT288X) += rt288x.o
113 obj-$(CONFIG_SOC_RT305X) += rt305x.o
115 obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
116 diff --git a/arch/mips/ralink/Platform b/arch/mips/ralink/Platform
117 index 6babd65..3f49e51 100644
118 --- a/arch/mips/ralink/Platform
119 +++ b/arch/mips/ralink/Platform
120 @@ -5,6 +5,11 @@ core-$(CONFIG_RALINK) += arch/mips/ralink/
121 cflags-$(CONFIG_RALINK) += -I$(srctree)/arch/mips/include/asm/mach-ralink
126 +load-$(CONFIG_SOC_RT288X) += 0xffffffff88000000
131 load-$(CONFIG_SOC_RT305X) += 0xffffffff80000000
132 diff --git a/arch/mips/ralink/rt288x.c b/arch/mips/ralink/rt288x.c
134 index 0000000..37faff0
136 +++ b/arch/mips/ralink/rt288x.c
139 + * This program is free software; you can redistribute it and/or modify it
140 + * under the terms of the GNU General Public License version 2 as published
141 + * by the Free Software Foundation.
143 + * Parts of this file are based on Ralink's 2.6.21 BSP
145 + * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
146 + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
147 + * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
150 +#include <linux/kernel.h>
151 +#include <linux/init.h>
152 +#include <linux/module.h>
154 +#include <asm/mipsregs.h>
155 +#include <asm/mach-ralink/ralink_regs.h>
156 +#include <asm/mach-ralink/rt288x.h>
160 +struct ralink_pinmux_grp mode_mux[] = {
163 + .mask = RT2880_GPIO_MODE_I2C,
168 + .mask = RT2880_GPIO_MODE_SPI,
172 + .name = "uartlite",
173 + .mask = RT2880_GPIO_MODE_UART0,
178 + .mask = RT2880_GPIO_MODE_JTAG,
183 + .mask = RT2880_GPIO_MODE_MDIO,
188 + .mask = RT2880_GPIO_MODE_SDRAM,
193 + .mask = RT2880_GPIO_MODE_PCI,
199 +void rt288x_wdt_reset(void)
203 + /* enable WDT reset output on pin SRAM_CS_N */
204 + t = rt_sysc_r32(SYSC_REG_CLKCFG);
205 + t |= CLKCFG_SRAM_CS_N_WDT;
206 + rt_sysc_w32(t, SYSC_REG_CLKCFG);
209 +struct ralink_pinmux rt_pinmux = {
211 + .wdt_reset = rt288x_wdt_reset,
214 +void ralink_usb_platform(void)
218 +void __init ralink_clk_init(void)
220 + unsigned long cpu_rate;
221 + u32 t = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG);
222 + t = ((t >> SYSTEM_CONFIG_CPUCLK_SHIFT) & SYSTEM_CONFIG_CPUCLK_MASK);
225 + case SYSTEM_CONFIG_CPUCLK_250:
226 + cpu_rate = 250000000;
228 + case SYSTEM_CONFIG_CPUCLK_266:
229 + cpu_rate = 266666667;
231 + case SYSTEM_CONFIG_CPUCLK_280:
232 + cpu_rate = 280000000;
234 + case SYSTEM_CONFIG_CPUCLK_300:
235 + cpu_rate = 300000000;
239 + ralink_clk_add("cpu", cpu_rate);
240 + ralink_clk_add("10000100.timer", cpu_rate / 2);
241 + ralink_clk_add("10000500.uart", cpu_rate / 2);
242 + ralink_clk_add("10000c00.uartlite", cpu_rate / 2);
245 +void __init ralink_of_remap(void)
247 + rt_sysc_membase = plat_of_remap_node("ralink,rt288x-sysc");
248 + rt_memc_membase = plat_of_remap_node("ralink,rt288x-memc");
250 + if (!rt_sysc_membase || !rt_memc_membase)
251 + panic("Failed to remap core resources");
254 +void prom_soc_init(struct ralink_soc_info *soc_info)
256 + void __iomem *sysc = (void __iomem *) KSEG1ADDR(RT2880_SYSC_BASE);
262 + n0 = __raw_readl(sysc + SYSC_REG_CHIP_NAME0);
263 + n1 = __raw_readl(sysc + SYSC_REG_CHIP_NAME1);
264 + id = __raw_readl(sysc + SYSC_REG_CHIP_ID);
266 + if (n0 == RT2880_CHIP_NAME0 && n1 == RT2880_CHIP_NAME1) {
267 + soc_info->compatible = "ralink,r2880-soc";
270 + panic("rt288x: unknown SoC, n0:%08x n1:%08x", n0, n1);
273 + snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN,
274 + "Ralink %s id:%u rev:%u",
276 + (id >> CHIP_ID_ID_SHIFT) & CHIP_ID_ID_MASK,
277 + (id & CHIP_ID_REV_MASK));