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package: fix insmod on install
[openwrt/openwrt.git] / target / linux / ramips / patches-3.8 / 0112-MIPS-ralink-adds-support-for-RT3883-SoC-family.patch
1 From 5eb4dfe5072595e0706de3364f2da45378dbaca6 Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Sun, 27 Jan 2013 09:39:02 +0100
4 Subject: [PATCH 112/137] MIPS: ralink: adds support for RT3883 SoC family
5
6 Add support code for rt3883 SOC.
7
8 The code detects the SoC and registers the clk / pinmux settings.
9
10 Signed-off-by: John Crispin <blogic@openwrt.org>
11 Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
12 Patchwork: http://patchwork.linux-mips.org/patch/5185/
13 ---
14 arch/mips/include/asm/mach-ralink/rt3883.h | 247 ++++++++++++++++++++++++++++
15 arch/mips/ralink/Kconfig | 5 +
16 arch/mips/ralink/Makefile | 1 +
17 arch/mips/ralink/Platform | 5 +
18 arch/mips/ralink/rt3883.c | 242 +++++++++++++++++++++++++++
19 5 files changed, 500 insertions(+)
20 create mode 100644 arch/mips/include/asm/mach-ralink/rt3883.h
21 create mode 100644 arch/mips/ralink/rt3883.c
22
23 --- /dev/null
24 +++ b/arch/mips/include/asm/mach-ralink/rt3883.h
25 @@ -0,0 +1,248 @@
26 +/*
27 + * Ralink RT3662/RT3883 SoC register definitions
28 + *
29 + * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
30 + *
31 + * This program is free software; you can redistribute it and/or modify it
32 + * under the terms of the GNU General Public License version 2 as published
33 + * by the Free Software Foundation.
34 + */
35 +
36 +#ifndef _RT3883_REGS_H_
37 +#define _RT3883_REGS_H_
38 +
39 +#include <linux/bitops.h>
40 +
41 +#define RT3883_SDRAM_BASE 0x00000000
42 +#define RT3883_SYSC_BASE 0x10000000
43 +#define RT3883_TIMER_BASE 0x10000100
44 +#define RT3883_INTC_BASE 0x10000200
45 +#define RT3883_MEMC_BASE 0x10000300
46 +#define RT3883_UART0_BASE 0x10000500
47 +#define RT3883_PIO_BASE 0x10000600
48 +#define RT3883_FSCC_BASE 0x10000700
49 +#define RT3883_NANDC_BASE 0x10000810
50 +#define RT3883_I2C_BASE 0x10000900
51 +#define RT3883_I2S_BASE 0x10000a00
52 +#define RT3883_SPI_BASE 0x10000b00
53 +#define RT3883_UART1_BASE 0x10000c00
54 +#define RT3883_PCM_BASE 0x10002000
55 +#define RT3883_GDMA_BASE 0x10002800
56 +#define RT3883_CODEC1_BASE 0x10003000
57 +#define RT3883_CODEC2_BASE 0x10003800
58 +#define RT3883_FE_BASE 0x10100000
59 +#define RT3883_ROM_BASE 0x10118000
60 +#define RT3883_USBDEV_BASE 0x10112000
61 +#define RT3883_PCI_BASE 0x10140000
62 +#define RT3883_WLAN_BASE 0x10180000
63 +#define RT3883_USBHOST_BASE 0x101c0000
64 +#define RT3883_BOOT_BASE 0x1c000000
65 +#define RT3883_SRAM_BASE 0x1e000000
66 +#define RT3883_PCIMEM_BASE 0x20000000
67 +
68 +#define RT3883_EHCI_BASE (RT3883_USBHOST_BASE)
69 +#define RT3883_OHCI_BASE (RT3883_USBHOST_BASE + 0x1000)
70 +
71 +#define RT3883_SYSC_SIZE 0x100
72 +#define RT3883_TIMER_SIZE 0x100
73 +#define RT3883_INTC_SIZE 0x100
74 +#define RT3883_MEMC_SIZE 0x100
75 +#define RT3883_UART0_SIZE 0x100
76 +#define RT3883_UART1_SIZE 0x100
77 +#define RT3883_PIO_SIZE 0x100
78 +#define RT3883_FSCC_SIZE 0x100
79 +#define RT3883_NANDC_SIZE 0x0f0
80 +#define RT3883_I2C_SIZE 0x100
81 +#define RT3883_I2S_SIZE 0x100
82 +#define RT3883_SPI_SIZE 0x100
83 +#define RT3883_PCM_SIZE 0x800
84 +#define RT3883_GDMA_SIZE 0x800
85 +#define RT3883_CODEC1_SIZE 0x800
86 +#define RT3883_CODEC2_SIZE 0x800
87 +#define RT3883_FE_SIZE 0x10000
88 +#define RT3883_ROM_SIZE 0x4000
89 +#define RT3883_USBDEV_SIZE 0x4000
90 +#define RT3883_PCI_SIZE 0x40000
91 +#define RT3883_WLAN_SIZE 0x40000
92 +#define RT3883_USBHOST_SIZE 0x40000
93 +#define RT3883_BOOT_SIZE (32 * 1024 * 1024)
94 +#define RT3883_SRAM_SIZE (32 * 1024 * 1024)
95 +
96 +/* SYSC registers */
97 +#define RT3883_SYSC_REG_CHIPID0_3 0x00 /* Chip ID 0 */
98 +#define RT3883_SYSC_REG_CHIPID4_7 0x04 /* Chip ID 1 */
99 +#define RT3883_SYSC_REG_REVID 0x0c /* Chip Revision Identification */
100 +#define RT3883_SYSC_REG_SYSCFG0 0x10 /* System Configuration 0 */
101 +#define RT3883_SYSC_REG_SYSCFG1 0x14 /* System Configuration 1 */
102 +#define RT3883_SYSC_REG_CLKCFG0 0x2c /* Clock Configuration 0 */
103 +#define RT3883_SYSC_REG_CLKCFG1 0x30 /* Clock Configuration 1 */
104 +#define RT3883_SYSC_REG_RSTCTRL 0x34 /* Reset Control*/
105 +#define RT3883_SYSC_REG_RSTSTAT 0x38 /* Reset Status*/
106 +#define RT3883_SYSC_REG_USB_PS 0x5c /* USB Power saving control */
107 +#define RT3883_SYSC_REG_GPIO_MODE 0x60 /* GPIO Purpose Select */
108 +#define RT3883_SYSC_REG_PCIE_CLK_GEN0 0x7c
109 +#define RT3883_SYSC_REG_PCIE_CLK_GEN1 0x80
110 +#define RT3883_SYSC_REG_PCIE_CLK_GEN2 0x84
111 +#define RT3883_SYSC_REG_PMU 0x88
112 +#define RT3883_SYSC_REG_PMU1 0x8c
113 +
114 +#define RT3883_CHIP_NAME0 0x38335452
115 +#define RT3883_CHIP_NAME1 0x20203338
116 +
117 +#define RT3883_REVID_VER_ID_MASK 0x0f
118 +#define RT3883_REVID_VER_ID_SHIFT 8
119 +#define RT3883_REVID_ECO_ID_MASK 0x0f
120 +
121 +#define RT3883_SYSCFG0_DRAM_TYPE_DDR2 BIT(17)
122 +#define RT3883_SYSCFG0_CPUCLK_SHIFT 8
123 +#define RT3883_SYSCFG0_CPUCLK_MASK 0x3
124 +#define RT3883_SYSCFG0_CPUCLK_250 0x0
125 +#define RT3883_SYSCFG0_CPUCLK_384 0x1
126 +#define RT3883_SYSCFG0_CPUCLK_480 0x2
127 +#define RT3883_SYSCFG0_CPUCLK_500 0x3
128 +
129 +#define RT3883_SYSCFG1_USB0_HOST_MODE BIT(10)
130 +#define RT3883_SYSCFG1_PCIE_RC_MODE BIT(8)
131 +#define RT3883_SYSCFG1_PCI_HOST_MODE BIT(7)
132 +#define RT3883_SYSCFG1_PCI_66M_MODE BIT(6)
133 +#define RT3883_SYSCFG1_GPIO2_AS_WDT_OUT BIT(2)
134 +
135 +#define RT3883_CLKCFG1_PCIE_CLK_EN BIT(21)
136 +#define RT3883_CLKCFG1_UPHY1_CLK_EN BIT(20)
137 +#define RT3883_CLKCFG1_PCI_CLK_EN BIT(19)
138 +#define RT3883_CLKCFG1_UPHY0_CLK_EN BIT(18)
139 +
140 +#define RT3883_GPIO_MODE_I2C BIT(0)
141 +#define RT3883_GPIO_MODE_SPI BIT(1)
142 +#define RT3883_GPIO_MODE_UART0_SHIFT 2
143 +#define RT3883_GPIO_MODE_UART0_MASK 0x7
144 +#define RT3883_GPIO_MODE_UART0(x) ((x) << RT3883_GPIO_MODE_UART0_SHIFT)
145 +#define RT3883_GPIO_MODE_UARTF 0x0
146 +#define RT3883_GPIO_MODE_PCM_UARTF 0x1
147 +#define RT3883_GPIO_MODE_PCM_I2S 0x2
148 +#define RT3883_GPIO_MODE_I2S_UARTF 0x3
149 +#define RT3883_GPIO_MODE_PCM_GPIO 0x4
150 +#define RT3883_GPIO_MODE_GPIO_UARTF 0x5
151 +#define RT3883_GPIO_MODE_GPIO_I2S 0x6
152 +#define RT3883_GPIO_MODE_GPIO 0x7
153 +#define RT3883_GPIO_MODE_UART1 BIT(5)
154 +#define RT3883_GPIO_MODE_JTAG BIT(6)
155 +#define RT3883_GPIO_MODE_MDIO BIT(7)
156 +#define RT3883_GPIO_MODE_GE1 BIT(9)
157 +#define RT3883_GPIO_MODE_GE2 BIT(10)
158 +#define RT3883_GPIO_MODE_PCI_SHIFT 11
159 +#define RT3883_GPIO_MODE_PCI_MASK 0x7
160 +#define RT3883_GPIO_MODE_PCI (RT3883_GPIO_MODE_PCI_MASK << RT3883_GPIO_MODE_PCI_SHIFT)
161 +#define RT3883_GPIO_MODE_LNA_A_SHIFT 16
162 +#define RT3883_GPIO_MODE_LNA_A_MASK 0x3
163 +#define _RT3883_GPIO_MODE_LNA_A(_x) ((_x) << RT3883_GPIO_MODE_LNA_A_SHIFT)
164 +#define RT3883_GPIO_MODE_LNA_A_GPIO 0x3
165 +#define RT3883_GPIO_MODE_LNA_A _RT3883_GPIO_MODE_LNA_A(RT3883_GPIO_MODE_LNA_A_MASK)
166 +#define RT3883_GPIO_MODE_LNA_G_SHIFT 18
167 +#define RT3883_GPIO_MODE_LNA_G_MASK 0x3
168 +#define _RT3883_GPIO_MODE_LNA_G(_x) ((_x) << RT3883_GPIO_MODE_LNA_G_SHIFT)
169 +#define RT3883_GPIO_MODE_LNA_G_GPIO 0x3
170 +#define RT3883_GPIO_MODE_LNA_G _RT3883_GPIO_MODE_LNA_G(RT3883_GPIO_MODE_LNA_G_MASK)
171 +
172 +#define RT3883_GPIO_I2C_SD 1
173 +#define RT3883_GPIO_I2C_SCLK 2
174 +#define RT3883_GPIO_SPI_CS0 3
175 +#define RT3883_GPIO_SPI_CLK 4
176 +#define RT3883_GPIO_SPI_MOSI 5
177 +#define RT3883_GPIO_SPI_MISO 6
178 +#define RT3883_GPIO_7 7
179 +#define RT3883_GPIO_10 10
180 +#define RT3883_GPIO_11 11
181 +#define RT3883_GPIO_14 14
182 +#define RT3883_GPIO_UART1_TXD 15
183 +#define RT3883_GPIO_UART1_RXD 16
184 +#define RT3883_GPIO_JTAG_TDO 17
185 +#define RT3883_GPIO_JTAG_TDI 18
186 +#define RT3883_GPIO_JTAG_TMS 19
187 +#define RT3883_GPIO_JTAG_TCLK 20
188 +#define RT3883_GPIO_JTAG_TRST_N 21
189 +#define RT3883_GPIO_MDIO_MDC 22
190 +#define RT3883_GPIO_MDIO_MDIO 23
191 +#define RT3883_GPIO_LNA_PE_A0 32
192 +#define RT3883_GPIO_LNA_PE_A1 33
193 +#define RT3883_GPIO_LNA_PE_A2 34
194 +#define RT3883_GPIO_LNA_PE_G0 35
195 +#define RT3883_GPIO_LNA_PE_G1 36
196 +#define RT3883_GPIO_LNA_PE_G2 37
197 +#define RT3883_GPIO_PCI_AD0 40
198 +#define RT3883_GPIO_PCI_AD31 71
199 +#define RT3883_GPIO_GE2_TXD0 72
200 +#define RT3883_GPIO_GE2_TXD1 73
201 +#define RT3883_GPIO_GE2_TXD2 74
202 +#define RT3883_GPIO_GE2_TXD3 75
203 +#define RT3883_GPIO_GE2_TXEN 76
204 +#define RT3883_GPIO_GE2_TXCLK 77
205 +#define RT3883_GPIO_GE2_RXD0 78
206 +#define RT3883_GPIO_GE2_RXD1 79
207 +#define RT3883_GPIO_GE2_RXD2 80
208 +#define RT3883_GPIO_GE2_RXD3 81
209 +#define RT3883_GPIO_GE2_RXDV 82
210 +#define RT3883_GPIO_GE2_RXCLK 83
211 +#define RT3883_GPIO_GE1_TXD0 84
212 +#define RT3883_GPIO_GE1_TXD1 85
213 +#define RT3883_GPIO_GE1_TXD2 86
214 +#define RT3883_GPIO_GE1_TXD3 87
215 +#define RT3883_GPIO_GE1_TXEN 88
216 +#define RT3883_GPIO_GE1_TXCLK 89
217 +#define RT3883_GPIO_GE1_RXD0 90
218 +#define RT3883_GPIO_GE1_RXD1 91
219 +#define RT3883_GPIO_GE1_RXD2 92
220 +#define RT3883_GPIO_GE1_RXD3 93
221 +#define RT3883_GPIO_GE1_RXDV 94
222 +#define RT3883_GPIO_GE1_RXCLK 95
223 +
224 +#define RT3883_RSTCTRL_PCIE_PCI_PDM BIT(27)
225 +#define RT3883_RSTCTRL_FLASH BIT(26)
226 +#define RT3883_RSTCTRL_UDEV BIT(25)
227 +#define RT3883_RSTCTRL_PCI BIT(24)
228 +#define RT3883_RSTCTRL_PCIE BIT(23)
229 +#define RT3883_RSTCTRL_UHST BIT(22)
230 +#define RT3883_RSTCTRL_FE BIT(21)
231 +#define RT3883_RSTCTRL_WLAN BIT(20)
232 +#define RT3883_RSTCTRL_UART1 BIT(29)
233 +#define RT3883_RSTCTRL_SPI BIT(18)
234 +#define RT3883_RSTCTRL_I2S BIT(17)
235 +#define RT3883_RSTCTRL_I2C BIT(16)
236 +#define RT3883_RSTCTRL_NAND BIT(15)
237 +#define RT3883_RSTCTRL_DMA BIT(14)
238 +#define RT3883_RSTCTRL_PIO BIT(13)
239 +#define RT3883_RSTCTRL_UART BIT(12)
240 +#define RT3883_RSTCTRL_PCM BIT(11)
241 +#define RT3883_RSTCTRL_MC BIT(10)
242 +#define RT3883_RSTCTRL_INTC BIT(9)
243 +#define RT3883_RSTCTRL_TIMER BIT(8)
244 +#define RT3883_RSTCTRL_SYS BIT(0)
245 +
246 +#define RT3883_INTC_INT_SYSCTL BIT(0)
247 +#define RT3883_INTC_INT_TIMER0 BIT(1)
248 +#define RT3883_INTC_INT_TIMER1 BIT(2)
249 +#define RT3883_INTC_INT_IA BIT(3)
250 +#define RT3883_INTC_INT_PCM BIT(4)
251 +#define RT3883_INTC_INT_UART0 BIT(5)
252 +#define RT3883_INTC_INT_PIO BIT(6)
253 +#define RT3883_INTC_INT_DMA BIT(7)
254 +#define RT3883_INTC_INT_NAND BIT(8)
255 +#define RT3883_INTC_INT_PERFC BIT(9)
256 +#define RT3883_INTC_INT_I2S BIT(10)
257 +#define RT3883_INTC_INT_UART1 BIT(12)
258 +#define RT3883_INTC_INT_UHST BIT(18)
259 +#define RT3883_INTC_INT_UDEV BIT(19)
260 +
261 +/* FLASH/SRAM/Codec Controller registers */
262 +#define RT3883_FSCC_REG_FLASH_CFG0 0x00
263 +#define RT3883_FSCC_REG_FLASH_CFG1 0x04
264 +#define RT3883_FSCC_REG_CODEC_CFG0 0x40
265 +#define RT3883_FSCC_REG_CODEC_CFG1 0x44
266 +
267 +#define RT3883_FLASH_CFG_WIDTH_SHIFT 26
268 +#define RT3883_FLASH_CFG_WIDTH_MASK 0x3
269 +#define RT3883_FLASH_CFG_WIDTH_8BIT 0x0
270 +#define RT3883_FLASH_CFG_WIDTH_16BIT 0x1
271 +#define RT3883_FLASH_CFG_WIDTH_32BIT 0x2
272 +
273 +#endif /* _RT3883_REGS_H_ */
274 --- a/arch/mips/ralink/Kconfig
275 +++ b/arch/mips/ralink/Kconfig
276 @@ -15,6 +15,11 @@ choice
277 select USB_ARCH_HAS_OHCI
278 select USB_ARCH_HAS_EHCI
279
280 + config SOC_RT3883
281 + bool "RT3883"
282 + select USB_ARCH_HAS_OHCI
283 + select USB_ARCH_HAS_EHCI
284 +
285 endchoice
286
287 choice
288 --- a/arch/mips/ralink/Makefile
289 +++ b/arch/mips/ralink/Makefile
290 @@ -10,6 +10,7 @@ obj-y := prom.o of.o reset.o clk.o irq.o
291
292 obj-$(CONFIG_SOC_RT288X) += rt288x.o
293 obj-$(CONFIG_SOC_RT305X) += rt305x.o
294 +obj-$(CONFIG_SOC_RT3883) += rt3883.o
295
296 obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
297
298 --- a/arch/mips/ralink/Platform
299 +++ b/arch/mips/ralink/Platform
300 @@ -13,3 +13,8 @@ load-$(CONFIG_SOC_RT288X) += 0xffffffff8
301 # Ralink RT305x
302 #
303 load-$(CONFIG_SOC_RT305X) += 0xffffffff80000000
304 +
305 +#
306 +# Ralink RT3883
307 +#
308 +load-$(CONFIG_SOC_RT3883) += 0xffffffff80000000
309 --- /dev/null
310 +++ b/arch/mips/ralink/rt3883.c
311 @@ -0,0 +1,242 @@
312 +/*
313 + * This program is free software; you can redistribute it and/or modify it
314 + * under the terms of the GNU General Public License version 2 as published
315 + * by the Free Software Foundation.
316 + *
317 + * Parts of this file are based on Ralink's 2.6.21 BSP
318 + *
319 + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
320 + * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
321 + * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
322 + */
323 +
324 +#include <linux/kernel.h>
325 +#include <linux/init.h>
326 +#include <linux/module.h>
327 +
328 +#include <asm/mipsregs.h>
329 +#include <asm/mach-ralink/ralink_regs.h>
330 +#include <asm/mach-ralink/rt3883.h>
331 +
332 +#include "common.h"
333 +
334 +static struct ralink_pinmux_grp mode_mux[] = {
335 + {
336 + .name = "i2c",
337 + .mask = RT3883_GPIO_MODE_I2C,
338 + .gpio_first = RT3883_GPIO_I2C_SD,
339 + .gpio_last = RT3883_GPIO_I2C_SCLK,
340 + }, {
341 + .name = "spi",
342 + .mask = RT3883_GPIO_MODE_SPI,
343 + .gpio_first = RT3883_GPIO_SPI_CS0,
344 + .gpio_last = RT3883_GPIO_SPI_MISO,
345 + }, {
346 + .name = "uartlite",
347 + .mask = RT3883_GPIO_MODE_UART1,
348 + .gpio_first = RT3883_GPIO_UART1_TXD,
349 + .gpio_last = RT3883_GPIO_UART1_RXD,
350 + }, {
351 + .name = "jtag",
352 + .mask = RT3883_GPIO_MODE_JTAG,
353 + .gpio_first = RT3883_GPIO_JTAG_TDO,
354 + .gpio_last = RT3883_GPIO_JTAG_TCLK,
355 + }, {
356 + .name = "mdio",
357 + .mask = RT3883_GPIO_MODE_MDIO,
358 + .gpio_first = RT3883_GPIO_MDIO_MDC,
359 + .gpio_last = RT3883_GPIO_MDIO_MDIO,
360 + }, {
361 + .name = "ge1",
362 + .mask = RT3883_GPIO_MODE_GE1,
363 + .gpio_first = RT3883_GPIO_GE1_TXD0,
364 + .gpio_last = RT3883_GPIO_GE1_RXCLK,
365 + }, {
366 + .name = "ge2",
367 + .mask = RT3883_GPIO_MODE_GE2,
368 + .gpio_first = RT3883_GPIO_GE2_TXD0,
369 + .gpio_last = RT3883_GPIO_GE2_RXCLK,
370 + }, {
371 + .name = "pci",
372 + .mask = RT3883_GPIO_MODE_PCI,
373 + .gpio_first = RT3883_GPIO_PCI_AD0,
374 + .gpio_last = RT3883_GPIO_PCI_AD31,
375 + }, {
376 + .name = "lna a",
377 + .mask = RT3883_GPIO_MODE_LNA_A,
378 + .gpio_first = RT3883_GPIO_LNA_PE_A0,
379 + .gpio_last = RT3883_GPIO_LNA_PE_A2,
380 + }, {
381 + .name = "lna g",
382 + .mask = RT3883_GPIO_MODE_LNA_G,
383 + .gpio_first = RT3883_GPIO_LNA_PE_G0,
384 + .gpio_last = RT3883_GPIO_LNA_PE_G2,
385 + }, {0}
386 +};
387 +
388 +static struct ralink_pinmux_grp uart_mux[] = {
389 + {
390 + .name = "uartf",
391 + .mask = RT3883_GPIO_MODE_UARTF,
392 + .gpio_first = RT3883_GPIO_7,
393 + .gpio_last = RT3883_GPIO_14,
394 + }, {
395 + .name = "pcm uartf",
396 + .mask = RT3883_GPIO_MODE_PCM_UARTF,
397 + .gpio_first = RT3883_GPIO_7,
398 + .gpio_last = RT3883_GPIO_14,
399 + }, {
400 + .name = "pcm i2s",
401 + .mask = RT3883_GPIO_MODE_PCM_I2S,
402 + .gpio_first = RT3883_GPIO_7,
403 + .gpio_last = RT3883_GPIO_14,
404 + }, {
405 + .name = "i2s uartf",
406 + .mask = RT3883_GPIO_MODE_I2S_UARTF,
407 + .gpio_first = RT3883_GPIO_7,
408 + .gpio_last = RT3883_GPIO_14,
409 + }, {
410 + .name = "pcm gpio",
411 + .mask = RT3883_GPIO_MODE_PCM_GPIO,
412 + .gpio_first = RT3883_GPIO_11,
413 + .gpio_last = RT3883_GPIO_14,
414 + }, {
415 + .name = "gpio uartf",
416 + .mask = RT3883_GPIO_MODE_GPIO_UARTF,
417 + .gpio_first = RT3883_GPIO_7,
418 + .gpio_last = RT3883_GPIO_10,
419 + }, {
420 + .name = "gpio i2s",
421 + .mask = RT3883_GPIO_MODE_GPIO_I2S,
422 + .gpio_first = RT3883_GPIO_7,
423 + .gpio_last = RT3883_GPIO_10,
424 + }, {
425 + .name = "gpio",
426 + .mask = RT3883_GPIO_MODE_GPIO,
427 + }, {0}
428 +};
429 +
430 +static struct ralink_pinmux_grp pci_mux[] = {
431 + {
432 + .name = "pci-dev",
433 + .mask = 0,
434 + .gpio_first = RT3883_GPIO_PCI_AD0,
435 + .gpio_last = RT3883_GPIO_PCI_AD31,
436 + }, {
437 + .name = "pci-host2",
438 + .mask = 1,
439 + .gpio_first = RT3883_GPIO_PCI_AD0,
440 + .gpio_last = RT3883_GPIO_PCI_AD31,
441 + }, {
442 + .name = "pci-host1",
443 + .mask = 2,
444 + .gpio_first = RT3883_GPIO_PCI_AD0,
445 + .gpio_last = RT3883_GPIO_PCI_AD31,
446 + }, {
447 + .name = "pci-fnc",
448 + .mask = 3,
449 + .gpio_first = RT3883_GPIO_PCI_AD0,
450 + .gpio_last = RT3883_GPIO_PCI_AD31,
451 + }, {
452 + .name = "pci-gpio",
453 + .mask = 7,
454 + .gpio_first = RT3883_GPIO_PCI_AD0,
455 + .gpio_last = RT3883_GPIO_PCI_AD31,
456 + }, {0}
457 +};
458 +
459 +static void rt3883_wdt_reset(void)
460 +{
461 + u32 t;
462 +
463 + /* enable WDT reset output on GPIO 2 */
464 + t = rt_sysc_r32(RT3883_SYSC_REG_SYSCFG1);
465 + t |= RT3883_SYSCFG1_GPIO2_AS_WDT_OUT;
466 + rt_sysc_w32(t, RT3883_SYSC_REG_SYSCFG1);
467 +}
468 +
469 +struct ralink_pinmux rt_gpio_pinmux = {
470 + .mode = mode_mux,
471 + .uart = uart_mux,
472 + .uart_shift = RT3883_GPIO_MODE_UART0_SHIFT,
473 + .uart_mask = RT3883_GPIO_MODE_GPIO,
474 + .wdt_reset = rt3883_wdt_reset,
475 + .pci = pci_mux,
476 + .pci_shift = RT3883_GPIO_MODE_PCI_SHIFT,
477 + .pci_mask = RT3883_GPIO_MODE_PCI_MASK,
478 +};
479 +
480 +void __init ralink_clk_init(void)
481 +{
482 + unsigned long cpu_rate, sys_rate;
483 + u32 syscfg0;
484 + u32 clksel;
485 + u32 ddr2;
486 +
487 + syscfg0 = rt_sysc_r32(RT3883_SYSC_REG_SYSCFG0);
488 + clksel = ((syscfg0 >> RT3883_SYSCFG0_CPUCLK_SHIFT) &
489 + RT3883_SYSCFG0_CPUCLK_MASK);
490 + ddr2 = syscfg0 & RT3883_SYSCFG0_DRAM_TYPE_DDR2;
491 +
492 + switch (clksel) {
493 + case RT3883_SYSCFG0_CPUCLK_250:
494 + cpu_rate = 250000000;
495 + sys_rate = (ddr2) ? 125000000 : 83000000;
496 + break;
497 + case RT3883_SYSCFG0_CPUCLK_384:
498 + cpu_rate = 384000000;
499 + sys_rate = (ddr2) ? 128000000 : 96000000;
500 + break;
501 + case RT3883_SYSCFG0_CPUCLK_480:
502 + cpu_rate = 480000000;
503 + sys_rate = (ddr2) ? 160000000 : 120000000;
504 + break;
505 + case RT3883_SYSCFG0_CPUCLK_500:
506 + cpu_rate = 500000000;
507 + sys_rate = (ddr2) ? 166000000 : 125000000;
508 + break;
509 + }
510 +
511 + ralink_clk_add("cpu", cpu_rate);
512 + ralink_clk_add("10000100.timer", sys_rate);
513 + ralink_clk_add("10000120.watchdog", sys_rate);
514 + ralink_clk_add("10000500.uart", 40000000);
515 + ralink_clk_add("10000b00.spi", sys_rate);
516 + ralink_clk_add("10000c00.uartlite", 40000000);
517 + ralink_clk_add("10100000.ethernet", sys_rate);
518 +}
519 +
520 +void __init ralink_of_remap(void)
521 +{
522 + rt_sysc_membase = plat_of_remap_node("ralink,rt3883-sysc");
523 + rt_memc_membase = plat_of_remap_node("ralink,rt3883-memc");
524 +
525 + if (!rt_sysc_membase || !rt_memc_membase)
526 + panic("Failed to remap core resources");
527 +}
528 +
529 +void prom_soc_init(struct ralink_soc_info *soc_info)
530 +{
531 + void __iomem *sysc = (void __iomem *) KSEG1ADDR(RT3883_SYSC_BASE);
532 + const char *name;
533 + u32 n0;
534 + u32 n1;
535 + u32 id;
536 +
537 + n0 = __raw_readl(sysc + RT3883_SYSC_REG_CHIPID0_3);
538 + n1 = __raw_readl(sysc + RT3883_SYSC_REG_CHIPID4_7);
539 + id = __raw_readl(sysc + RT3883_SYSC_REG_REVID);
540 +
541 + if (n0 == RT3883_CHIP_NAME0 && n1 == RT3883_CHIP_NAME1) {
542 + soc_info->compatible = "ralink,rt3883-soc";
543 + name = "RT3883";
544 + } else {
545 + panic("rt3883: unknown SoC, n0:%08x n1:%08x", n0, n1);
546 + }
547 +
548 + snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN,
549 + "Ralink %s ver:%u eco:%u",
550 + name,
551 + (id >> RT3883_REVID_VER_ID_SHIFT) & RT3883_REVID_VER_ID_MASK,
552 + (id & RT3883_REVID_ECO_ID_MASK));
553 +}
OpenWrt Source Repository