1 From 27eef043b05fb8d9d3178fd3352c530f71901dd4 Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Thu, 23 May 2013 18:45:29 +0200
4 Subject: [PATCH 148/164] DMA: MIPS: ralink: add dmaengine driver
6 Signed-off-by: John Crispin <blogic@openwrt.org>
8 drivers/dma/Kconfig | 7 ++
9 drivers/dma/Makefile | 1 +
10 drivers/dma/ralink_gdma.c | 229 +++++++++++++++++++++++++++++++++++++++++++++
11 drivers/dma/ralink_gdma.h | 55 +++++++++++
12 4 files changed, 292 insertions(+)
13 create mode 100644 drivers/dma/ralink_gdma.c
14 create mode 100644 drivers/dma/ralink_gdma.h
16 diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
17 index aeaea32..751cdc4 100644
18 --- a/drivers/dma/Kconfig
19 +++ b/drivers/dma/Kconfig
20 @@ -322,6 +322,13 @@ config MMP_PDMA
22 Support the MMP PDMA engine for PXA and MMP platfrom.
25 + bool "Ralink Generic DMA support"
29 + Support the GDMA engine for MIPS based Ralink SoC.
34 diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile
35 index 488e3ff..f69e07e 100644
36 --- a/drivers/dma/Makefile
37 +++ b/drivers/dma/Makefile
38 @@ -37,3 +37,4 @@ obj-$(CONFIG_DMA_SA11X0) += sa11x0-dma.o
39 obj-$(CONFIG_MMP_TDMA) += mmp_tdma.o
40 obj-$(CONFIG_DMA_OMAP) += omap-dma.o
41 obj-$(CONFIG_MMP_PDMA) += mmp_pdma.o
42 +obj-$(CONFIG_RALINK_GDMA) += ralink_gdma.o
43 diff --git a/drivers/dma/ralink_gdma.c b/drivers/dma/ralink_gdma.c
45 index 0000000..be7c317
47 +++ b/drivers/dma/ralink_gdma.c
49 +#include <linux/init.h>
50 +#include <linux/module.h>
51 +#include <linux/slab.h>
52 +#include <linux/delay.h>
53 +#include <linux/dma-mapping.h>
54 +#include <linux/spinlock.h>
55 +#include <linux/interrupt.h>
56 +#include <linux/platform_device.h>
57 +#include <linux/of_platform.h>
58 +#include <linux/memory.h>
60 +#include "ralink_gdma.h"
62 +#define SURFBOARDINT_DMA 10
63 +#define MEMCPY_DMA_CH 8
64 +#define to_rt2880_dma_chan(chan) \
65 + container_of(chan, struct rt2880_dma_chan, common)
67 +static dma_cookie_t rt2880_dma_tx_submit(struct dma_async_tx_descriptor *tx)
69 + dma_cookie_t cookie;
71 + cookie = tx->chan->cookie;
76 +#define MIN_RTDMA_PKT_LEN 128
77 +static struct dma_async_tx_descriptor *
78 +rt2880_dma_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
79 + size_t len, unsigned long flags)
81 + struct rt2880_dma_chan *rt_chan = to_rt2880_dma_chan(chan);
82 + unsigned long mid_offset;
84 + spin_lock_bh(&rt_chan->lock);
86 + if(len < MIN_RTDMA_PKT_LEN) {
87 + memcpy(phys_to_virt(dest), phys_to_virt(src), len);
91 + /* Lower parts are transferred by GDMA.
92 + * Upper parts are transferred by CPU.
94 + RT_DMA_WRITE_REG(RT_DMA_SRC_REG(MEMCPY_DMA_CH), src);
95 + RT_DMA_WRITE_REG(RT_DMA_DST_REG(MEMCPY_DMA_CH), dest);
96 + RT_DMA_WRITE_REG(RT_DMA_CTRL_REG(MEMCPY_DMA_CH), (mid_offset << 16) | (3 << 3) | (3 << 0));
98 + memcpy(phys_to_virt(dest)+mid_offset, phys_to_virt(src)+mid_offset, len-mid_offset);
100 + dma_async_tx_descriptor_init(&rt_chan->txd, chan);
102 + while((RT_DMA_READ_REG(RT_DMA_DONEINT) & (0x1<<MEMCPY_DMA_CH))==0);
103 + RT_DMA_WRITE_REG(RT_DMA_DONEINT, (1<<MEMCPY_DMA_CH));
106 + spin_unlock_bh(&rt_chan->lock);
108 + return &rt_chan->txd;
112 + * rt2880_dma_status - poll the status of an XOR transaction
113 + * @chan: XOR channel handle
114 + * @cookie: XOR transaction identifier
115 + * @txstate: XOR transactions state holder (or NULL)
117 +static enum dma_status rt2880_dma_status(struct dma_chan *chan,
118 + dma_cookie_t cookie,
119 + struct dma_tx_state *txstate)
124 +static irqreturn_t rt2880_dma_interrupt_handler(int irq, void *data)
127 + printk("%s\n",__FUNCTION__);
129 + return IRQ_HANDLED;
132 +static void rt2880_dma_issue_pending(struct dma_chan *chan)
136 +static int rt2880_dma_alloc_chan_resources(struct dma_chan *chan)
138 +// printk("%s\n",__FUNCTION__);
143 +static void rt2880_dma_free_chan_resources(struct dma_chan *chan)
145 +// printk("%s\n",__FUNCTION__);
149 +static int rt2880_dma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd, unsigned long arg)
152 + case DMA_TERMINATE_ALL:
153 + printk("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
155 + case DMA_SLAVE_CONFIG:
156 + printk("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
165 +static int rt2880_dma_probe(struct platform_device *pdev)
167 + struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
168 + __iomem void *membase;
169 + struct dma_device *dma_dev;
170 + struct rt2880_dma_chan *rt_chan;
176 + membase = devm_request_and_ioremap(&pdev->dev, res);
177 + if (IS_ERR(membase))
178 + return PTR_ERR(membase);
180 + dma_dev = devm_kzalloc(&pdev->dev, sizeof(*dma_dev), GFP_KERNEL);
184 + irq = platform_get_irq(pdev, 0);
186 + dev_err(&pdev->dev, "failed to load irq\n");
191 + INIT_LIST_HEAD(&dma_dev->channels);
192 + dma_cap_zero(dma_dev->cap_mask);
193 + dma_cap_set(DMA_MEMCPY, dma_dev->cap_mask);
194 + dma_cap_set(DMA_SLAVE, dma_dev->cap_mask);
195 + dma_dev->device_alloc_chan_resources = rt2880_dma_alloc_chan_resources;
196 + dma_dev->device_free_chan_resources = rt2880_dma_free_chan_resources;
197 + dma_dev->device_tx_status = rt2880_dma_status;
198 + dma_dev->device_issue_pending = rt2880_dma_issue_pending;
199 + dma_dev->device_prep_dma_memcpy = rt2880_dma_prep_dma_memcpy;
200 + dma_dev->device_control = rt2880_dma_control;
201 + dma_dev->dev = &pdev->dev;
203 + rt_chan = devm_kzalloc(&pdev->dev, sizeof(*rt_chan), GFP_KERNEL);
208 + spin_lock_init(&rt_chan->lock);
209 + INIT_LIST_HEAD(&rt_chan->chain);
210 + INIT_LIST_HEAD(&rt_chan->completed_slots);
211 + INIT_LIST_HEAD(&rt_chan->all_slots);
212 + rt_chan->common.device = dma_dev;
213 + rt_chan->txd.tx_submit = rt2880_dma_tx_submit;
215 + list_add_tail(&rt_chan->common.device_node, &dma_dev->channels);
217 + err = dma_async_device_register(dma_dev);
219 + pr_err("ERR_MDMA:device_register failed: %d\n", err);
223 + ret = request_irq(irq, rt2880_dma_interrupt_handler, 0, dev_name(&pdev->dev), NULL);
225 + pr_err("IRQ %d is not free.\n", SURFBOARDINT_DMA);
229 + //set GDMA register in advance.
230 + reg = (32 << 16) | (32 << 8) | (MEMCPY_DMA_CH << 3);
231 + RT_DMA_WRITE_REG(RT_DMA_CTRL_REG1(MEMCPY_DMA_CH), reg);
233 + dev_info(&pdev->dev, "running\n");
238 +static int rt2880_dma_remove(struct platform_device *dev)
240 + struct dma_device *dma_dev = platform_get_drvdata(dev);
242 + printk("%s\n",__FUNCTION__);
244 + dma_async_device_unregister(dma_dev);
249 +static const struct of_device_id rt2880_dma_match[] = {
250 + { .compatible = "ralink,rt2880-gdma" },
253 +MODULE_DEVICE_TABLE(of, rt2880_wdt_match);
255 +static struct platform_driver rt2880_dma_driver = {
256 + .probe = rt2880_dma_probe,
257 + .remove = rt2880_dma_remove,
259 + .owner = THIS_MODULE,
260 + .name = RT_DMA_NAME,
261 + .of_match_table = rt2880_dma_match,
265 +static int __init rt2880_dma_init(void)
269 + rc = platform_driver_register(&rt2880_dma_driver);
272 +module_init(rt2880_dma_init);
274 +MODULE_AUTHOR("Steven Liu <steven_liu@mediatek.com>");
275 +MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
276 +MODULE_DESCRIPTION("DMA engine driver for Ralink DMA engine");
277 +MODULE_LICENSE("GPL");
278 diff --git a/drivers/dma/ralink_gdma.h b/drivers/dma/ralink_gdma.h
280 index 0000000..73e1948
282 +++ b/drivers/dma/ralink_gdma.h
285 + * Copyright (C) 2007, 2008, Marvell International Ltd.
287 + * This program is free software; you can redistribute it and/or modify
288 + * it under the terms and conditions of the GNU General Public License,
289 + * version 2, as published by the Free Software Foundation.
291 + * This program is distributed in the hope it will be useful, but WITHOUT
292 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
293 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
294 + * for more details.
296 + * You should have received a copy of the GNU General Public License
297 + * along with this program; if not, write to the Free Software Foundation,
298 + * Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
304 +#include <linux/types.h>
305 +#include <linux/io.h>
306 +#include <linux/dmaengine.h>
307 +#include <linux/interrupt.h>
309 +#define RT_DMA_NAME "rt2880_dma"
311 +#define RALINK_GDMA_BASE 0xB0002800
313 +struct rt2880_dma_chan {
315 + dma_cookie_t completed_cookie;
316 + spinlock_t lock; /* protects the descriptor slot pool */
317 + void __iomem *mmr_base;
319 + enum dma_transaction_type current_type;
320 + struct dma_async_tx_descriptor txd;
321 + struct list_head chain;
322 + struct list_head completed_slots;
323 + struct dma_chan common;
324 + struct list_head all_slots;
325 + int slots_allocated;
326 + struct tasklet_struct irq_tasklet;
329 +#define RT_DMA_READ_REG(addr) le32_to_cpu(*(volatile u32 *)(addr))
330 +#define RT_DMA_WRITE_REG(addr, val) *((volatile uint32_t *)(addr)) = cpu_to_le32(val)
332 +#define RT_DMA_SRC_REG(ch) (RALINK_GDMA_BASE + ch*16)
333 +#define RT_DMA_DST_REG(ch) (RT_DMA_SRC_REG(ch) + 4)
334 +#define RT_DMA_CTRL_REG(ch) (RT_DMA_DST_REG(ch) + 4)
335 +#define RT_DMA_CTRL_REG1(ch) (RT_DMA_CTRL_REG(ch) + 4)
336 +#define RT_DMA_DONEINT (RALINK_GDMA_BASE + 0x204)