1 From 69fdd2c4f937796b934e89c33acde9d082e27bfd Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Mon, 4 Aug 2014 20:36:29 +0200
4 Subject: [PATCH 27/53] GPIO: MIPS: ralink: add gpio driver for ralink SoC
6 Add gpio driver for Ralink SoC. This driver makes the gpio core on
7 RT2880, RT305x, rt3352, rt3662, rt3883, rt5350 and mt7620 work.
9 Signed-off-by: John Crispin <blogic@openwrt.org>
10 Cc: linux-mips@linux-mips.org
11 Cc: linux-gpio@vger.kernel.org
13 arch/mips/include/asm/mach-ralink/gpio.h | 24 ++
14 drivers/gpio/Kconfig | 6 +
15 drivers/gpio/Makefile | 1 +
16 drivers/gpio/gpio-ralink.c | 355 ++++++++++++++++++++++++++++++
17 4 files changed, 386 insertions(+)
18 create mode 100644 arch/mips/include/asm/mach-ralink/gpio.h
19 create mode 100644 drivers/gpio/gpio-ralink.c
22 +++ b/arch/mips/include/asm/mach-ralink/gpio.h
25 + * Ralink SoC GPIO API support
27 + * Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
28 + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
30 + * This program is free software; you can redistribute it and/or modify it
31 + * under the terms of the GNU General Public License version 2 as published
32 + * by the Free Software Foundation.
36 +#ifndef __ASM_MACH_RALINK_GPIO_H
37 +#define __ASM_MACH_RALINK_GPIO_H
39 +#define ARCH_NR_GPIOS 128
40 +#include <asm-generic/gpio.h>
42 +#define gpio_get_value __gpio_get_value
43 +#define gpio_set_value __gpio_set_value
44 +#define gpio_cansleep __gpio_cansleep
45 +#define gpio_to_irq __gpio_to_irq
47 +#endif /* __ASM_MACH_RALINK_GPIO_H */
48 --- a/drivers/gpio/Kconfig
49 +++ b/drivers/gpio/Kconfig
50 @@ -398,6 +398,12 @@ config GPIO_REG
51 A 32-bit single register GPIO fixed in/out implementation. This
52 can be used to represent any register as a set of GPIO signals.
55 + bool "Ralink GPIO Support"
58 + Say yes here to support the Ralink SoC GPIO device
60 config GPIO_SPEAR_SPICS
61 bool "ST SPEAr13xx SPI Chip Select as GPIO support"
63 --- a/drivers/gpio/Makefile
64 +++ b/drivers/gpio/Makefile
65 @@ -98,6 +98,7 @@ obj-$(CONFIG_GPIO_PCI_IDIO_16) += gpio-p
66 obj-$(CONFIG_GPIO_PISOSR) += gpio-pisosr.o
67 obj-$(CONFIG_GPIO_PL061) += gpio-pl061.o
68 obj-$(CONFIG_GPIO_PXA) += gpio-pxa.o
69 +obj-$(CONFIG_GPIO_RALINK) += gpio-ralink.o
70 obj-$(CONFIG_GPIO_RC5T583) += gpio-rc5t583.o
71 obj-$(CONFIG_GPIO_RDC321X) += gpio-rdc321x.o
72 obj-$(CONFIG_GPIO_RCAR) += gpio-rcar.o
74 +++ b/drivers/gpio/gpio-ralink.c
77 + * This program is free software; you can redistribute it and/or modify it
78 + * under the terms of the GNU General Public License version 2 as published
79 + * by the Free Software Foundation.
81 + * Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
82 + * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
85 +#include <linux/module.h>
86 +#include <linux/io.h>
87 +#include <linux/gpio.h>
88 +#include <linux/spinlock.h>
89 +#include <linux/platform_device.h>
90 +#include <linux/of_irq.h>
91 +#include <linux/irqdomain.h>
92 +#include <linux/interrupt.h>
94 +enum ralink_gpio_reg {
108 +struct ralink_gpio_chip {
109 + struct gpio_chip chip;
110 + u8 regs[GPIO_REG_MAX];
113 + void __iomem *membase;
114 + struct irq_domain *domain;
122 +static struct irq_domain *irq_map[MAP_MAX];
123 +static int irq_map_count;
124 +static atomic_t irq_refcount = ATOMIC_INIT(0);
126 +static inline struct ralink_gpio_chip *to_ralink_gpio(struct gpio_chip *chip)
128 + struct ralink_gpio_chip *rg;
130 + rg = container_of(chip, struct ralink_gpio_chip, chip);
135 +static inline void rt_gpio_w32(struct ralink_gpio_chip *rg, u8 reg, u32 val)
137 + iowrite32(val, rg->membase + rg->regs[reg]);
140 +static inline u32 rt_gpio_r32(struct ralink_gpio_chip *rg, u8 reg)
142 + return ioread32(rg->membase + rg->regs[reg]);
145 +static void ralink_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
147 + struct ralink_gpio_chip *rg = to_ralink_gpio(chip);
149 + rt_gpio_w32(rg, (value) ? GPIO_REG_SET : GPIO_REG_RESET, BIT(offset));
152 +static int ralink_gpio_get(struct gpio_chip *chip, unsigned offset)
154 + struct ralink_gpio_chip *rg = to_ralink_gpio(chip);
156 + return !!(rt_gpio_r32(rg, GPIO_REG_DATA) & BIT(offset));
159 +static int ralink_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
161 + struct ralink_gpio_chip *rg = to_ralink_gpio(chip);
162 + unsigned long flags;
165 + spin_lock_irqsave(&rg->lock, flags);
166 + t = rt_gpio_r32(rg, GPIO_REG_DIR);
168 + rt_gpio_w32(rg, GPIO_REG_DIR, t);
169 + spin_unlock_irqrestore(&rg->lock, flags);
174 +static int ralink_gpio_direction_output(struct gpio_chip *chip,
175 + unsigned offset, int value)
177 + struct ralink_gpio_chip *rg = to_ralink_gpio(chip);
178 + unsigned long flags;
181 + spin_lock_irqsave(&rg->lock, flags);
182 + ralink_gpio_set(chip, offset, value);
183 + t = rt_gpio_r32(rg, GPIO_REG_DIR);
185 + rt_gpio_w32(rg, GPIO_REG_DIR, t);
186 + spin_unlock_irqrestore(&rg->lock, flags);
191 +static int ralink_gpio_to_irq(struct gpio_chip *chip, unsigned pin)
193 + struct ralink_gpio_chip *rg = to_ralink_gpio(chip);
198 + return irq_create_mapping(rg->domain, pin);
201 +static void ralink_gpio_irq_handler(struct irq_desc *desc)
205 + for (i = 0; i < irq_map_count; i++) {
206 + struct irq_domain *domain = irq_map[i];
207 + struct ralink_gpio_chip *rg;
208 + unsigned long pending;
211 + rg = (struct ralink_gpio_chip *) domain->host_data;
212 + pending = rt_gpio_r32(rg, GPIO_REG_INT);
214 + for_each_set_bit(bit, &pending, rg->chip.ngpio) {
215 + u32 map = irq_find_mapping(domain, bit);
216 + generic_handle_irq(map);
217 + rt_gpio_w32(rg, GPIO_REG_INT, BIT(bit));
222 +static void ralink_gpio_irq_unmask(struct irq_data *d)
224 + struct ralink_gpio_chip *rg;
225 + unsigned long flags;
228 + rg = (struct ralink_gpio_chip *) d->domain->host_data;
229 + rise = rt_gpio_r32(rg, GPIO_REG_RENA);
230 + fall = rt_gpio_r32(rg, GPIO_REG_FENA);
232 + spin_lock_irqsave(&rg->lock, flags);
233 + rt_gpio_w32(rg, GPIO_REG_RENA, rise | (BIT(d->hwirq) & rg->rising));
234 + rt_gpio_w32(rg, GPIO_REG_FENA, fall | (BIT(d->hwirq) & rg->falling));
235 + spin_unlock_irqrestore(&rg->lock, flags);
238 +static void ralink_gpio_irq_mask(struct irq_data *d)
240 + struct ralink_gpio_chip *rg;
241 + unsigned long flags;
244 + rg = (struct ralink_gpio_chip *) d->domain->host_data;
245 + rise = rt_gpio_r32(rg, GPIO_REG_RENA);
246 + fall = rt_gpio_r32(rg, GPIO_REG_FENA);
248 + spin_lock_irqsave(&rg->lock, flags);
249 + rt_gpio_w32(rg, GPIO_REG_FENA, fall & ~BIT(d->hwirq));
250 + rt_gpio_w32(rg, GPIO_REG_RENA, rise & ~BIT(d->hwirq));
251 + spin_unlock_irqrestore(&rg->lock, flags);
254 +static int ralink_gpio_irq_type(struct irq_data *d, unsigned int type)
256 + struct ralink_gpio_chip *rg;
257 + u32 mask = BIT(d->hwirq);
259 + rg = (struct ralink_gpio_chip *) d->domain->host_data;
261 + if (type == IRQ_TYPE_PROBE) {
262 + if ((rg->rising | rg->falling) & mask)
265 + type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
268 + if (type & IRQ_TYPE_EDGE_RISING)
269 + rg->rising |= mask;
271 + rg->rising &= ~mask;
273 + if (type & IRQ_TYPE_EDGE_FALLING)
274 + rg->falling |= mask;
276 + rg->falling &= ~mask;
281 +static struct irq_chip ralink_gpio_irq_chip = {
283 + .irq_unmask = ralink_gpio_irq_unmask,
284 + .irq_mask = ralink_gpio_irq_mask,
285 + .irq_mask_ack = ralink_gpio_irq_mask,
286 + .irq_set_type = ralink_gpio_irq_type,
289 +static int gpio_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
291 + irq_set_chip_and_handler(irq, &ralink_gpio_irq_chip, handle_level_irq);
292 + irq_set_handler_data(irq, d);
297 +static const struct irq_domain_ops irq_domain_ops = {
298 + .xlate = irq_domain_xlate_onecell,
302 +static void ralink_gpio_irq_init(struct device_node *np,
303 + struct ralink_gpio_chip *rg)
305 + if (irq_map_count >= MAP_MAX)
308 + rg->irq = irq_of_parse_and_map(np, 0);
312 + rg->domain = irq_domain_add_linear(np, rg->chip.ngpio,
313 + &irq_domain_ops, rg);
315 + dev_err(rg->chip.parent, "irq_domain_add_linear failed\n");
319 + irq_map[irq_map_count++] = rg->domain;
321 + rt_gpio_w32(rg, GPIO_REG_RENA, 0x0);
322 + rt_gpio_w32(rg, GPIO_REG_FENA, 0x0);
324 + if (!atomic_read(&irq_refcount))
325 + irq_set_chained_handler(rg->irq, ralink_gpio_irq_handler);
326 + atomic_inc(&irq_refcount);
328 + dev_info(rg->chip.parent, "registering %d irq handlers\n", rg->chip.ngpio);
331 +static int ralink_gpio_request(struct gpio_chip *chip, unsigned offset)
333 + int gpio = chip->base + offset;
335 + return pinctrl_request_gpio(gpio);
338 +static void ralink_gpio_free(struct gpio_chip *chip, unsigned offset)
340 + int gpio = chip->base + offset;
342 + pinctrl_free_gpio(gpio);
345 +static int ralink_gpio_probe(struct platform_device *pdev)
347 + struct device_node *np = pdev->dev.of_node;
348 + struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
349 + struct ralink_gpio_chip *rg;
350 + const __be32 *ngpio, *gpiobase;
353 + dev_err(&pdev->dev, "failed to find resource\n");
357 + rg = devm_kzalloc(&pdev->dev,
358 + sizeof(struct ralink_gpio_chip), GFP_KERNEL);
362 + rg->membase = devm_ioremap_resource(&pdev->dev, res);
363 + if (!rg->membase) {
364 + dev_err(&pdev->dev, "cannot remap I/O memory region\n");
368 + if (of_property_read_u8_array(np, "ralink,register-map",
369 + rg->regs, GPIO_REG_MAX)) {
370 + dev_err(&pdev->dev, "failed to read register definition\n");
374 + ngpio = of_get_property(np, "ralink,nr-gpio", NULL);
376 + dev_err(&pdev->dev, "failed to read number of pins\n");
380 + gpiobase = of_get_property(np, "ralink,gpio-base", NULL);
382 + rg->chip.base = be32_to_cpu(*gpiobase);
384 + rg->chip.base = -1;
386 + spin_lock_init(&rg->lock);
388 + rg->chip.parent = &pdev->dev;
389 + rg->chip.label = dev_name(&pdev->dev);
390 + rg->chip.of_node = np;
391 + rg->chip.ngpio = be32_to_cpu(*ngpio);
392 + rg->chip.direction_input = ralink_gpio_direction_input;
393 + rg->chip.direction_output = ralink_gpio_direction_output;
394 + rg->chip.get = ralink_gpio_get;
395 + rg->chip.set = ralink_gpio_set;
396 + rg->chip.request = ralink_gpio_request;
397 + rg->chip.to_irq = ralink_gpio_to_irq;
398 + rg->chip.free = ralink_gpio_free;
400 + /* set polarity to low for all lines */
401 + rt_gpio_w32(rg, GPIO_REG_POL, 0);
403 + dev_info(&pdev->dev, "registering %d gpios\n", rg->chip.ngpio);
405 + ralink_gpio_irq_init(np, rg);
407 + return gpiochip_add(&rg->chip);
410 +static const struct of_device_id ralink_gpio_match[] = {
411 + { .compatible = "ralink,rt2880-gpio" },
414 +MODULE_DEVICE_TABLE(of, ralink_gpio_match);
416 +static struct platform_driver ralink_gpio_driver = {
417 + .probe = ralink_gpio_probe,
419 + .name = "rt2880_gpio",
420 + .owner = THIS_MODULE,
421 + .of_match_table = ralink_gpio_match,
425 +static int __init ralink_gpio_init(void)
427 + return platform_driver_register(&ralink_gpio_driver);
430 +subsys_initcall(ralink_gpio_init);