1 From 87a5fcd57c577cd94b5b080deb98885077c13a42 Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Sun, 27 Jul 2014 09:49:07 +0100
4 Subject: [PATCH 43/53] spi: add mt7621 support
6 Signed-off-by: John Crispin <blogic@openwrt.org>
8 drivers/spi/Kconfig | 6 +
9 drivers/spi/Makefile | 1 +
10 drivers/spi/spi-mt7621.c | 480 ++++++++++++++++++++++++++++++++++++++++++++++
11 3 files changed, 487 insertions(+)
12 create mode 100644 drivers/spi/spi-mt7621.c
14 --- a/drivers/spi/Kconfig
15 +++ b/drivers/spi/Kconfig
16 @@ -569,6 +569,12 @@ config SPI_RT2880
18 This selects a driver for the Ralink RT288x/RT305x SPI Controller.
21 + tristate "MediaTek MT7621 SPI Controller"
24 + This selects a driver for the MediaTek MT7621 SPI Controller.
27 tristate "Samsung S3C24XX series SPI"
28 depends on ARCH_S3C24XX
29 --- a/drivers/spi/Makefile
30 +++ b/drivers/spi/Makefile
31 @@ -60,6 +60,7 @@ obj-$(CONFIG_SPI_MPC512x_PSC) += spi-mp
32 obj-$(CONFIG_SPI_MPC52xx_PSC) += spi-mpc52xx-psc.o
33 obj-$(CONFIG_SPI_MPC52xx) += spi-mpc52xx.o
34 obj-$(CONFIG_SPI_MT65XX) += spi-mt65xx.o
35 +obj-$(CONFIG_SPI_MT7621) += spi-mt7621.o
36 obj-$(CONFIG_SPI_MXS) += spi-mxs.o
37 obj-$(CONFIG_SPI_NUC900) += spi-nuc900.o
38 obj-$(CONFIG_SPI_OC_TINY) += spi-oc-tiny.o
40 +++ b/drivers/spi/spi-mt7621.c
43 + * spi-mt7621.c -- MediaTek MT7621 SPI controller driver
45 + * Copyright (C) 2011 Sergiy <piratfm@gmail.com>
46 + * Copyright (C) 2011-2013 Gabor Juhos <juhosg@openwrt.org>
47 + * Copyright (C) 2014-2015 Felix Fietkau <nbd@nbd.name>
49 + * Some parts are based on spi-orion.c:
50 + * Author: Shadi Ammouri <shadi@marvell.com>
51 + * Copyright (C) 2007-2008 Marvell Ltd.
53 + * This program is free software; you can redistribute it and/or modify
54 + * it under the terms of the GNU General Public License version 2 as
55 + * published by the Free Software Foundation.
58 +#include <linux/init.h>
59 +#include <linux/module.h>
60 +#include <linux/clk.h>
61 +#include <linux/err.h>
62 +#include <linux/delay.h>
63 +#include <linux/io.h>
64 +#include <linux/reset.h>
65 +#include <linux/spi/spi.h>
66 +#include <linux/of_device.h>
67 +#include <linux/platform_device.h>
68 +#include <linux/swab.h>
70 +#include <ralink_regs.h>
72 +#define SPI_BPW_MASK(bits) BIT((bits) - 1)
74 +#define DRIVER_NAME "spi-mt7621"
76 +#define RALINK_SPI_WAIT_MAX_LOOP 2000
78 +/* SPISTAT register bit field */
79 +#define SPISTAT_BUSY BIT(0)
81 +#define MT7621_SPI_TRANS 0x00
82 +#define SPITRANS_BUSY BIT(16)
84 +#define MT7621_SPI_OPCODE 0x04
85 +#define MT7621_SPI_DATA0 0x08
86 +#define MT7621_SPI_DATA4 0x18
87 +#define SPI_CTL_TX_RX_CNT_MASK 0xff
88 +#define SPI_CTL_START BIT(8)
90 +#define MT7621_SPI_POLAR 0x38
91 +#define MT7621_SPI_MASTER 0x28
92 +#define MT7621_SPI_MOREBUF 0x2c
93 +#define MT7621_SPI_SPACE 0x3c
95 +#define MT7621_CPHA BIT(5)
96 +#define MT7621_CPOL BIT(4)
97 +#define MT7621_LSB_FIRST BIT(3)
99 +#define RT2880_SPI_MODE_BITS (SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST | SPI_CS_HIGH)
104 + struct spi_master *master;
105 + void __iomem *base;
106 + unsigned int sys_freq;
107 + unsigned int speed;
111 + struct mt7621_spi_ops *ops;
114 +static inline struct mt7621_spi *spidev_to_mt7621_spi(struct spi_device *spi)
116 + return spi_master_get_devdata(spi->master);
119 +static inline u32 mt7621_spi_read(struct mt7621_spi *rs, u32 reg)
121 + return ioread32(rs->base + reg);
124 +static inline void mt7621_spi_write(struct mt7621_spi *rs, u32 reg, u32 val)
126 + iowrite32(val, rs->base + reg);
129 +static void mt7621_spi_reset(struct mt7621_spi *rs, int duplex)
131 + u32 master = mt7621_spi_read(rs, MT7621_SPI_MASTER);
138 + master &= ~(1 << 10);
140 + mt7621_spi_write(rs, MT7621_SPI_MASTER, master);
143 +static void mt7621_spi_set_cs(struct spi_device *spi, int enable)
145 + struct mt7621_spi *rs = spidev_to_mt7621_spi(spi);
146 + int cs = spi->chip_select;
149 + mt7621_spi_reset(rs, cs);
152 + mt7621_spi_write(rs, MT7621_SPI_POLAR, polar);
155 +static int mt7621_spi_prepare(struct spi_device *spi, unsigned int speed)
157 + struct mt7621_spi *rs = spidev_to_mt7621_spi(spi);
161 + dev_dbg(&spi->dev, "speed:%u\n", speed);
163 + rate = DIV_ROUND_UP(rs->sys_freq, speed);
164 + dev_dbg(&spi->dev, "rate-1:%u\n", rate);
172 + reg = mt7621_spi_read(rs, MT7621_SPI_MASTER);
173 + reg &= ~(0xfff << 16);
174 + reg |= (rate - 2) << 16;
177 + reg &= ~MT7621_LSB_FIRST;
178 + if (spi->mode & SPI_LSB_FIRST)
179 + reg |= MT7621_LSB_FIRST;
181 + reg &= ~(MT7621_CPHA | MT7621_CPOL);
182 + switch(spi->mode & (SPI_CPOL | SPI_CPHA)) {
186 + reg |= MT7621_CPHA;
189 + reg |= MT7621_CPOL;
192 + reg |= MT7621_CPOL | MT7621_CPHA;
195 + mt7621_spi_write(rs, MT7621_SPI_MASTER, reg);
200 +static inline int mt7621_spi_wait_till_ready(struct spi_device *spi)
202 + struct mt7621_spi *rs = spidev_to_mt7621_spi(spi);
205 + for (i = 0; i < RALINK_SPI_WAIT_MAX_LOOP; i++) {
208 + status = mt7621_spi_read(rs, MT7621_SPI_TRANS);
209 + if ((status & SPITRANS_BUSY) == 0) {
219 +static int mt7621_spi_transfer_half_duplex(struct spi_master *master,
220 + struct spi_message *m)
222 + struct mt7621_spi *rs = spi_master_get_devdata(master);
223 + struct spi_device *spi = m->spi;
224 + unsigned int speed = spi->max_speed_hz;
225 + struct spi_transfer *t = NULL;
229 + u32 data[9] = { 0 };
232 + mt7621_spi_wait_till_ready(spi);
234 + list_for_each_entry(t, &m->transfers, transfer_list) {
235 + const u8 *buf = t->tx_buf;
243 + if (t->speed_hz < speed)
244 + speed = t->speed_hz;
247 + * m25p80 might attempt to write more data than we can handle.
248 + * truncate the message to what we can fit into the registers
250 + if (len + t->len > 36)
253 + for (i = 0; i < t->len; i++, len++)
254 + data[len / 4] |= buf[i] << (8 * (len & 3));
257 + if (WARN_ON(rx_len > 32)) {
262 + if (mt7621_spi_prepare(spi, speed)) {
266 + data[0] = swab32(data[0]);
268 + data[0] >>= (4 - len) * 8;
270 + for (i = 0; i < len; i += 4)
271 + mt7621_spi_write(rs, MT7621_SPI_OPCODE + i, data[i / 4]);
273 + val = (min_t(int, len, 4) * 8) << 24;
275 + val |= (len - 4) * 8;
276 + val |= (rx_len * 8) << 12;
277 + mt7621_spi_write(rs, MT7621_SPI_MOREBUF, val);
279 + mt7621_spi_set_cs(spi, 1);
281 + val = mt7621_spi_read(rs, MT7621_SPI_TRANS);
282 + val |= SPI_CTL_START;
283 + mt7621_spi_write(rs, MT7621_SPI_TRANS, val);
285 + mt7621_spi_wait_till_ready(spi);
287 + mt7621_spi_set_cs(spi, 0);
289 + for (i = 0; i < rx_len; i += 4)
290 + data[i / 4] = mt7621_spi_read(rs, MT7621_SPI_DATA0 + i);
292 + m->actual_length = len + rx_len;
295 + list_for_each_entry(t, &m->transfers, transfer_list) {
296 + u8 *buf = t->rx_buf;
301 + for (i = 0; i < t->len; i++, len++)
302 + buf[i] = data[len / 4] >> (8 * (len & 3));
306 + m->status = status;
307 + spi_finalize_current_message(master);
312 +static int mt7621_spi_transfer_full_duplex(struct spi_master *master,
313 + struct spi_message *m)
315 + struct mt7621_spi *rs = spi_master_get_devdata(master);
316 + struct spi_device *spi = m->spi;
317 + unsigned int speed = spi->max_speed_hz;
318 + struct spi_transfer *t = NULL;
322 + u32 data[9] = { 0 };
325 + mt7621_spi_wait_till_ready(spi);
327 + list_for_each_entry(t, &m->transfers, transfer_list) {
328 + const u8 *buf = t->tx_buf;
336 + if (WARN_ON(len + t->len > 16)) {
341 + for (i = 0; i < t->len; i++, len++)
342 + data[len / 4] |= buf[i] << (8 * (len & 3));
343 + if (speed > t->speed_hz)
344 + speed = t->speed_hz;
347 + if (WARN_ON(rx_len > 16)) {
352 + if (mt7621_spi_prepare(spi, speed)) {
357 + for (i = 0; i < len; i += 4)
358 + mt7621_spi_write(rs, MT7621_SPI_DATA0 + i, data[i / 4]);
361 + val |= (rx_len * 8) << 12;
362 + mt7621_spi_write(rs, MT7621_SPI_MOREBUF, val);
364 + mt7621_spi_set_cs(spi, 1);
366 + val = mt7621_spi_read(rs, MT7621_SPI_TRANS);
367 + val |= SPI_CTL_START;
368 + mt7621_spi_write(rs, MT7621_SPI_TRANS, val);
370 + mt7621_spi_wait_till_ready(spi);
372 + mt7621_spi_set_cs(spi, 0);
374 + for (i = 0; i < rx_len; i += 4)
375 + data[i / 4] = mt7621_spi_read(rs, MT7621_SPI_DATA4 + i);
377 + m->actual_length = rx_len;
380 + list_for_each_entry(t, &m->transfers, transfer_list) {
381 + u8 *buf = t->rx_buf;
386 + for (i = 0; i < t->len; i++, len++)
387 + buf[i] = data[len / 4] >> (8 * (len & 3));
391 + m->status = status;
392 + spi_finalize_current_message(master);
397 +static int mt7621_spi_transfer_one_message(struct spi_master *master,
398 + struct spi_message *m)
400 + struct spi_device *spi = m->spi;
401 + int cs = spi->chip_select;
404 + return mt7621_spi_transfer_full_duplex(master, m);
405 + return mt7621_spi_transfer_half_duplex(master, m);
408 +static int mt7621_spi_setup(struct spi_device *spi)
410 + struct mt7621_spi *rs = spidev_to_mt7621_spi(spi);
412 + if ((spi->max_speed_hz == 0) ||
413 + (spi->max_speed_hz > (rs->sys_freq / 2)))
414 + spi->max_speed_hz = (rs->sys_freq / 2);
416 + if (spi->max_speed_hz < (rs->sys_freq / 4097)) {
417 + dev_err(&spi->dev, "setup: requested speed is too low %d Hz\n",
418 + spi->max_speed_hz);
425 +static const struct of_device_id mt7621_spi_match[] = {
426 + { .compatible = "ralink,mt7621-spi" },
429 +MODULE_DEVICE_TABLE(of, mt7621_spi_match);
431 +static size_t mt7621_max_transfer_size(struct spi_device *spi)
436 +static int mt7621_spi_probe(struct platform_device *pdev)
438 + const struct of_device_id *match;
439 + struct spi_master *master;
440 + struct mt7621_spi *rs;
441 + unsigned long flags;
442 + void __iomem *base;
443 + struct resource *r;
446 + struct mt7621_spi_ops *ops;
448 + match = of_match_device(mt7621_spi_match, &pdev->dev);
451 + ops = (struct mt7621_spi_ops *)match->data;
453 + r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
454 + base = devm_ioremap_resource(&pdev->dev, r);
456 + return PTR_ERR(base);
458 + clk = devm_clk_get(&pdev->dev, NULL);
460 + dev_err(&pdev->dev, "unable to get SYS clock, err=%d\n",
462 + return PTR_ERR(clk);
465 + status = clk_prepare_enable(clk);
469 + master = spi_alloc_master(&pdev->dev, sizeof(*rs));
470 + if (master == NULL) {
471 + dev_info(&pdev->dev, "master allocation failed\n");
475 + master->mode_bits = RT2880_SPI_MODE_BITS;
477 + master->setup = mt7621_spi_setup;
478 + master->transfer_one_message = mt7621_spi_transfer_one_message;
479 + master->bits_per_word_mask = SPI_BPW_MASK(8);
480 + master->dev.of_node = pdev->dev.of_node;
481 + master->num_chipselect = 2;
482 + master->max_transfer_size = mt7621_max_transfer_size;
484 + dev_set_drvdata(&pdev->dev, master);
486 + rs = spi_master_get_devdata(master);
489 + rs->master = master;
490 + rs->sys_freq = clk_get_rate(rs->clk);
492 + dev_info(&pdev->dev, "sys_freq: %u\n", rs->sys_freq);
493 + spin_lock_irqsave(&rs->lock, flags);
495 + device_reset(&pdev->dev);
497 + mt7621_spi_reset(rs, 0);
499 + return spi_register_master(master);
502 +static int mt7621_spi_remove(struct platform_device *pdev)
504 + struct spi_master *master;
505 + struct mt7621_spi *rs;
507 + master = dev_get_drvdata(&pdev->dev);
508 + rs = spi_master_get_devdata(master);
510 + clk_disable(rs->clk);
511 + spi_unregister_master(master);
516 +MODULE_ALIAS("platform:" DRIVER_NAME);
518 +static struct platform_driver mt7621_spi_driver = {
520 + .name = DRIVER_NAME,
521 + .owner = THIS_MODULE,
522 + .of_match_table = mt7621_spi_match,
524 + .probe = mt7621_spi_probe,
525 + .remove = mt7621_spi_remove,
528 +module_platform_driver(mt7621_spi_driver);
530 +MODULE_DESCRIPTION("MT7621 SPI driver");
531 +MODULE_AUTHOR("Felix Fietkau <nbd@nbd.name>");
532 +MODULE_LICENSE("GPL");