target/linux/ramips/patches-4.3/0027-GPIO-MIPS-ralink-add-gpio-driver-for-ralink-SoC.patch

   1 From 69fdd2c4f937796b934e89c33acde9d082e27bfd Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Mon, 4 Aug 2014 20:36:29 +0200
   4 Subject: [PATCH 27/53] GPIO: MIPS: ralink: add gpio driver for ralink SoC
   5
   6 Add gpio driver for Ralink SoC. This driver makes the gpio core on
   7 RT2880, RT305x, rt3352, rt3662, rt3883, rt5350 and mt7620 work.
   8
   9 Signed-off-by: John Crispin <blogic@openwrt.org>
  10 Cc: linux-mips@linux-mips.org
  11 Cc: linux-gpio@vger.kernel.org
  12 ---
  13  arch/mips/include/asm/mach-ralink/gpio.h |   24 ++
  14  drivers/gpio/Kconfig                     |    6 +
  15  drivers/gpio/Makefile                    |    1 +
  16  drivers/gpio/gpio-ralink.c               |  355 ++++++++++++++++++++++++++++++
  17  4 files changed, 386 insertions(+)
  18  create mode 100644 arch/mips/include/asm/mach-ralink/gpio.h
  19  create mode 100644 drivers/gpio/gpio-ralink.c
  20
  21 diff --git a/arch/mips/include/asm/mach-ralink/gpio.h b/arch/mips/include/asm/mach-ralink/gpio.h
  22 new file mode 100644
  23 index 0000000..f68ee16
  24 --- /dev/null
  25 +++ b/arch/mips/include/asm/mach-ralink/gpio.h
  26 @@ -0,0 +1,24 @@
  27 +/*
  28 + *  Ralink SoC GPIO API support
  29 + *
  30 + *  Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
  31 + *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
  32 + *
  33 + *  This program is free software; you can redistribute it and/or modify it
  34 + *  under the terms of the GNU General Public License version 2 as published
  35 + *  by the Free Software Foundation.
  36 + *
  37 + */
  38 +
  39 +#ifndef __ASM_MACH_RALINK_GPIO_H
  40 +#define __ASM_MACH_RALINK_GPIO_H
  41 +
  42 +#define ARCH_NR_GPIOS  128
  43 +#include <asm-generic/gpio.h>
  44 +
  45 +#define gpio_get_value __gpio_get_value
  46 +#define gpio_set_value __gpio_set_value
  47 +#define gpio_cansleep  __gpio_cansleep
  48 +#define gpio_to_irq    __gpio_to_irq
  49 +
  50 +#endif /* __ASM_MACH_RALINK_GPIO_H */
  51 diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
  52 index 8949b3f..4a3e7df 100644
  53 --- a/drivers/gpio/Kconfig
  54 +++ b/drivers/gpio/Kconfig
  55 @@ -404,6 +404,12 @@ config GPIO_SCH311X
  56           To compile this driver as a module, choose M here: the module will
  57           be called gpio-sch311x.
  58
  59 +config GPIO_RALINK
  60 +       bool "Ralink GPIO Support"
  61 +       depends on RALINK
  62 +       help
  63 +         Say yes here to support the Ralink SoC GPIO device
  64 +
  65  config GPIO_SPEAR_SPICS
  66         bool "ST SPEAr13xx SPI Chip Select as GPIO support"
  67         depends on PLAT_SPEAR
  68 diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
  69 index f79a7c4..13448d78 100644
  70 --- a/drivers/gpio/Makefile
  71 +++ b/drivers/gpio/Makefile
  72 @@ -75,6 +75,7 @@ obj-$(CONFIG_GPIO_PCF857X)    += gpio-pcf857x.o
  73  obj-$(CONFIG_GPIO_PCH)         += gpio-pch.o
  74  obj-$(CONFIG_GPIO_PL061)       += gpio-pl061.o
  75  obj-$(CONFIG_GPIO_PXA)         += gpio-pxa.o
  76 +obj-$(CONFIG_GPIO_RALINK)      += gpio-ralink.o
  77  obj-$(CONFIG_GPIO_RC5T583)     += gpio-rc5t583.o
  78  obj-$(CONFIG_GPIO_RDC321X)     += gpio-rdc321x.o
  79  obj-$(CONFIG_GPIO_RCAR)                += gpio-rcar.o
  80 diff --git a/drivers/gpio/gpio-ralink.c b/drivers/gpio/gpio-ralink.c
  81 new file mode 100644
  82 index 0000000..2be9b8a
  83 --- /dev/null
  84 +++ b/drivers/gpio/gpio-ralink.c
  85 @@ -0,0 +1,355 @@
  86 +/*
  87 + * This program is free software; you can redistribute it and/or modify it
  88 + * under the terms of the GNU General Public License version 2 as published
  89 + * by the Free Software Foundation.
  90 + *
  91 + * Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
  92 + * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
  93 + */
  94 +
  95 +#include <linux/module.h>
  96 +#include <linux/io.h>
  97 +#include <linux/gpio.h>
  98 +#include <linux/spinlock.h>
  99 +#include <linux/platform_device.h>
 100 +#include <linux/of_irq.h>
 101 +#include <linux/irqdomain.h>
 102 +#include <linux/interrupt.h>
 103 +
 104 +enum ralink_gpio_reg {
 105 +       GPIO_REG_INT = 0,
 106 +       GPIO_REG_EDGE,
 107 +       GPIO_REG_RENA,
 108 +       GPIO_REG_FENA,
 109 +       GPIO_REG_DATA,
 110 +       GPIO_REG_DIR,
 111 +       GPIO_REG_POL,
 112 +       GPIO_REG_SET,
 113 +       GPIO_REG_RESET,
 114 +       GPIO_REG_TOGGLE,
 115 +       GPIO_REG_MAX
 116 +};
 117 +
 118 +struct ralink_gpio_chip {
 119 +       struct gpio_chip chip;
 120 +       u8 regs[GPIO_REG_MAX];
 121 +
 122 +       spinlock_t lock;
 123 +       void __iomem *membase;
 124 +       struct irq_domain *domain;
 125 +       int irq;
 126 +
 127 +       u32 rising;
 128 +       u32 falling;
 129 +};
 130 +
 131 +#define MAP_MAX        4
 132 +static struct irq_domain *irq_map[MAP_MAX];
 133 +static int irq_map_count;
 134 +static atomic_t irq_refcount = ATOMIC_INIT(0);
 135 +
 136 +static inline struct ralink_gpio_chip *to_ralink_gpio(struct gpio_chip *chip)
 137 +{
 138 +       struct ralink_gpio_chip *rg;
 139 +
 140 +       rg = container_of(chip, struct ralink_gpio_chip, chip);
 141 +
 142 +       return rg;
 143 +}
 144 +
 145 +static inline void rt_gpio_w32(struct ralink_gpio_chip *rg, u8 reg, u32 val)
 146 +{
 147 +       iowrite32(val, rg->membase + rg->regs[reg]);
 148 +}
 149 +
 150 +static inline u32 rt_gpio_r32(struct ralink_gpio_chip *rg, u8 reg)
 151 +{
 152 +       return ioread32(rg->membase + rg->regs[reg]);
 153 +}
 154 +
 155 +static void ralink_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
 156 +{
 157 +       struct ralink_gpio_chip *rg = to_ralink_gpio(chip);
 158 +
 159 +       rt_gpio_w32(rg, (value) ? GPIO_REG_SET : GPIO_REG_RESET, BIT(offset));
 160 +}
 161 +
 162 +static int ralink_gpio_get(struct gpio_chip *chip, unsigned offset)
 163 +{
 164 +       struct ralink_gpio_chip *rg = to_ralink_gpio(chip);
 165 +
 166 +       return !!(rt_gpio_r32(rg, GPIO_REG_DATA) & BIT(offset));
 167 +}
 168 +
 169 +static int ralink_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
 170 +{
 171 +       struct ralink_gpio_chip *rg = to_ralink_gpio(chip);
 172 +       unsigned long flags;
 173 +       u32 t;
 174 +
 175 +       spin_lock_irqsave(&rg->lock, flags);
 176 +       t = rt_gpio_r32(rg, GPIO_REG_DIR);
 177 +       t &= ~BIT(offset);
 178 +       rt_gpio_w32(rg, GPIO_REG_DIR, t);
 179 +       spin_unlock_irqrestore(&rg->lock, flags);
 180 +
 181 +       return 0;
 182 +}
 183 +
 184 +static int ralink_gpio_direction_output(struct gpio_chip *chip,
 185 +                                       unsigned offset, int value)
 186 +{
 187 +       struct ralink_gpio_chip *rg = to_ralink_gpio(chip);
 188 +       unsigned long flags;
 189 +       u32 t;
 190 +
 191 +       spin_lock_irqsave(&rg->lock, flags);
 192 +       ralink_gpio_set(chip, offset, value);
 193 +       t = rt_gpio_r32(rg, GPIO_REG_DIR);
 194 +       t |= BIT(offset);
 195 +       rt_gpio_w32(rg, GPIO_REG_DIR, t);
 196 +       spin_unlock_irqrestore(&rg->lock, flags);
 197 +
 198 +       return 0;
 199 +}
 200 +
 201 +static int ralink_gpio_to_irq(struct gpio_chip *chip, unsigned pin)
 202 +{
 203 +       struct ralink_gpio_chip *rg = to_ralink_gpio(chip);
 204 +
 205 +       if (rg->irq < 1)
 206 +               return -1;
 207 +
 208 +       return irq_create_mapping(rg->domain, pin);
 209 +}
 210 +
 211 +static void ralink_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
 212 +{
 213 +       int i;
 214 +
 215 +       for (i = 0; i < irq_map_count; i++) {
 216 +               struct irq_domain *domain = irq_map[i];
 217 +               struct ralink_gpio_chip *rg;
 218 +               unsigned long pending;
 219 +               int bit;
 220 +
 221 +               rg = (struct ralink_gpio_chip *) domain->host_data;
 222 +               pending = rt_gpio_r32(rg, GPIO_REG_INT);
 223 +
 224 +               for_each_set_bit(bit, &pending, rg->chip.ngpio) {
 225 +                       u32 map = irq_find_mapping(domain, bit);
 226 +                       generic_handle_irq(map);
 227 +                       rt_gpio_w32(rg, GPIO_REG_INT, BIT(bit));
 228 +               }
 229 +       }
 230 +}
 231 +
 232 +static void ralink_gpio_irq_unmask(struct irq_data *d)
 233 +{
 234 +       struct ralink_gpio_chip *rg;
 235 +       unsigned long flags;
 236 +       u32 rise, fall;
 237 +
 238 +       rg = (struct ralink_gpio_chip *) d->domain->host_data;
 239 +       rise = rt_gpio_r32(rg, GPIO_REG_RENA);
 240 +       fall = rt_gpio_r32(rg, GPIO_REG_FENA);
 241 +
 242 +       spin_lock_irqsave(&rg->lock, flags);
 243 +       rt_gpio_w32(rg, GPIO_REG_RENA, rise | (BIT(d->hwirq) & rg->rising));
 244 +       rt_gpio_w32(rg, GPIO_REG_FENA, fall | (BIT(d->hwirq) & rg->falling));
 245 +       spin_unlock_irqrestore(&rg->lock, flags);
 246 +}
 247 +
 248 +static void ralink_gpio_irq_mask(struct irq_data *d)
 249 +{
 250 +       struct ralink_gpio_chip *rg;
 251 +       unsigned long flags;
 252 +       u32 rise, fall;
 253 +
 254 +       rg = (struct ralink_gpio_chip *) d->domain->host_data;
 255 +       rise = rt_gpio_r32(rg, GPIO_REG_RENA);
 256 +       fall = rt_gpio_r32(rg, GPIO_REG_FENA);
 257 +
 258 +       spin_lock_irqsave(&rg->lock, flags);
 259 +       rt_gpio_w32(rg, GPIO_REG_FENA, fall & ~BIT(d->hwirq));
 260 +       rt_gpio_w32(rg, GPIO_REG_RENA, rise & ~BIT(d->hwirq));
 261 +       spin_unlock_irqrestore(&rg->lock, flags);
 262 +}
 263 +
 264 +static int ralink_gpio_irq_type(struct irq_data *d, unsigned int type)
 265 +{
 266 +       struct ralink_gpio_chip *rg;
 267 +       u32 mask = BIT(d->hwirq);
 268 +
 269 +       rg = (struct ralink_gpio_chip *) d->domain->host_data;
 270 +
 271 +       if (type == IRQ_TYPE_PROBE) {
 272 +               if ((rg->rising | rg->falling) & mask)
 273 +                       return 0;
 274 +
 275 +               type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
 276 +       }
 277 +
 278 +       if (type & IRQ_TYPE_EDGE_RISING)
 279 +               rg->rising |= mask;
 280 +       else
 281 +               rg->rising &= ~mask;
 282 +
 283 +       if (type & IRQ_TYPE_EDGE_FALLING)
 284 +               rg->falling |= mask;
 285 +       else
 286 +               rg->falling &= ~mask;
 287 +
 288 +       return 0;
 289 +}
 290 +
 291 +static struct irq_chip ralink_gpio_irq_chip = {
 292 +       .name           = "GPIO",
 293 +       .irq_unmask     = ralink_gpio_irq_unmask,
 294 +       .irq_mask       = ralink_gpio_irq_mask,
 295 +       .irq_mask_ack   = ralink_gpio_irq_mask,
 296 +       .irq_set_type   = ralink_gpio_irq_type,
 297 +};
 298 +
 299 +static int gpio_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
 300 +{
 301 +       irq_set_chip_and_handler(irq, &ralink_gpio_irq_chip, handle_level_irq);
 302 +       irq_set_handler_data(irq, d);
 303 +
 304 +       return 0;
 305 +}
 306 +
 307 +static const struct irq_domain_ops irq_domain_ops = {
 308 +       .xlate = irq_domain_xlate_onecell,
 309 +       .map = gpio_map,
 310 +};
 311 +
 312 +static void ralink_gpio_irq_init(struct device_node *np,
 313 +                                struct ralink_gpio_chip *rg)
 314 +{
 315 +       if (irq_map_count >= MAP_MAX)
 316 +               return;
 317 +
 318 +       rg->irq = irq_of_parse_and_map(np, 0);
 319 +       if (!rg->irq)
 320 +               return;
 321 +
 322 +       rg->domain = irq_domain_add_linear(np, rg->chip.ngpio,
 323 +                                          &irq_domain_ops, rg);
 324 +       if (!rg->domain) {
 325 +               dev_err(rg->chip.dev, "irq_domain_add_linear failed\n");
 326 +               return;
 327 +       }
 328 +
 329 +       irq_map[irq_map_count++] = rg->domain;
 330 +
 331 +       rt_gpio_w32(rg, GPIO_REG_RENA, 0x0);
 332 +       rt_gpio_w32(rg, GPIO_REG_FENA, 0x0);
 333 +
 334 +       if (!atomic_read(&irq_refcount))
 335 +               irq_set_chained_handler(rg->irq, ralink_gpio_irq_handler);
 336 +       atomic_inc(&irq_refcount);
 337 +
 338 +       dev_info(rg->chip.dev, "registering %d irq handlers\n", rg->chip.ngpio);
 339 +}
 340 +
 341 +static int ralink_gpio_request(struct gpio_chip *chip, unsigned offset)
 342 +{
 343 +       int gpio = chip->base + offset;
 344 +
 345 +       return pinctrl_request_gpio(gpio);
 346 +}
 347 +
 348 +static void ralink_gpio_free(struct gpio_chip *chip, unsigned offset)
 349 +{
 350 +       int gpio = chip->base + offset;
 351 +
 352 +       pinctrl_free_gpio(gpio);
 353 +}
 354 +
 355 +static int ralink_gpio_probe(struct platform_device *pdev)
 356 +{
 357 +       struct device_node *np = pdev->dev.of_node;
 358 +       struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 359 +       struct ralink_gpio_chip *rg;
 360 +       const __be32 *ngpio, *gpiobase;
 361 +
 362 +       if (!res) {
 363 +               dev_err(&pdev->dev, "failed to find resource\n");
 364 +               return -ENOMEM;
 365 +       }
 366 +
 367 +       rg = devm_kzalloc(&pdev->dev,
 368 +                       sizeof(struct ralink_gpio_chip), GFP_KERNEL);
 369 +       if (!rg)
 370 +               return -ENOMEM;
 371 +
 372 +       rg->membase = devm_ioremap_resource(&pdev->dev, res);
 373 +       if (!rg->membase) {
 374 +               dev_err(&pdev->dev, "cannot remap I/O memory region\n");
 375 +               return -ENOMEM;
 376 +       }
 377 +
 378 +       if (of_property_read_u8_array(np, "ralink,register-map",
 379 +                       rg->regs, GPIO_REG_MAX)) {
 380 +               dev_err(&pdev->dev, "failed to read register definition\n");
 381 +               return -EINVAL;
 382 +       }
 383 +
 384 +       ngpio = of_get_property(np, "ralink,num-gpios", NULL);
 385 +       if (!ngpio) {
 386 +               dev_err(&pdev->dev, "failed to read number of pins\n");
 387 +               return -EINVAL;
 388 +       }
 389 +
 390 +       gpiobase = of_get_property(np, "ralink,gpio-base", NULL);
 391 +       if (gpiobase)
 392 +               rg->chip.base = be32_to_cpu(*gpiobase);
 393 +       else
 394 +               rg->chip.base = -1;
 395 +
 396 +       spin_lock_init(&rg->lock);
 397 +
 398 +       rg->chip.dev = &pdev->dev;
 399 +       rg->chip.label = dev_name(&pdev->dev);
 400 +       rg->chip.of_node = np;
 401 +       rg->chip.ngpio = be32_to_cpu(*ngpio);
 402 +       rg->chip.direction_input = ralink_gpio_direction_input;
 403 +       rg->chip.direction_output = ralink_gpio_direction_output;
 404 +       rg->chip.get = ralink_gpio_get;
 405 +       rg->chip.set = ralink_gpio_set;
 406 +       rg->chip.request = ralink_gpio_request;
 407 +       rg->chip.to_irq = ralink_gpio_to_irq;
 408 +       rg->chip.free = ralink_gpio_free;
 409 +
 410 +       /* set polarity to low for all lines */
 411 +       rt_gpio_w32(rg, GPIO_REG_POL, 0);
 412 +
 413 +       dev_info(&pdev->dev, "registering %d gpios\n", rg->chip.ngpio);
 414 +
 415 +       ralink_gpio_irq_init(np, rg);
 416 +
 417 +       return gpiochip_add(&rg->chip);
 418 +}
 419 +
 420 +static const struct of_device_id ralink_gpio_match[] = {
 421 +       { .compatible = "ralink,rt2880-gpio" },
 422 +       {},
 423 +};
 424 +MODULE_DEVICE_TABLE(of, ralink_gpio_match);
 425 +
 426 +static struct platform_driver ralink_gpio_driver = {
 427 +       .probe = ralink_gpio_probe,
 428 +       .driver = {
 429 +               .name = "rt2880_gpio",
 430 +               .owner = THIS_MODULE,
 431 +               .of_match_table = ralink_gpio_match,
 432 +       },
 433 +};
 434 +
 435 +static int __init ralink_gpio_init(void)
 436 +{
 437 +       return platform_driver_register(&ralink_gpio_driver);
 438 +}
 439 +
 440 +subsys_initcall(ralink_gpio_init);
 441 --
 442 1.7.10.4
 443