1 From b00b5eafa7e8d059bd0ce844e66f648916953270 Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Sun, 3 Jan 2016 19:11:22 +0100
4 Subject: [PATCH 2/3] phy: ralink-usb: add driver for Mediatek/Ralink
6 Add a driver to setup the USB phy on Mediatek/Ralink SoCs.
7 The driver is trivial and only sets up power and host mode.
9 Signed-off-by: John Crispin <blogic@openwrt.org>
11 .../devicetree/bindings/phy/ralink-usb-phy.txt | 17 ++
12 drivers/phy/Kconfig | 8 +
13 drivers/phy/Makefile | 1 +
14 drivers/phy/phy-ralink-usb.c | 171 ++++++++++++++++++++
15 4 files changed, 197 insertions(+)
16 create mode 100644 Documentation/devicetree/bindings/phy/ralink-usb-phy.txt
17 create mode 100644 drivers/phy/phy-ralink-usb.c
20 +++ b/Documentation/devicetree/bindings/phy/ralink-usb-phy.txt
22 +Mediatek/Ralink USB PHY
25 + - compatible: ralink,rt3352-usbphy or mediatek,mt7620-usbphy
26 + - #phy-cells: should be 0
27 + - resets: the two reset controllers for host and device
28 + - reset-names: the names of the 2 reset controllers
33 + compatible = "mediatek,mt7620-usbphy";
36 + resets = <&rstctrl 22 &rstctrl 25>;
37 + reset-names = "host", "device";
39 --- a/drivers/phy/Kconfig
40 +++ b/drivers/phy/Kconfig
41 @@ -341,6 +341,14 @@ config PHY_XGENE
43 This option enables support for APM X-Gene SoC multi-purpose PHY.
45 +config PHY_RALINK_USB
46 + tristate "Ralink USB PHY driver"
50 + This option enables support for the Ralink USB PHY found inside
53 config PHY_STIH407_USB
54 tristate "STMicroelectronics USB2 picoPHY driver for STiH407 family"
55 depends on RESET_CONTROLLER
56 --- a/drivers/phy/Makefile
57 +++ b/drivers/phy/Makefile
58 @@ -48,3 +48,4 @@ obj-$(CONFIG_PHY_TUSB1210) += phy-tusb1
59 obj-$(CONFIG_PHY_BRCMSTB_SATA) += phy-brcmstb-sata.o
60 obj-$(CONFIG_PHY_PISTACHIO_USB) += phy-pistachio-usb.o
61 obj-$(CONFIG_PHY_CYGNUS_PCIE) += phy-bcm-cygnus-pcie.o
62 +obj-$(CONFIG_PHY_RALINK_USB) += phy-ralink-usb.o
64 +++ b/drivers/phy/phy-ralink-usb.c
67 + * Allwinner ralink USB phy driver
69 + * Copyright (C) 2016 John Crispin <blogic@openwrt.org>
71 + * Based on code from
72 + * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
74 + * This program is free software; you can redistribute it and/or modify
75 + * it under the terms of the GNU General Public License as published by
76 + * the Free Software Foundation; either version 2 of the License, or
77 + * (at your option) any later version.
79 + * This program is distributed in the hope that it will be useful,
80 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
81 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
82 + * GNU General Public License for more details.
85 +#include <linux/delay.h>
86 +#include <linux/err.h>
87 +#include <linux/io.h>
88 +#include <linux/kernel.h>
89 +#include <linux/module.h>
90 +#include <linux/mutex.h>
91 +#include <linux/phy/phy.h>
92 +#include <linux/platform_device.h>
93 +#include <linux/reset.h>
94 +#include <linux/of_platform.h>
96 +#include <asm/mach-ralink/ralink_regs.h>
98 +#define RT_SYSC_REG_SYSCFG1 0x014
99 +#define RT_SYSC_REG_CLKCFG1 0x030
100 +#define RT_SYSC_REG_USB_PHY_CFG 0x05c
102 +#define OFS_U2_PHY_AC0 0x00
103 +#define OFS_U2_PHY_AC1 0x04
104 +#define OFS_U2_PHY_AC2 0x08
105 +#define OFS_U2_PHY_ACR0 0x10
106 +#define OFS_U2_PHY_ACR1 0x14
107 +#define OFS_U2_PHY_ACR2 0x18
108 +#define OFS_U2_PHY_ACR3 0x1C
109 +#define OFS_U2_PHY_ACR4 0x20
110 +#define OFS_U2_PHY_AMON0 0x24
111 +#define OFS_U2_PHY_DCR0 0x60
112 +#define OFS_U2_PHY_DCR1 0x64
113 +#define OFS_U2_PHY_DTM0 0x68
114 +#define OFS_U2_PHY_DTM1 0x6C
116 +#define RT_RSTCTRL_UDEV BIT(25)
117 +#define RT_RSTCTRL_UHST BIT(22)
118 +#define RT_SYSCFG1_USB0_HOST_MODE BIT(10)
120 +#define MT7620_CLKCFG1_UPHY0_CLK_EN BIT(25)
121 +#define MT7620_CLKCFG1_UPHY1_CLK_EN BIT(22)
122 +#define RT_CLKCFG1_UPHY1_CLK_EN BIT(20)
123 +#define RT_CLKCFG1_UPHY0_CLK_EN BIT(18)
125 +#define USB_PHY_UTMI_8B60M BIT(1)
126 +#define UDEV_WAKEUP BIT(0)
128 +struct ralink_usb_phy {
129 + struct reset_control *rstdev;
130 + struct reset_control *rsthost;
133 + void __iomem *base;
136 +static void u2_phy_w32(struct ralink_usb_phy *phy, u32 val, u32 reg)
138 + iowrite32(val, phy->base + reg);
141 +static u32 u2_phy_r32(struct ralink_usb_phy *phy, u32 reg)
143 + return ioread32(phy->base + reg);
147 +u2_phy_init(struct ralink_usb_phy *phy)
149 + u2_phy_r32(phy, OFS_U2_PHY_AC2);
150 + u2_phy_r32(phy, OFS_U2_PHY_ACR0);
151 + u2_phy_r32(phy, OFS_U2_PHY_DCR0);
153 + u2_phy_w32(phy, 0x00ffff02, OFS_U2_PHY_DCR0);
154 + u2_phy_r32(phy, OFS_U2_PHY_DCR0);
155 + u2_phy_w32(phy, 0x00555502, OFS_U2_PHY_DCR0);
156 + u2_phy_r32(phy, OFS_U2_PHY_DCR0);
157 + u2_phy_w32(phy, 0x00aaaa02, OFS_U2_PHY_DCR0);
158 + u2_phy_r32(phy, OFS_U2_PHY_DCR0);
159 + u2_phy_w32(phy, 0x00000402, OFS_U2_PHY_DCR0);
160 + u2_phy_r32(phy, OFS_U2_PHY_DCR0);
161 + u2_phy_w32(phy, 0x0048086a, OFS_U2_PHY_AC0);
162 + u2_phy_w32(phy, 0x4400001c, OFS_U2_PHY_AC1);
163 + u2_phy_w32(phy, 0xc0200000, OFS_U2_PHY_ACR3);
164 + u2_phy_w32(phy, 0x02000000, OFS_U2_PHY_DTM0);
167 +static int ralink_usb_phy_power_on(struct phy *_phy)
169 + struct ralink_usb_phy *phy = phy_get_drvdata(_phy);
172 + /* enable the phy */
173 + rt_sysc_m32(0, phy->clk, RT_SYSC_REG_CLKCFG1);
175 + /* setup host mode */
176 + rt_sysc_m32(0, RT_SYSCFG1_USB0_HOST_MODE, RT_SYSC_REG_SYSCFG1);
178 + /* deassert the reset lines */
179 + reset_control_deassert(phy->rsthost);
180 + reset_control_deassert(phy->rstdev);
183 + * The SDK kernel had a delay of 100ms. however on device
184 + * testing showed that 10ms is enough
188 + if (!IS_ERR(phy->base))
191 + /* print some status info */
192 + t = rt_sysc_r32(RT_SYSC_REG_USB_PHY_CFG);
193 + dev_info(&phy->phy->dev, "remote usb device wakeup %s\n",
194 + (t & UDEV_WAKEUP) ? ("enabled") : ("disabled"));
195 + if (t & USB_PHY_UTMI_8B60M)
196 + dev_info(&phy->phy->dev, "UTMI 8bit 60MHz\n");
198 + dev_info(&phy->phy->dev, "UTMI 16bit 30MHz\n");
203 +static int ralink_usb_phy_power_off(struct phy *_phy)
205 + struct ralink_usb_phy *phy = phy_get_drvdata(_phy);
207 + /* assert the reset lines */
208 + reset_control_assert(phy->rstdev);
209 + reset_control_assert(phy->rsthost);
211 + /* disable the phy */
212 + rt_sysc_m32(phy->clk, 0, RT_SYSC_REG_CLKCFG1);
217 +static struct phy_ops ralink_usb_phy_ops = {
218 + .power_on = ralink_usb_phy_power_on,
219 + .power_off = ralink_usb_phy_power_off,
220 + .owner = THIS_MODULE,
223 +static const struct of_device_id ralink_usb_phy_of_match[] = {
225 + .compatible = "ralink,rt3352-usbphy",
226 + .data = (void *) (RT_CLKCFG1_UPHY1_CLK_EN |
227 + RT_CLKCFG1_UPHY0_CLK_EN)
230 + .compatible = "mediatek,mt7620-usbphy",
231 + .data = (void *) (MT7620_CLKCFG1_UPHY1_CLK_EN |
232 + MT7620_CLKCFG1_UPHY0_CLK_EN) },
235 +MODULE_DEVICE_TABLE(of, ralink_usb_phy_of_match);
237 +static int ralink_usb_phy_probe(struct platform_device *pdev)
239 + struct resource *res;
240 + struct device *dev = &pdev->dev;
241 + struct phy_provider *phy_provider;
242 + const struct of_device_id *match;
243 + struct ralink_usb_phy *phy;
245 + phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);
249 + match = of_match_device(ralink_usb_phy_of_match, &pdev->dev);
253 + phy->clk = (int) match->data;
255 + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
256 + phy->base = devm_ioremap_resource(&pdev->dev, res);
258 + phy->rsthost = devm_reset_control_get(&pdev->dev, "host");
259 + if (IS_ERR(phy->rsthost)) {
260 + dev_err(dev, "host reset is missing\n");
261 + return PTR_ERR(phy->rsthost);
264 + phy->rstdev = devm_reset_control_get(&pdev->dev, "device");
265 + if (IS_ERR(phy->rstdev)) {
266 + dev_err(dev, "device reset is missing\n");
267 + return PTR_ERR(phy->rstdev);
270 + phy->phy = devm_phy_create(dev, NULL, &ralink_usb_phy_ops);
271 + if (IS_ERR(phy->phy)) {
272 + dev_err(dev, "failed to create PHY\n");
273 + return PTR_ERR(phy->phy);
275 + phy_set_drvdata(phy->phy, phy);
277 + phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
279 + return PTR_ERR_OR_ZERO(phy_provider);
282 +static struct platform_driver ralink_usb_phy_driver = {
283 + .probe = ralink_usb_phy_probe,
285 + .of_match_table = ralink_usb_phy_of_match,
286 + .name = "ralink-usb-phy",
289 +module_platform_driver(ralink_usb_phy_driver);
291 +MODULE_DESCRIPTION("Ralink USB phy driver");
292 +MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
293 +MODULE_LICENSE("GPL v2");