1 From 2c39ddc83452c34fedc86261ed1f96d7537adfd1 Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Mon, 14 Dec 2015 21:28:10 +0100
4 Subject: [PATCH 502/513] net-next: mediatek: add switch driver for rt3050
6 This driver is very basic and only provides basic init and irq support.
7 Switchdev support for this device will follow.
9 Signed-off-by: John Crispin <blogic@openwrt.org>
11 drivers/net/ethernet/mediatek/esw_rt3050.c | 640 ++++++++++++++++++++++++++++
12 drivers/net/ethernet/mediatek/esw_rt3050.h | 29 ++
13 2 files changed, 669 insertions(+)
14 create mode 100644 drivers/net/ethernet/mediatek/esw_rt3050.c
15 create mode 100644 drivers/net/ethernet/mediatek/esw_rt3050.h
18 +++ b/drivers/net/ethernet/mediatek/esw_rt3050.c
20 +/* This program is free software; you can redistribute it and/or modify
21 + * it under the terms of the GNU General Public License as published by
22 + * the Free Software Foundation; version 2 of the License
24 + * This program is distributed in the hope that it will be useful,
25 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
26 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
27 + * GNU General Public License for more details.
29 + * Copyright (C) 2009-2015 John Crispin <blogic@openwrt.org>
30 + * Copyright (C) 2009-2015 Felix Fietkau <nbd@openwrt.org>
31 + * Copyright (C) 2013-2015 Michael Lee <igvtee@gmail.com>
34 +#include <linux/module.h>
35 +#include <linux/kernel.h>
36 +#include <linux/types.h>
37 +#include <linux/dma-mapping.h>
38 +#include <linux/init.h>
39 +#include <linux/skbuff.h>
40 +#include <linux/etherdevice.h>
41 +#include <linux/ethtool.h>
42 +#include <linux/platform_device.h>
43 +#include <linux/of_device.h>
44 +#include <linux/clk.h>
45 +#include <linux/of_net.h>
46 +#include <linux/of_mdio.h>
48 +#include <asm/mach-ralink/ralink_regs.h>
50 +#include "mtk_eth_soc.h"
52 +#include <linux/ioport.h>
53 +#include <linux/mii.h>
55 +#include <ralink_regs.h>
57 +/* HW limitations for this switch:
58 + * - No large frame support (PKT_MAX_LEN at most 1536)
59 + * - Can't have untagged vlan and tagged vlan on one port at the same time,
60 + * though this might be possible using the undocumented PPE.
63 +#define RT305X_ESW_REG_ISR 0x00
64 +#define RT305X_ESW_REG_IMR 0x04
65 +#define RT305X_ESW_REG_FCT0 0x08
66 +#define RT305X_ESW_REG_PFC1 0x14
67 +#define RT305X_ESW_REG_ATS 0x24
68 +#define RT305X_ESW_REG_ATS0 0x28
69 +#define RT305X_ESW_REG_ATS1 0x2c
70 +#define RT305X_ESW_REG_ATS2 0x30
71 +#define RT305X_ESW_REG_PVIDC(_n) (0x40 + 4 * (_n))
72 +#define RT305X_ESW_REG_VLANI(_n) (0x50 + 4 * (_n))
73 +#define RT305X_ESW_REG_VMSC(_n) (0x70 + 4 * (_n))
74 +#define RT305X_ESW_REG_POA 0x80
75 +#define RT305X_ESW_REG_FPA 0x84
76 +#define RT305X_ESW_REG_SOCPC 0x8c
77 +#define RT305X_ESW_REG_POC0 0x90
78 +#define RT305X_ESW_REG_POC1 0x94
79 +#define RT305X_ESW_REG_POC2 0x98
80 +#define RT305X_ESW_REG_SGC 0x9c
81 +#define RT305X_ESW_REG_STRT 0xa0
82 +#define RT305X_ESW_REG_PCR0 0xc0
83 +#define RT305X_ESW_REG_PCR1 0xc4
84 +#define RT305X_ESW_REG_FPA2 0xc8
85 +#define RT305X_ESW_REG_FCT2 0xcc
86 +#define RT305X_ESW_REG_SGC2 0xe4
87 +#define RT305X_ESW_REG_P0LED 0xa4
88 +#define RT305X_ESW_REG_P1LED 0xa8
89 +#define RT305X_ESW_REG_P2LED 0xac
90 +#define RT305X_ESW_REG_P3LED 0xb0
91 +#define RT305X_ESW_REG_P4LED 0xb4
92 +#define RT305X_ESW_REG_PXPC(_x) (0xe8 + (4 * _x))
93 +#define RT305X_ESW_REG_P1PC 0xec
94 +#define RT305X_ESW_REG_P2PC 0xf0
95 +#define RT305X_ESW_REG_P3PC 0xf4
96 +#define RT305X_ESW_REG_P4PC 0xf8
97 +#define RT305X_ESW_REG_P5PC 0xfc
99 +#define RT305X_ESW_LED_LINK 0
100 +#define RT305X_ESW_LED_100M 1
101 +#define RT305X_ESW_LED_DUPLEX 2
102 +#define RT305X_ESW_LED_ACTIVITY 3
103 +#define RT305X_ESW_LED_COLLISION 4
104 +#define RT305X_ESW_LED_LINKACT 5
105 +#define RT305X_ESW_LED_DUPLCOLL 6
106 +#define RT305X_ESW_LED_10MACT 7
107 +#define RT305X_ESW_LED_100MACT 8
108 +/* Additional led states not in datasheet: */
109 +#define RT305X_ESW_LED_BLINK 10
110 +#define RT305X_ESW_LED_ON 12
112 +#define RT305X_ESW_LINK_S 25
113 +#define RT305X_ESW_DUPLEX_S 9
114 +#define RT305X_ESW_SPD_S 0
116 +#define RT305X_ESW_PCR0_WT_NWAY_DATA_S 16
117 +#define RT305X_ESW_PCR0_WT_PHY_CMD BIT(13)
118 +#define RT305X_ESW_PCR0_CPU_PHY_REG_S 8
120 +#define RT305X_ESW_PCR1_WT_DONE BIT(0)
122 +#define RT305X_ESW_ATS_TIMEOUT (5 * HZ)
123 +#define RT305X_ESW_PHY_TIMEOUT (5 * HZ)
125 +#define RT305X_ESW_PVIDC_PVID_M 0xfff
126 +#define RT305X_ESW_PVIDC_PVID_S 12
128 +#define RT305X_ESW_VLANI_VID_M 0xfff
129 +#define RT305X_ESW_VLANI_VID_S 12
131 +#define RT305X_ESW_VMSC_MSC_M 0xff
132 +#define RT305X_ESW_VMSC_MSC_S 8
134 +#define RT305X_ESW_SOCPC_DISUN2CPU_S 0
135 +#define RT305X_ESW_SOCPC_DISMC2CPU_S 8
136 +#define RT305X_ESW_SOCPC_DISBC2CPU_S 16
137 +#define RT305X_ESW_SOCPC_CRC_PADDING BIT(25)
139 +#define RT305X_ESW_POC0_EN_BP_S 0
140 +#define RT305X_ESW_POC0_EN_FC_S 8
141 +#define RT305X_ESW_POC0_DIS_RMC2CPU_S 16
142 +#define RT305X_ESW_POC0_DIS_PORT_M 0x7f
143 +#define RT305X_ESW_POC0_DIS_PORT_S 23
145 +#define RT305X_ESW_POC2_UNTAG_EN_M 0xff
146 +#define RT305X_ESW_POC2_UNTAG_EN_S 0
147 +#define RT305X_ESW_POC2_ENAGING_S 8
148 +#define RT305X_ESW_POC2_DIS_UC_PAUSE_S 16
150 +#define RT305X_ESW_SGC2_DOUBLE_TAG_M 0x7f
151 +#define RT305X_ESW_SGC2_DOUBLE_TAG_S 0
152 +#define RT305X_ESW_SGC2_LAN_PMAP_M 0x3f
153 +#define RT305X_ESW_SGC2_LAN_PMAP_S 24
155 +#define RT305X_ESW_PFC1_EN_VLAN_M 0xff
156 +#define RT305X_ESW_PFC1_EN_VLAN_S 16
157 +#define RT305X_ESW_PFC1_EN_TOS_S 24
159 +#define RT305X_ESW_VLAN_NONE 0xfff
161 +#define RT305X_ESW_GSC_BC_STROM_MASK 0x3
162 +#define RT305X_ESW_GSC_BC_STROM_SHIFT 4
164 +#define RT305X_ESW_GSC_LED_FREQ_MASK 0x3
165 +#define RT305X_ESW_GSC_LED_FREQ_SHIFT 23
167 +#define RT305X_ESW_POA_LINK_MASK 0x1f
168 +#define RT305X_ESW_POA_LINK_SHIFT 25
170 +#define RT305X_ESW_PORT_ST_CHG BIT(26)
171 +#define RT305X_ESW_PORT0 0
172 +#define RT305X_ESW_PORT1 1
173 +#define RT305X_ESW_PORT2 2
174 +#define RT305X_ESW_PORT3 3
175 +#define RT305X_ESW_PORT4 4
176 +#define RT305X_ESW_PORT5 5
177 +#define RT305X_ESW_PORT6 6
179 +#define RT305X_ESW_PMAP_LLLLLL 0x3f
180 +#define RT305X_ESW_PMAP_LLLLWL 0x2f
181 +#define RT305X_ESW_PMAP_WLLLLL 0x3e
183 +#define RT305X_ESW_PORTS_INTERNAL \
184 + (BIT(RT305X_ESW_PORT0) | BIT(RT305X_ESW_PORT1) | \
185 + BIT(RT305X_ESW_PORT2) | BIT(RT305X_ESW_PORT3) | \
186 + BIT(RT305X_ESW_PORT4))
188 +#define RT305X_ESW_PORTS_NOCPU \
189 + (RT305X_ESW_PORTS_INTERNAL | BIT(RT305X_ESW_PORT5))
191 +#define RT305X_ESW_PORTS_CPU BIT(RT305X_ESW_PORT6)
193 +#define RT305X_ESW_PORTS_ALL \
194 + (RT305X_ESW_PORTS_NOCPU | RT305X_ESW_PORTS_CPU)
196 +#define RT305X_ESW_NUM_PORTS 7
197 +#define RT305X_ESW_NUM_LEDS 5
199 +#define RT5350_EWS_REG_LED_POLARITY 0x168
200 +#define RT5350_RESET_EPHY BIT(24)
208 + struct device *dev;
209 + void __iomem *base;
212 + /* Protects against concurrent register r/w operations. */
213 + spinlock_t reg_rw_lock;
215 + unsigned char port_map;
216 + unsigned int reg_led_polarity;
218 + struct esw_port ports[RT305X_ESW_NUM_PORTS];
222 +static inline void esw_w32(struct rt305x_esw *esw, u32 val, unsigned reg)
224 + __raw_writel(val, esw->base + reg);
227 +static inline u32 esw_r32(struct rt305x_esw *esw, unsigned reg)
229 + return __raw_readl(esw->base + reg);
232 +static inline void esw_rmw_raw(struct rt305x_esw *esw, unsigned reg,
233 + unsigned long mask, unsigned long val)
237 + t = __raw_readl(esw->base + reg) & ~mask;
238 + __raw_writel(t | val, esw->base + reg);
241 +static void esw_rmw(struct rt305x_esw *esw, unsigned reg,
242 + unsigned long mask, unsigned long val)
244 + unsigned long flags;
246 + spin_lock_irqsave(&esw->reg_rw_lock, flags);
247 + esw_rmw_raw(esw, reg, mask, val);
248 + spin_unlock_irqrestore(&esw->reg_rw_lock, flags);
251 +static u32 rt305x_mii_write(struct rt305x_esw *esw, u32 phy_addr,
252 + u32 phy_register, u32 write_data)
254 + unsigned long t_start = jiffies;
258 + if (!(esw_r32(esw, RT305X_ESW_REG_PCR1) &
259 + RT305X_ESW_PCR1_WT_DONE))
261 + if (time_after(jiffies, t_start + RT305X_ESW_PHY_TIMEOUT)) {
267 + write_data &= 0xffff;
268 + esw_w32(esw, (write_data << RT305X_ESW_PCR0_WT_NWAY_DATA_S) |
269 + (phy_register << RT305X_ESW_PCR0_CPU_PHY_REG_S) |
270 + (phy_addr) | RT305X_ESW_PCR0_WT_PHY_CMD,
271 + RT305X_ESW_REG_PCR0);
275 + if (esw_r32(esw, RT305X_ESW_REG_PCR1) &
276 + RT305X_ESW_PCR1_WT_DONE)
279 + if (time_after(jiffies, t_start + RT305X_ESW_PHY_TIMEOUT)) {
286 + dev_err(esw->dev, "ramips_eth: MDIO timeout\n");
290 +static unsigned esw_get_port_disable(struct rt305x_esw *esw)
294 + reg = esw_r32(esw, RT305X_ESW_REG_POC0);
295 + return (reg >> RT305X_ESW_POC0_DIS_PORT_S) &
296 + RT305X_ESW_POC0_DIS_PORT_M;
299 +static void esw_hw_init(struct rt305x_esw *esw)
302 + u8 port_disable = 0;
303 + u8 port_map = RT305X_ESW_PMAP_LLLLLL;
305 + /* vodoo from original driver */
306 + esw_w32(esw, 0xC8A07850, RT305X_ESW_REG_FCT0);
307 + esw_w32(esw, 0x00000000, RT305X_ESW_REG_SGC2);
308 + /* Port priority 1 for all ports, vlan enabled. */
309 + esw_w32(esw, 0x00005555 |
310 + (RT305X_ESW_PORTS_ALL << RT305X_ESW_PFC1_EN_VLAN_S),
311 + RT305X_ESW_REG_PFC1);
313 + /* Enable Back Pressure, and Flow Control */
314 + esw_w32(esw, ((RT305X_ESW_PORTS_ALL << RT305X_ESW_POC0_EN_BP_S) |
315 + (RT305X_ESW_PORTS_ALL << RT305X_ESW_POC0_EN_FC_S)),
316 + RT305X_ESW_REG_POC0);
318 + /* Enable Aging, and VLAN TAG removal */
319 + esw_w32(esw, ((RT305X_ESW_PORTS_ALL << RT305X_ESW_POC2_ENAGING_S) |
320 + (RT305X_ESW_PORTS_NOCPU << RT305X_ESW_POC2_UNTAG_EN_S)),
321 + RT305X_ESW_REG_POC2);
323 + esw_w32(esw, 0x00d6500c, RT305X_ESW_REG_FCT2);
325 + /* 300s aging timer, max packet len 1536, broadcast storm prevention
326 + * disabled, disable collision abort, mac xor48 hash, 10 packet back
327 + * pressure jam, GMII disable was_transmit, back pressure disabled,
328 + * 30ms led flash, unmatched IGMP as broadcast, rmc tb fault to all
331 + esw_w32(esw, 0x0008a301, RT305X_ESW_REG_SGC);
333 + /* Setup SoC Port control register */
335 + (RT305X_ESW_SOCPC_CRC_PADDING |
336 + (RT305X_ESW_PORTS_CPU << RT305X_ESW_SOCPC_DISUN2CPU_S) |
337 + (RT305X_ESW_PORTS_CPU << RT305X_ESW_SOCPC_DISMC2CPU_S) |
338 + (RT305X_ESW_PORTS_CPU << RT305X_ESW_SOCPC_DISBC2CPU_S)),
339 + RT305X_ESW_REG_SOCPC);
341 + /* ext phy base addr 31, enable port 5 polling, rx/tx clock skew 1,
342 + * turbo mii off, rgmi 3.3v off
344 + * port6: enabled, gige, full-duplex, rx/tx-flow-control
346 + esw_w32(esw, 0x3f502b28, RT305X_ESW_REG_FPA2);
347 + esw_w32(esw, 0x00000000, RT305X_ESW_REG_FPA);
349 + /* Force Link/Activity on ports */
350 + esw_w32(esw, 0x00000005, RT305X_ESW_REG_P0LED);
351 + esw_w32(esw, 0x00000005, RT305X_ESW_REG_P1LED);
352 + esw_w32(esw, 0x00000005, RT305X_ESW_REG_P2LED);
353 + esw_w32(esw, 0x00000005, RT305X_ESW_REG_P3LED);
354 + esw_w32(esw, 0x00000005, RT305X_ESW_REG_P4LED);
356 + /* Copy disabled port configuration from bootloader setup */
357 + port_disable = esw_get_port_disable(esw);
358 + for (i = 0; i < 6; i++)
359 + esw->ports[i].disable = (port_disable & (1 << i)) != 0;
361 + if (ralink_soc == RT305X_SOC_RT3352) {
363 + fe_reset(RT5350_RESET_EPHY);
365 + rt305x_mii_write(esw, 0, 31, 0x8000);
366 + for (i = 0; i < 5; i++) {
367 + if (esw->ports[i].disable) {
368 + rt305x_mii_write(esw, i, MII_BMCR, BMCR_PDOWN);
370 + rt305x_mii_write(esw, i, MII_BMCR,
375 + /* TX10 waveform coefficient LSB=0 disable PHY */
376 + rt305x_mii_write(esw, i, 26, 0x1601);
377 + /* TX100/TX10 AD/DA current bias */
378 + rt305x_mii_write(esw, i, 29, 0x7016);
379 + /* TX100 slew rate control */
380 + rt305x_mii_write(esw, i, 30, 0x0038);
383 + /* select global register */
384 + rt305x_mii_write(esw, 0, 31, 0x0);
385 + /* enlarge agcsel threshold 3 and threshold 2 */
386 + rt305x_mii_write(esw, 0, 1, 0x4a40);
387 + /* enlarge agcsel threshold 5 and threshold 4 */
388 + rt305x_mii_write(esw, 0, 2, 0x6254);
389 + /* enlarge agcsel threshold */
390 + rt305x_mii_write(esw, 0, 3, 0xa17f);
391 + rt305x_mii_write(esw, 0, 12, 0x7eaa);
392 + /* longer TP_IDL tail length */
393 + rt305x_mii_write(esw, 0, 14, 0x65);
394 + /* increased squelch pulse count threshold. */
395 + rt305x_mii_write(esw, 0, 16, 0x0684);
396 + /* set TX10 signal amplitude threshold to minimum */
397 + rt305x_mii_write(esw, 0, 17, 0x0fe0);
398 + /* set squelch amplitude to higher threshold */
399 + rt305x_mii_write(esw, 0, 18, 0x40ba);
400 + /* tune TP_IDL tail and head waveform, enable power
401 + * down slew rate control
403 + rt305x_mii_write(esw, 0, 22, 0x253f);
404 + /* set PLL/Receive bias current are calibrated */
405 + rt305x_mii_write(esw, 0, 27, 0x2fda);
406 + /* change PLL/Receive bias current to internal(RT3350) */
407 + rt305x_mii_write(esw, 0, 28, 0xc410);
408 + /* change PLL bias current to internal(RT3052_MP3) */
409 + rt305x_mii_write(esw, 0, 29, 0x598b);
410 + /* select local register */
411 + rt305x_mii_write(esw, 0, 31, 0x8000);
412 + } else if (ralink_soc == RT305X_SOC_RT5350) {
414 + fe_reset(RT5350_RESET_EPHY);
416 + /* set the led polarity */
417 + esw_w32(esw, esw->reg_led_polarity & 0x1F,
418 + RT5350_EWS_REG_LED_POLARITY);
420 + /* local registers */
421 + rt305x_mii_write(esw, 0, 31, 0x8000);
422 + for (i = 0; i < 5; i++) {
423 + if (esw->ports[i].disable) {
424 + rt305x_mii_write(esw, i, MII_BMCR, BMCR_PDOWN);
426 + rt305x_mii_write(esw, i, MII_BMCR,
431 + /* TX10 waveform coefficient LSB=0 disable PHY */
432 + rt305x_mii_write(esw, i, 26, 0x1601);
433 + /* TX100/TX10 AD/DA current bias */
434 + rt305x_mii_write(esw, i, 29, 0x7015);
435 + /* TX100 slew rate control */
436 + rt305x_mii_write(esw, i, 30, 0x0038);
439 + /* global registers */
440 + rt305x_mii_write(esw, 0, 31, 0x0);
441 + /* enlarge agcsel threshold 3 and threshold 2 */
442 + rt305x_mii_write(esw, 0, 1, 0x4a40);
443 + /* enlarge agcsel threshold 5 and threshold 4 */
444 + rt305x_mii_write(esw, 0, 2, 0x6254);
445 + /* enlarge agcsel threshold 6 */
446 + rt305x_mii_write(esw, 0, 3, 0xa17f);
447 + rt305x_mii_write(esw, 0, 12, 0x7eaa);
448 + /* longer TP_IDL tail length */
449 + rt305x_mii_write(esw, 0, 14, 0x65);
450 + /* increased squelch pulse count threshold. */
451 + rt305x_mii_write(esw, 0, 16, 0x0684);
452 + /* set TX10 signal amplitude threshold to minimum */
453 + rt305x_mii_write(esw, 0, 17, 0x0fe0);
454 + /* set squelch amplitude to higher threshold */
455 + rt305x_mii_write(esw, 0, 18, 0x40ba);
456 + /* tune TP_IDL tail and head waveform, enable power
457 + * down slew rate control
459 + rt305x_mii_write(esw, 0, 22, 0x253f);
460 + /* set PLL/Receive bias current are calibrated */
461 + rt305x_mii_write(esw, 0, 27, 0x2fda);
462 + /* change PLL/Receive bias current to internal(RT3350) */
463 + rt305x_mii_write(esw, 0, 28, 0xc410);
464 + /* change PLL bias current to internal(RT3052_MP3) */
465 + rt305x_mii_write(esw, 0, 29, 0x598b);
466 + /* select local register */
467 + rt305x_mii_write(esw, 0, 31, 0x8000);
468 + } else if (ralink_soc == MT762X_SOC_MT7628AN || ralink_soc == MT762X_SOC_MT7688) {
472 + fe_reset(RT5350_RESET_EPHY);
474 + rt305x_mii_write(esw, 0, 31, 0x2000); /* change G2 page */
475 + rt305x_mii_write(esw, 0, 26, 0x0020);
477 + for (i = 0; i < 5; i++) {
478 + rt305x_mii_write(esw, i, 31, 0x8000);
479 + rt305x_mii_write(esw, i, 0, 0x3100);
480 + rt305x_mii_write(esw, i, 30, 0xa000);
481 + rt305x_mii_write(esw, i, 31, 0xa000);
482 + rt305x_mii_write(esw, i, 16, 0x0606);
483 + rt305x_mii_write(esw, i, 23, 0x0f0e);
484 + rt305x_mii_write(esw, i, 24, 0x1610);
485 + rt305x_mii_write(esw, i, 30, 0x1f15);
486 + rt305x_mii_write(esw, i, 28, 0x6111);
487 + rt305x_mii_write(esw, i, 31, 0x2000);
488 + rt305x_mii_write(esw, i, 26, 0x0000);
491 + /* 100Base AOI setting */
492 + rt305x_mii_write(esw, 0, 31, 0x5000);
493 + rt305x_mii_write(esw, 0, 19, 0x004a);
494 + rt305x_mii_write(esw, 0, 20, 0x015a);
495 + rt305x_mii_write(esw, 0, 21, 0x00ee);
496 + rt305x_mii_write(esw, 0, 22, 0x0033);
497 + rt305x_mii_write(esw, 0, 23, 0x020a);
498 + rt305x_mii_write(esw, 0, 24, 0x0000);
499 + rt305x_mii_write(esw, 0, 25, 0x024a);
500 + rt305x_mii_write(esw, 0, 26, 0x035a);
501 + rt305x_mii_write(esw, 0, 27, 0x02ee);
502 + rt305x_mii_write(esw, 0, 28, 0x0233);
503 + rt305x_mii_write(esw, 0, 29, 0x000a);
504 + rt305x_mii_write(esw, 0, 30, 0x0000);
506 + rt305x_mii_write(esw, 0, 31, 0x8000);
507 + for (i = 0; i < 5; i++) {
508 + if (esw->ports[i].disable) {
509 + rt305x_mii_write(esw, i, MII_BMCR, BMCR_PDOWN);
511 + rt305x_mii_write(esw, i, MII_BMCR,
516 + /* TX10 waveform coefficient */
517 + rt305x_mii_write(esw, i, 26, 0x1601);
518 + /* TX100/TX10 AD/DA current bias */
519 + rt305x_mii_write(esw, i, 29, 0x7058);
520 + /* TX100 slew rate control */
521 + rt305x_mii_write(esw, i, 30, 0x0018);
525 + /* select global register */
526 + rt305x_mii_write(esw, 0, 31, 0x0);
527 + /* tune TP_IDL tail and head waveform */
528 + rt305x_mii_write(esw, 0, 22, 0x052f);
529 + /* set TX10 signal amplitude threshold to minimum */
530 + rt305x_mii_write(esw, 0, 17, 0x0fe0);
531 + /* set squelch amplitude to higher threshold */
532 + rt305x_mii_write(esw, 0, 18, 0x40ba);
533 + /* longer TP_IDL tail length */
534 + rt305x_mii_write(esw, 0, 14, 0x65);
535 + /* select local register */
536 + rt305x_mii_write(esw, 0, 31, 0x8000);
540 + port_map = esw->port_map;
542 + port_map = RT305X_ESW_PMAP_LLLLLL;
544 + /* Unused HW feature, but still nice to be consistent here...
545 + * This is also exported to userspace ('lan' attribute) so it's
546 + * conveniently usable to decide which ports go into the wan vlan by
549 + esw_rmw(esw, RT305X_ESW_REG_SGC2,
550 + RT305X_ESW_SGC2_LAN_PMAP_M << RT305X_ESW_SGC2_LAN_PMAP_S,
551 + port_map << RT305X_ESW_SGC2_LAN_PMAP_S);
553 + /* make the switch leds blink */
554 + for (i = 0; i < RT305X_ESW_NUM_LEDS; i++)
555 + esw->ports[i].led = 0x05;
557 + /* Only unmask the port change interrupt */
558 + esw_w32(esw, ~RT305X_ESW_PORT_ST_CHG, RT305X_ESW_REG_IMR);
561 +static irqreturn_t esw_interrupt(int irq, void *_esw)
563 + struct rt305x_esw *esw = (struct rt305x_esw *)_esw;
566 + status = esw_r32(esw, RT305X_ESW_REG_ISR);
567 + if (status & RT305X_ESW_PORT_ST_CHG) {
568 + u32 link = esw_r32(esw, RT305X_ESW_REG_POA);
570 + link >>= RT305X_ESW_POA_LINK_SHIFT;
571 + link &= RT305X_ESW_POA_LINK_MASK;
572 + dev_info(esw->dev, "link changed 0x%02X\n", link);
574 + esw_w32(esw, status, RT305X_ESW_REG_ISR);
576 + return IRQ_HANDLED;
579 +static int esw_probe(struct platform_device *pdev)
581 + struct resource *res = platform_get_resource(p, IORESOURCE_MEM, 0);
582 + struct device_node *np = pdev->dev.of_node;
583 + const __be32 *port_map, *reg_init;
584 + struct rt305x_esw *esw;
585 + struct resource *irq;
588 + esw = devm_kzalloc(&pdev->dev, sizeof(*esw), GFP_KERNEL);
592 + esw->dev = &pdev->dev;
593 + esw->irq = irq->start;
594 + esw->base = devm_ioremap_resource(&pdev->dev, res);
596 + return -EADDRNOTAVAIL;
598 + port_map = of_get_property(np, "mediatek,portmap", NULL);
600 + esw->port_map = be32_to_cpu(*port_map);
602 + reg_init = of_get_property(np, "mediatek,led_polarity", NULL);
604 + esw->reg_led_polarity = be32_to_cpu(*reg_init);
606 + platform_set_drvdata(pdev, esw);
608 + spin_lock_init(&esw->reg_rw_lock);
612 + ret = devm_request_irq(&pdev->dev, esw->irq, esw_interrupt, 0, "esw",
616 + esw_w32(esw, RT305X_ESW_PORT_ST_CHG, RT305X_ESW_REG_ISR);
617 + esw_w32(esw, ~RT305X_ESW_PORT_ST_CHG, RT305X_ESW_REG_IMR);
623 +static int esw_remove(struct platform_device *pdev)
625 + struct rt305x_esw *esw = platform_get_drvdata(pdev);
628 + esw_w32(esw, ~0, RT305X_ESW_REG_IMR);
629 + platform_set_drvdata(pdev, NULL);
635 +static const struct of_device_id ralink_esw_match[] = {
636 + { .compatible = "ralink,rt3050-esw" },
639 +MODULE_DEVICE_TABLE(of, ralink_esw_match);
641 +static struct platform_driver esw_driver = {
642 + .probe = esw_probe,
643 + .remove = esw_remove,
645 + .name = "rt3050-esw",
646 + .owner = THIS_MODULE,
647 + .of_match_table = ralink_esw_match,
651 +int __init mtk_switch_init(void)
653 + return platform_driver_register(&esw_driver);
656 +void mtk_switch_exit(void)
658 + platform_driver_unregister(&esw_driver);
661 +++ b/drivers/net/ethernet/mediatek/esw_rt3050.h
663 +/* This program is free software; you can redistribute it and/or modify
664 + * it under the terms of the GNU General Public License as published by
665 + * the Free Software Foundation; version 2 of the License
667 + * This program is distributed in the hope that it will be useful,
668 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
669 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
670 + * GNU General Public License for more details.
672 + * Copyright (C) 2009-2015 John Crispin <blogic@openwrt.org>
673 + * Copyright (C) 2009-2015 Felix Fietkau <nbd@openwrt.org>
674 + * Copyright (C) 2013-2015 Michael Lee <igvtee@gmail.com>
677 +#ifndef _RALINK_ESW_RT3052_H__
678 +#define _RALINK_ESW_RT3052_H__
680 +#ifdef CONFIG_NET_MEDIATEK_ESW_RT3052
682 +int __init mtk_switch_init(void);
683 +void mtk_switch_exit(void);
687 +static inline int __init mtk_switch_init(void) { return 0; }
688 +static inline void mtk_switch_exit(void) { }