1 From 9fc19d5f7354709298dcb15b3a4c7cd9a18acebf Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Mon, 14 Dec 2015 21:24:46 +0100
4 Subject: [PATCH 504/513] net-next: mediatek: add switch driver for mt7621
6 This driver is very basic and only provides basic init and irq support.
7 Switchdev support for this device will follow.
9 Signed-off-by: John Crispin <blogic@openwrt.org>
11 drivers/net/ethernet/mediatek/gsw_mt7621.c | 284 ++++++++++++++++++++++++++++
12 1 file changed, 284 insertions(+)
13 create mode 100644 drivers/net/ethernet/mediatek/gsw_mt7621.c
16 +++ b/drivers/net/ethernet/mediatek/gsw_mt7621.c
18 +/* This program is free software; you can redistribute it and/or modify
19 + * it under the terms of the GNU General Public License as published by
20 + * the Free Software Foundation; version 2 of the License
22 + * This program is distributed in the hope that it will be useful,
23 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
24 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
25 + * GNU General Public License for more details.
27 + * Copyright (C) 2009-2015 John Crispin <blogic@openwrt.org>
28 + * Copyright (C) 2009-2015 Felix Fietkau <nbd@nbd.name>
29 + * Copyright (C) 2013-2015 Michael Lee <igvtee@gmail.com>
32 +#include <linux/module.h>
33 +#include <linux/kernel.h>
34 +#include <linux/types.h>
35 +#include <linux/platform_device.h>
36 +#include <linux/of_device.h>
37 +#include <linux/of_irq.h>
39 +#include <ralink_regs.h>
41 +#include "mtk_eth_soc.h"
42 +#include "gsw_mt7620.h"
44 +void mtk_switch_w32(struct mt7620_gsw *gsw, u32 val, unsigned reg)
46 + iowrite32(val, gsw->base + reg);
49 +u32 mtk_switch_r32(struct mt7620_gsw *gsw, unsigned reg)
51 + return ioread32(gsw->base + reg);
54 +static irqreturn_t gsw_interrupt_mt7621(int irq, void *_priv)
56 + struct fe_priv *priv = (struct fe_priv *)_priv;
57 + struct mt7620_gsw *gsw = (struct mt7620_gsw *)priv->soc->swpriv;
60 + reg = mt7530_mdio_r32(gsw, 0x700c);
62 + for (i = 0; i < 5; i++)
66 + link = mt7530_mdio_r32(gsw,
67 + 0x3008 + (i * 0x100)) & 0x1;
69 + if (link != priv->link[i]) {
70 + priv->link[i] = link;
72 + netdev_info(priv->netdev,
73 + "port %d link up\n", i);
75 + netdev_info(priv->netdev,
76 + "port %d link down\n", i);
80 + mt7530_mdio_w32(gsw, 0x700c, 0x1f);
85 +static void mt7621_hw_init(struct mt7620_gsw *gsw, struct device_node *np)
90 + /* wardware reset the switch */
91 + fe_reset(RST_CTRL_MCM);
94 + /* reduce RGMII2 PAD driving strength */
95 + rt_sysc_m32(3 << 4, 0, SYSC_PAD_RGMII2_MDIO);
97 + /* gpio mux - RGMII1=Normal mode */
98 + rt_sysc_m32(BIT(14), 0, SYSC_GPIO_MODE);
100 + /* set GMAC1 RGMII mode */
101 + rt_sysc_m32(3 << 12, 0, SYSC_REG_CFG1);
103 + /* enable MDIO to control MT7530 */
104 + rt_sysc_m32(3 << 12, 0, SYSC_GPIO_MODE);
106 + /* turn off all PHYs */
107 + for (i = 0; i <= 4; i++) {
108 + val = _mt7620_mii_read(gsw, i, 0x0);
110 + _mt7620_mii_write(gsw, i, 0x0, val);
113 + /* reset the switch */
114 + mt7530_mdio_w32(gsw, 0x7000, 0x3);
115 + usleep_range(10, 20);
117 + if ((rt_sysc_r32(SYSC_REG_CHIP_REV_ID) & 0xFFFF) == 0x0101) {
118 + /* (GE1, Force 1000M/FD, FC ON, MAX_RX_LENGTH 1536) */
119 + mtk_switch_w32(gsw, 0x2105e30b, 0x100);
120 + mt7530_mdio_w32(gsw, 0x3600, 0x5e30b);
122 + /* (GE1, Force 1000M/FD, FC ON, MAX_RX_LENGTH 1536) */
123 + mtk_switch_w32(gsw, 0x2105e33b, 0x100);
124 + mt7530_mdio_w32(gsw, 0x3600, 0x5e33b);
127 + /* (GE2, Link down) */
128 + mtk_switch_w32(gsw, 0x8000, 0x200);
130 + /* Enable Port 6, P5 as GMAC5, P5 disable */
131 + val = mt7530_mdio_r32(gsw, 0x7804);
133 + val |= BIT(6) | BIT(13) | BIT(16);
134 + mt7530_mdio_w32(gsw, 0x7804, val);
136 + val = rt_sysc_r32(0x10);
137 + val = (val >> 6) & 0x7;
139 + /* 25Mhz Xtal - do nothing */
140 + } else if (val >= 3) {
143 + /* disable MT7530 core clock */
144 + _mt7620_mii_write(gsw, 0, 13, 0x1f);
145 + _mt7620_mii_write(gsw, 0, 14, 0x410);
146 + _mt7620_mii_write(gsw, 0, 13, 0x401f);
147 + _mt7620_mii_write(gsw, 0, 14, 0x0);
149 + /* disable MT7530 PLL */
150 + _mt7620_mii_write(gsw, 0, 13, 0x1f);
151 + _mt7620_mii_write(gsw, 0, 14, 0x40d);
152 + _mt7620_mii_write(gsw, 0, 13, 0x401f);
153 + _mt7620_mii_write(gsw, 0, 14, 0x2020);
155 + /* for MT7530 core clock = 500Mhz */
156 + _mt7620_mii_write(gsw, 0, 13, 0x1f);
157 + _mt7620_mii_write(gsw, 0, 14, 0x40e);
158 + _mt7620_mii_write(gsw, 0, 13, 0x401f);
159 + _mt7620_mii_write(gsw, 0, 14, 0x119);
161 + /* enable MT7530 PLL */
162 + _mt7620_mii_write(gsw, 0, 13, 0x1f);
163 + _mt7620_mii_write(gsw, 0, 14, 0x40d);
164 + _mt7620_mii_write(gsw, 0, 13, 0x401f);
165 + _mt7620_mii_write(gsw, 0, 14, 0x2820);
167 + usleep_range(20, 40);
169 + /* enable MT7530 core clock */
170 + _mt7620_mii_write(gsw, 0, 13, 0x1f);
171 + _mt7620_mii_write(gsw, 0, 14, 0x410);
172 + _mt7620_mii_write(gsw, 0, 13, 0x401f);
174 + /* 20Mhz Xtal - TODO */
178 + _mt7620_mii_write(gsw, 0, 14, 0x1);
180 + /* set MT7530 central align */
181 + val = mt7530_mdio_r32(gsw, 0x7830);
184 + mt7530_mdio_w32(gsw, 0x7830, val);
185 + val = mt7530_mdio_r32(gsw, 0x7a40);
187 + mt7530_mdio_w32(gsw, 0x7a40, val);
188 + mt7530_mdio_w32(gsw, 0x7a78, 0x855);
190 + /* delay setting for 10/1000M */
191 + mt7530_mdio_w32(gsw, 0x7b00, 0x102);
192 + mt7530_mdio_w32(gsw, 0x7b04, 0x14);
194 + /* lower Tx Driving*/
195 + mt7530_mdio_w32(gsw, 0x7a54, 0x44);
196 + mt7530_mdio_w32(gsw, 0x7a5c, 0x44);
197 + mt7530_mdio_w32(gsw, 0x7a64, 0x44);
198 + mt7530_mdio_w32(gsw, 0x7a6c, 0x44);
199 + mt7530_mdio_w32(gsw, 0x7a74, 0x44);
200 + mt7530_mdio_w32(gsw, 0x7a7c, 0x44);
202 + /* turn on all PHYs */
203 + for (i = 0; i <= 4; i++) {
204 + val = _mt7620_mii_read(gsw, i, 0);
206 + _mt7620_mii_write(gsw, i, 0, val);
210 + val = mt7530_mdio_r32(gsw, 0x7808);
212 + mt7530_mdio_w32(gsw, 0x7808, val);
215 +static const struct of_device_id mediatek_gsw_match[] = {
216 + { .compatible = "mediatek,mt7621-gsw" },
219 +MODULE_DEVICE_TABLE(of, mediatek_gsw_match);
221 +int mtk_gsw_init(struct fe_priv *priv)
223 + struct device_node *np = priv->switch_np;
224 + struct platform_device *pdev = of_find_device_by_node(np);
225 + struct mt7620_gsw *gsw;
230 + if (!of_device_is_compatible(np, mediatek_gsw_match->compatible))
233 + gsw = platform_get_drvdata(pdev);
234 + priv->soc->swpriv = gsw;
236 + mt7621_hw_init(gsw, np);
239 + request_irq(gsw->irq, gsw_interrupt_mt7621, 0,
241 + mt7530_mdio_w32(gsw, 0x7008, 0x1f);
247 +static int mt7621_gsw_probe(struct platform_device *pdev)
249 + struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
250 + const char *port4 = NULL;
251 + struct mt7620_gsw *gsw;
252 + struct device_node *np;
254 + gsw = devm_kzalloc(&pdev->dev, sizeof(struct mt7620_gsw), GFP_KERNEL);
258 + gsw->base = devm_ioremap_resource(&pdev->dev, res);
260 + return -EADDRNOTAVAIL;
262 + gsw->dev = &pdev->dev;
264 + of_property_read_string(np, "mediatek,port4", &port4);
265 + if (port4 && !strcmp(port4, "ephy"))
266 + gsw->port4 = PORT4_EPHY;
267 + else if (port4 && !strcmp(port4, "gmac"))
268 + gsw->port4 = PORT4_EXT;
270 + gsw->port4 = PORT4_EPHY;
272 + gsw->irq = irq_of_parse_and_map(np, 0);
274 + platform_set_drvdata(pdev, gsw);
279 +static int mt7621_gsw_remove(struct platform_device *pdev)
281 + platform_set_drvdata(pdev, NULL);
286 +static struct platform_driver gsw_driver = {
287 + .probe = mt7621_gsw_probe,
288 + .remove = mt7621_gsw_remove,
290 + .name = "mt7621-gsw",
291 + .owner = THIS_MODULE,
292 + .of_match_table = mediatek_gsw_match,
296 +module_platform_driver(gsw_driver);
298 +MODULE_LICENSE("GPL");
299 +MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
300 +MODULE_DESCRIPTION("GBit switch driver for Mediatek MT7621 SoC");
301 +MODULE_VERSION(MTK_FE_DRV_VERSION);