1 From f8c8f4bd2a13e0cc060c93812377373d436f7f02 Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Wed, 18 Nov 2015 03:13:05 +0100
4 Subject: [PATCH 505/513] net-next: mediatek: add support for rt2880
6 rt2880 is the oldest SoC with this core. It has a single gBit port that will
7 normally be attached to an external phy of switch. The patch also adds the
8 code required to drive the mdio bus.
10 Signed-off-by: John Crispin <blogic@openwrt.org>
11 Signed-off-by: Felix Fietkau <nbd@nbd.name>
12 Signed-off-by: Michael Lee <igvtee@gmail.com>
14 drivers/net/ethernet/mediatek/mdio_rt2880.c | 222 +++++++++++++++++++++++++++
15 drivers/net/ethernet/mediatek/mdio_rt2880.h | 23 +++
16 drivers/net/ethernet/mediatek/soc_rt2880.c | 76 +++++++++
17 3 files changed, 321 insertions(+)
18 create mode 100644 drivers/net/ethernet/mediatek/mdio_rt2880.c
19 create mode 100644 drivers/net/ethernet/mediatek/mdio_rt2880.h
20 create mode 100644 drivers/net/ethernet/mediatek/soc_rt2880.c
23 +++ b/drivers/net/ethernet/mediatek/mdio_rt2880.c
25 +/* This program is free software; you can redistribute it and/or modify
26 + * it under the terms of the GNU General Public License as published by
27 + * the Free Software Foundation; version 2 of the License
29 + * This program is distributed in the hope that it will be useful,
30 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
31 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
32 + * GNU General Public License for more details.
34 + * Copyright (C) 2009-2015 John Crispin <blogic@openwrt.org>
35 + * Copyright (C) 2009-2015 Felix Fietkau <nbd@nbd.name>
36 + * Copyright (C) 2013-2015 Michael Lee <igvtee@gmail.com>
39 +#include <linux/module.h>
40 +#include <linux/kernel.h>
41 +#include <linux/types.h>
42 +#include <linux/of_net.h>
43 +#include <linux/of_mdio.h>
45 +#include "mtk_eth_soc.h"
46 +#include "mdio_rt2880.h"
49 +#define FE_MDIO_RETRY 1000
51 +static unsigned char *rt2880_speed_str(struct fe_priv *priv)
53 + switch (priv->phy->speed[0]) {
65 +void rt2880_mdio_link_adjust(struct fe_priv *priv, int port)
69 + if (!priv->link[0]) {
70 + netif_carrier_off(priv->netdev);
71 + netdev_info(priv->netdev, "link down\n");
75 + mdio_cfg = FE_MDIO_CFG_TX_CLK_SKEW_200 |
76 + FE_MDIO_CFG_RX_CLK_SKEW_200 |
77 + FE_MDIO_CFG_GP1_FRC_EN;
79 + if (priv->phy->duplex[0] == DUPLEX_FULL)
80 + mdio_cfg |= FE_MDIO_CFG_GP1_DUPLEX;
82 + if (priv->phy->tx_fc[0])
83 + mdio_cfg |= FE_MDIO_CFG_GP1_FC_TX;
85 + if (priv->phy->rx_fc[0])
86 + mdio_cfg |= FE_MDIO_CFG_GP1_FC_RX;
88 + switch (priv->phy->speed[0]) {
90 + mdio_cfg |= FE_MDIO_CFG_GP1_SPEED_10;
93 + mdio_cfg |= FE_MDIO_CFG_GP1_SPEED_100;
96 + mdio_cfg |= FE_MDIO_CFG_GP1_SPEED_1000;
102 + fe_w32(mdio_cfg, FE_MDIO_CFG);
104 + netif_carrier_on(priv->netdev);
105 + netdev_info(priv->netdev, "link up (%sMbps/%s duplex)\n",
106 + rt2880_speed_str(priv),
107 + (priv->phy->duplex[0] == DUPLEX_FULL) ? "Full" : "Half");
110 +static int rt2880_mdio_wait_ready(struct fe_priv *priv)
114 + retries = FE_MDIO_RETRY;
118 + t = fe_r32(FE_MDIO_ACCESS);
119 + if ((t & BIT(31)) == 0)
122 + if (retries-- == 0)
128 + dev_err(priv->device, "MDIO operation timed out\n");
132 +int rt2880_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg)
134 + struct fe_priv *priv = bus->priv;
138 + err = rt2880_mdio_wait_ready(priv);
142 + t = (phy_addr << 24) | (phy_reg << 16);
143 + fe_w32(t, FE_MDIO_ACCESS);
145 + fe_w32(t, FE_MDIO_ACCESS);
147 + err = rt2880_mdio_wait_ready(priv);
151 + pr_debug("%s: addr=%04x, reg=%04x, value=%04x\n", __func__,
152 + phy_addr, phy_reg, fe_r32(FE_MDIO_ACCESS) & 0xffff);
154 + return fe_r32(FE_MDIO_ACCESS) & 0xffff;
157 +int rt2880_mdio_write(struct mii_bus *bus, int phy_addr, int phy_reg, u16 val)
159 + struct fe_priv *priv = bus->priv;
163 + pr_debug("%s: addr=%04x, reg=%04x, value=%04x\n", __func__,
164 + phy_addr, phy_reg, fe_r32(FE_MDIO_ACCESS) & 0xffff);
166 + err = rt2880_mdio_wait_ready(priv);
170 + t = (1 << 30) | (phy_addr << 24) | (phy_reg << 16) | val;
171 + fe_w32(t, FE_MDIO_ACCESS);
173 + fe_w32(t, FE_MDIO_ACCESS);
175 + return rt2880_mdio_wait_ready(priv);
178 +void rt2880_port_init(struct fe_priv *priv, struct device_node *np)
180 + const __be32 *id = of_get_property(np, "reg", NULL);
181 + const __be32 *link;
185 + if (!id || (be32_to_cpu(*id) != 0)) {
186 + pr_err("%s: invalid port id\n", np->name);
190 + priv->phy->phy_fixed[0] = of_get_property(np,
191 + "mediatek,fixed-link", &size);
192 + if (priv->phy->phy_fixed[0] &&
193 + (size != (4 * sizeof(*priv->phy->phy_fixed[0])))) {
194 + pr_err("%s: invalid fixed link property\n", np->name);
195 + priv->phy->phy_fixed[0] = NULL;
199 + phy_mode = of_get_phy_mode(np);
200 + switch (phy_mode) {
201 + case PHY_INTERFACE_MODE_RGMII:
203 + case PHY_INTERFACE_MODE_MII:
205 + case PHY_INTERFACE_MODE_RMII:
208 + if (!priv->phy->phy_fixed[0])
209 + dev_err(priv->device, "port %d - invalid phy mode\n",
210 + priv->phy->speed[0]);
214 + priv->phy->phy_node[0] = of_parse_phandle(np, "phy-handle", 0);
215 + if (!priv->phy->phy_node[0] && !priv->phy->phy_fixed[0])
218 + if (priv->phy->phy_fixed[0]) {
219 + link = priv->phy->phy_fixed[0];
220 + priv->phy->speed[0] = be32_to_cpup(link++);
221 + priv->phy->duplex[0] = be32_to_cpup(link++);
222 + priv->phy->tx_fc[0] = be32_to_cpup(link++);
223 + priv->phy->rx_fc[0] = be32_to_cpup(link++);
226 + switch (priv->phy->speed[0]) {
234 + dev_err(priv->device, "invalid link speed: %d\n",
235 + priv->phy->speed[0]);
236 + priv->phy->phy_fixed[0] = 0;
239 + dev_info(priv->device, "using fixed link parameters\n");
240 + rt2880_mdio_link_adjust(priv, 0);
244 + if (priv->phy->phy_node[0] && priv->mii_bus->phy_map[0])
245 + fe_connect_phy_node(priv, priv->phy->phy_node[0]);
248 +++ b/drivers/net/ethernet/mediatek/mdio_rt2880.h
250 +/* This program is free software; you can redistribute it and/or modify
251 + * it under the terms of the GNU General Public License as published by
252 + * the Free Software Foundation; version 2 of the License
254 + * This program is distributed in the hope that it will be useful,
255 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
256 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
257 + * GNU General Public License for more details.
259 + * Copyright (C) 2009-2015 John Crispin <blogic@openwrt.org>
260 + * Copyright (C) 2009-2015 Felix Fietkau <nbd@nbd.name>
261 + * Copyright (C) 2013-2015 Michael Lee <igvtee@gmail.com>
264 +#ifndef _RALINK_MDIO_RT2880_H__
265 +#define _RALINK_MDIO_RT2880_H__
267 +void rt2880_mdio_link_adjust(struct fe_priv *priv, int port);
268 +int rt2880_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg);
269 +int rt2880_mdio_write(struct mii_bus *bus, int phy_addr, int phy_reg, u16 val);
270 +void rt2880_port_init(struct fe_priv *priv, struct device_node *np);
274 +++ b/drivers/net/ethernet/mediatek/soc_rt2880.c
276 +/* This program is free software; you can redistribute it and/or modify
277 + * it under the terms of the GNU General Public License as published by
278 + * the Free Software Foundation; version 2 of the License
280 + * This program is distributed in the hope that it will be useful,
281 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
282 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
283 + * GNU General Public License for more details.
285 + * Copyright (C) 2009-2015 John Crispin <blogic@openwrt.org>
286 + * Copyright (C) 2009-2015 Felix Fietkau <nbd@nbd.name>
287 + * Copyright (C) 2013-2015 Michael Lee <igvtee@gmail.com>
290 +#include <linux/module.h>
292 +#include <asm/mach-ralink/ralink_regs.h>
294 +#include "mtk_eth_soc.h"
295 +#include "mdio_rt2880.h"
297 +#define RT2880_RESET_FE BIT(18)
299 +static void rt2880_init_data(struct fe_soc_data *data,
300 + struct net_device *netdev)
302 + struct fe_priv *priv = netdev_priv(netdev);
304 + priv->flags = FE_FLAG_PADDING_64B | FE_FLAG_PADDING_BUG |
305 + FE_FLAG_JUMBO_FRAME | FE_FLAG_CALIBRATE_CLK;
306 + netdev->hw_features = NETIF_F_SG | NETIF_F_HW_VLAN_CTAG_TX;
307 + /* this should work according to the datasheet but actually does not*/
308 + /* netdev->hw_features |= NETIF_F_IP_CSUM | NETIF_F_RXCSUM; */
311 +void rt2880_fe_reset(void)
313 + fe_reset(RT2880_RESET_FE);
316 +static int rt2880_fwd_config(struct fe_priv *priv)
320 + ret = fe_set_clock_cycle(priv);
324 + fe_fwd_config(priv);
325 + fe_w32(FE_PSE_FQFC_CFG_INIT, FE_PSE_FQ_CFG);
326 + fe_csum_config(priv);
331 +struct fe_soc_data rt2880_data = {
332 + .init_data = rt2880_init_data,
333 + .reset_fe = rt2880_fe_reset,
334 + .fwd_config = rt2880_fwd_config,
335 + .pdma_glo_cfg = FE_PDMA_SIZE_8DWORDS,
336 + .checksum_bit = RX_DMA_L4VALID,
337 + .rx_int = FE_RX_DONE_INT,
338 + .tx_int = FE_TX_DONE_INT,
339 + .status_int = FE_CNT_GDM_AF,
340 + .mdio_read = rt2880_mdio_read,
341 + .mdio_write = rt2880_mdio_write,
342 + .mdio_adjust_link = rt2880_mdio_link_adjust,
343 + .port_init = rt2880_port_init,
346 +const struct of_device_id of_fe_match[] = {
347 + { .compatible = "ralink,rt2880-eth", .data = &rt2880_data },
351 +MODULE_DEVICE_TABLE(of, of_fe_match);