1 From 107ff718dad1c8f6abbf6247d6796a4535b71276 Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Mon, 14 Dec 2015 23:50:53 +0100
4 Subject: [PATCH 509/513] net-next: mediatek: add support for mt7621
6 Add support for SoCs from the mt7620 family. This include mt7620 and mt7621.
7 These all have one dedicated external gbit port and a builtin 5 port 100mbit
8 switch. Additionally one of the 5 switch ports can be changed to become an
9 additional gbit port that we can attach a phy to. This patch includes
10 rudimentary code to power up the switch. There are a lot of magic values
11 that get written to the switch and the internal phys. These values come
12 straight from the SDK driver.
14 Signed-off-by: John Crispin <blogic@openwrt.org>
15 Signed-off-by: Felix Fietkau <nbd@openwrt.org>
16 Signed-off-by: Michael Lee <igvtee@gmail.com>
18 drivers/net/ethernet/mediatek/soc_mt7621.c | 186 ++++++++++++++++++++++++++++
19 1 file changed, 186 insertions(+)
20 create mode 100644 drivers/net/ethernet/mediatek/soc_mt7621.c
23 +++ b/drivers/net/ethernet/mediatek/soc_mt7621.c
25 +/* This program is free software; you can redistribute it and/or modify
26 + * it under the terms of the GNU General Public License as published by
27 + * the Free Software Foundation; version 2 of the License
29 + * This program is distributed in the hope that it will be useful,
30 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
31 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
32 + * GNU General Public License for more details.
34 + * Copyright (C) 2009-2015 John Crispin <blogic@openwrt.org>
35 + * Copyright (C) 2009-2015 Felix Fietkau <nbd@openwrt.org>
36 + * Copyright (C) 2013-2015 Michael Lee <igvtee@gmail.com>
39 +#include <linux/module.h>
40 +#include <linux/platform_device.h>
41 +#include <linux/if_vlan.h>
42 +#include <linux/of_net.h>
44 +#include <asm/mach-ralink/ralink_regs.h>
46 +#include "mtk_eth_soc.h"
47 +#include "gsw_mt7620.h"
51 +#define MT7620A_CDMA_CSG_CFG 0x400
52 +#define MT7621_CDMP_IG_CTRL (MT7620A_CDMA_CSG_CFG + 0x00)
53 +#define MT7621_CDMP_EG_CTRL (MT7620A_CDMA_CSG_CFG + 0x04)
54 +#define MT7621_RESET_FE BIT(6)
55 +#define MT7621_L4_VALID BIT(24)
57 +#define MT7621_TX_DMA_UDF BIT(19)
58 +#define MT7621_TX_DMA_FPORT BIT(25)
60 +#define CDMA_ICS_EN BIT(2)
61 +#define CDMA_UCS_EN BIT(1)
62 +#define CDMA_TCS_EN BIT(0)
64 +#define GDMA_ICS_EN BIT(22)
65 +#define GDMA_TCS_EN BIT(21)
66 +#define GDMA_UCS_EN BIT(20)
68 +/* frame engine counters */
69 +#define MT7621_REG_MIB_OFFSET 0x2000
70 +#define MT7621_PPE_AC_BCNT0 (MT7621_REG_MIB_OFFSET + 0x00)
71 +#define MT7621_GDM1_TX_GBCNT (MT7621_REG_MIB_OFFSET + 0x400)
72 +#define MT7621_GDM2_TX_GBCNT (MT7621_GDM1_TX_GBCNT + 0x40)
74 +#define GSW_REG_GDMA1_MAC_ADRL 0x508
75 +#define GSW_REG_GDMA1_MAC_ADRH 0x50C
77 +#define MT7621_FE_RST_GL (FE_FE_OFFSET + 0x04)
78 +#define MT7620_FE_INT_STATUS2 (FE_FE_OFFSET + 0x08)
80 +/* FE_INT_STATUS reg on mt7620 define CNT_GDM1_AF at BIT(29)
81 + * but after test it should be BIT(13).
83 +#define MT7620_FE_GDM1_AF BIT(13)
84 +#define MT7621_FE_GDM1_AF BIT(28)
85 +#define MT7621_FE_GDM2_AF BIT(29)
87 +static const u16 mt7621_reg_table[FE_REG_COUNT] = {
88 + [FE_REG_PDMA_GLO_CFG] = RT5350_PDMA_GLO_CFG,
89 + [FE_REG_PDMA_RST_CFG] = RT5350_PDMA_RST_CFG,
90 + [FE_REG_DLY_INT_CFG] = RT5350_DLY_INT_CFG,
91 + [FE_REG_TX_BASE_PTR0] = RT5350_TX_BASE_PTR0,
92 + [FE_REG_TX_MAX_CNT0] = RT5350_TX_MAX_CNT0,
93 + [FE_REG_TX_CTX_IDX0] = RT5350_TX_CTX_IDX0,
94 + [FE_REG_TX_DTX_IDX0] = RT5350_TX_DTX_IDX0,
95 + [FE_REG_RX_BASE_PTR0] = RT5350_RX_BASE_PTR0,
96 + [FE_REG_RX_MAX_CNT0] = RT5350_RX_MAX_CNT0,
97 + [FE_REG_RX_CALC_IDX0] = RT5350_RX_CALC_IDX0,
98 + [FE_REG_RX_DRX_IDX0] = RT5350_RX_DRX_IDX0,
99 + [FE_REG_FE_INT_ENABLE] = RT5350_FE_INT_ENABLE,
100 + [FE_REG_FE_INT_STATUS] = RT5350_FE_INT_STATUS,
101 + [FE_REG_FE_DMA_VID_BASE] = 0,
102 + [FE_REG_FE_COUNTER_BASE] = MT7621_GDM1_TX_GBCNT,
103 + [FE_REG_FE_RST_GL] = MT7621_FE_RST_GL,
104 + [FE_REG_FE_INT_STATUS2] = MT7620_FE_INT_STATUS2,
107 +static int mt7621_gsw_config(struct fe_priv *priv)
109 + if (priv->mii_bus && priv->mii_bus->phy_map[0x1f])
110 + mt7530_probe(priv->device, NULL, priv->mii_bus, 1);
115 +static void mt7621_fe_reset(void)
117 + fe_reset(MT7621_RESET_FE);
120 +static void mt7621_rxcsum_config(bool enable)
123 + fe_w32(fe_r32(MT7620A_GDMA1_FWD_CFG) | (GDMA_ICS_EN |
124 + GDMA_TCS_EN | GDMA_UCS_EN),
125 + MT7620A_GDMA1_FWD_CFG);
127 + fe_w32(fe_r32(MT7620A_GDMA1_FWD_CFG) & ~(GDMA_ICS_EN |
128 + GDMA_TCS_EN | GDMA_UCS_EN),
129 + MT7620A_GDMA1_FWD_CFG);
132 +static void mt7621_rxvlan_config(bool enable)
135 + fe_w32(1, MT7621_CDMP_EG_CTRL);
137 + fe_w32(0, MT7621_CDMP_EG_CTRL);
140 +static int mt7621_fwd_config(struct fe_priv *priv)
142 + struct net_device *dev = priv_netdev(priv);
144 + fe_w32(fe_r32(MT7620A_GDMA1_FWD_CFG) & ~0xffff,
145 + MT7620A_GDMA1_FWD_CFG);
147 + /* mt7621 doesn't have txcsum config */
148 + mt7621_rxcsum_config((dev->features & NETIF_F_RXCSUM));
149 + mt7621_rxvlan_config((dev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
150 + (priv->flags & FE_FLAG_RX_VLAN_CTAG));
155 +static void mt7621_tx_dma(struct fe_tx_dma *txd)
157 + txd->txd4 = MT7621_TX_DMA_FPORT;
160 +static void mt7621_init_data(struct fe_soc_data *data,
161 + struct net_device *netdev)
163 + struct fe_priv *priv = netdev_priv(netdev);
165 + priv->flags = FE_FLAG_PADDING_64B | FE_FLAG_RX_2B_OFFSET |
166 + FE_FLAG_RX_SG_DMA | FE_FLAG_NAPI_WEIGHT |
167 + FE_FLAG_HAS_SWITCH;
169 + netdev->hw_features = NETIF_F_IP_CSUM | NETIF_F_RXCSUM |
170 + NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_SG | NETIF_F_TSO |
171 + NETIF_F_TSO6 | NETIF_F_IPV6_CSUM;
174 +static void mt7621_set_mac(struct fe_priv *priv, unsigned char *mac)
176 + unsigned long flags;
178 + spin_lock_irqsave(&priv->page_lock, flags);
179 + fe_w32((mac[0] << 8) | mac[1], GSW_REG_GDMA1_MAC_ADRH);
180 + fe_w32((mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5],
181 + GSW_REG_GDMA1_MAC_ADRL);
182 + spin_unlock_irqrestore(&priv->page_lock, flags);
185 +static struct fe_soc_data mt7621_data = {
186 + .init_data = mt7621_init_data,
187 + .reset_fe = mt7621_fe_reset,
188 + .set_mac = mt7621_set_mac,
189 + .fwd_config = mt7621_fwd_config,
190 + .tx_dma = mt7621_tx_dma,
191 + .switch_init = mtk_gsw_init,
192 + .switch_config = mt7621_gsw_config,
193 + .reg_table = mt7621_reg_table,
194 + .pdma_glo_cfg = FE_PDMA_SIZE_16DWORDS,
195 + .rx_int = RT5350_RX_DONE_INT,
196 + .tx_int = RT5350_TX_DONE_INT,
197 + .status_int = (MT7621_FE_GDM1_AF | MT7621_FE_GDM2_AF),
198 + .checksum_bit = MT7621_L4_VALID,
199 + .has_carrier = mt7620_has_carrier,
200 + .mdio_read = mt7620_mdio_read,
201 + .mdio_write = mt7620_mdio_write,
202 + .mdio_adjust_link = mt7620_mdio_link_adjust,
205 +const struct of_device_id of_fe_match[] = {
206 + { .compatible = "mediatek,mt7621-eth", .data = &mt7621_data },
210 +MODULE_DEVICE_TABLE(of, of_fe_match);