1 From cf5a08f1f16913da8bb24a96afaa2969b29d0827 Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Mon, 14 Dec 2015 22:25:57 +0100
4 Subject: [PATCH 513/513] net: mediatek: add swconfig driver for gsw_mt762x
6 Signed-off-by: John Crispin <blogic@openwrt.org>
8 drivers/net/ethernet/mediatek/Makefile | 4 +-
9 drivers/net/ethernet/mediatek/gsw_mt7620.c | 3 +
10 drivers/net/ethernet/mediatek/gsw_mt7620.h | 3 +
11 drivers/net/ethernet/mediatek/mt7530.c | 884 ++++++++++++++++++++++++++++
12 drivers/net/ethernet/mediatek/mt7530.h | 186 ++++++
13 drivers/net/ethernet/mediatek/mtk_eth_soc.c | 9 +-
14 drivers/net/ethernet/mediatek/mtk_eth_soc.h | 1 +
15 drivers/net/ethernet/mediatek/soc_mt7620.c | 1 +
16 8 files changed, 1087 insertions(+), 4 deletions(-)
17 create mode 100644 drivers/net/ethernet/mediatek/mt7530.c
18 create mode 100644 drivers/net/ethernet/mediatek/mt7530.h
20 --- a/drivers/net/ethernet/mediatek/Makefile
21 +++ b/drivers/net/ethernet/mediatek/Makefile
22 @@ -15,6 +15,6 @@ mtk-eth-soc-$(CONFIG_NET_MEDIATEK_MT7620
23 mtk-eth-soc-$(CONFIG_NET_MEDIATEK_MT7621) += soc_mt7621.o
25 obj-$(CONFIG_NET_MEDIATEK_ESW_RT3050) += esw_rt3050.o
26 -obj-$(CONFIG_NET_MEDIATEK_GSW_MT7620) += gsw_mt7620.o
27 -obj-$(CONFIG_NET_MEDIATEK_GSW_MT7621) += gsw_mt7621.o
28 +obj-$(CONFIG_NET_MEDIATEK_GSW_MT7620) += gsw_mt7620.o mt7530.o
29 +obj-$(CONFIG_NET_MEDIATEK_GSW_MT7621) += gsw_mt7621.o mt7530.o
30 obj-$(CONFIG_NET_MEDIATEK_SOC) += mtk-eth-soc.o
31 --- a/drivers/net/ethernet/mediatek/gsw_mt7620.c
32 +++ b/drivers/net/ethernet/mediatek/gsw_mt7620.c
33 @@ -67,6 +67,9 @@ static void mt7620_hw_init(struct mt7620
34 rt_sysc_w32(rt_sysc_r32(SYSC_REG_CFG1) | BIT(8), SYSC_REG_CFG1);
35 mtk_switch_w32(gsw, mtk_switch_r32(gsw, GSW_REG_CKGCR) & ~(0x3 << 4), GSW_REG_CKGCR);
37 + /* Enable MIB stats */
38 + mtk_switch_w32(gsw, mtk_switch_r32(gsw, GSW_REG_MIB_CNT_EN) | (1 << 1), GSW_REG_MIB_CNT_EN);
40 if (of_property_read_bool(np, "mediatek,mt7530")) {
43 --- a/drivers/net/ethernet/mediatek/gsw_mt7620.h
44 +++ b/drivers/net/ethernet/mediatek/gsw_mt7620.h
46 #define GSW_MDIO_ADDR_SHIFT 20
47 #define GSW_MDIO_REG_SHIFT 25
49 +#define GSW_REG_MIB_CNT_EN 0x4000
51 #define GSW_REG_PORT_PMCR(x) (0x3000 + (x * 0x100))
52 #define GSW_REG_PORT_STATUS(x) (0x3008 + (x * 0x100))
53 #define GSW_REG_SMACCR0 0x3fE4
55 #define PHY_PRE_EN BIT(30)
56 #define PMY_MDC_CONF(_x) ((_x & 0x3f) << 24)
60 /* Global attributes. */
63 +++ b/drivers/net/ethernet/mediatek/mt7530.c
66 + * This program is free software; you can redistribute it and/or
67 + * modify it under the terms of the GNU General Public License
68 + * as published by the Free Software Foundation; either version 2
69 + * of the License, or (at your option) any later version.
71 + * This program is distributed in the hope that it will be useful,
72 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
73 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
74 + * GNU General Public License for more details.
76 + * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
77 + * Copyright (C) 2016 Vitaly Chekryzhev <13hakta@gmail.com>
80 +#include <linux/if.h>
81 +#include <linux/module.h>
82 +#include <linux/init.h>
83 +#include <linux/list.h>
84 +#include <linux/if_ether.h>
85 +#include <linux/skbuff.h>
86 +#include <linux/netdevice.h>
87 +#include <linux/netlink.h>
88 +#include <linux/bitops.h>
89 +#include <net/genetlink.h>
90 +#include <linux/switch.h>
91 +#include <linux/delay.h>
92 +#include <linux/phy.h>
93 +#include <linux/netdevice.h>
94 +#include <linux/etherdevice.h>
95 +#include <linux/lockdep.h>
96 +#include <linux/workqueue.h>
97 +#include <linux/of_device.h>
101 +#define MT7530_CPU_PORT 6
102 +#define MT7530_NUM_PORTS 8
103 +#define MT7530_NUM_VLANS 16
104 +#define MT7530_MAX_VID 4095
105 +#define MT7530_MIN_VID 0
108 +#define REG_ESW_VLAN_VTCR 0x90
109 +#define REG_ESW_VLAN_VAWD1 0x94
110 +#define REG_ESW_VLAN_VAWD2 0x98
111 +#define REG_ESW_VLAN_VTIM(x) (0x100 + 4 * ((x) / 2))
113 +#define REG_ESW_VLAN_VAWD1_IVL_MAC BIT(30)
114 +#define REG_ESW_VLAN_VAWD1_VTAG_EN BIT(28)
115 +#define REG_ESW_VLAN_VAWD1_VALID BIT(0)
117 +/* vlan egress mode */
119 + ETAG_CTRL_UNTAG = 0,
121 + ETAG_CTRL_SWAP = 1,
122 + ETAG_CTRL_STACK = 3,
125 +#define REG_ESW_PORT_PCR(x) (0x2004 | ((x) << 8))
126 +#define REG_ESW_PORT_PVC(x) (0x2010 | ((x) << 8))
127 +#define REG_ESW_PORT_PPBV1(x) (0x2014 | ((x) << 8))
129 +#define REG_HWTRAP 0x7804
131 +#define MIB_DESC(_s , _o, _n) \
138 +struct mt7xxx_mib_desc {
140 + unsigned int offset;
144 +static const struct mt7xxx_mib_desc mt7620_mibs[] = {
145 + MIB_DESC(1, MT7620_MIB_STATS_PPE_AC_BCNT0, "PPE_AC_BCNT0"),
146 + MIB_DESC(1, MT7620_MIB_STATS_PPE_AC_PCNT0, "PPE_AC_PCNT0"),
147 + MIB_DESC(1, MT7620_MIB_STATS_PPE_AC_BCNT63, "PPE_AC_BCNT63"),
148 + MIB_DESC(1, MT7620_MIB_STATS_PPE_AC_PCNT63, "PPE_AC_PCNT63"),
149 + MIB_DESC(1, MT7620_MIB_STATS_PPE_MTR_CNT0, "PPE_MTR_CNT0"),
150 + MIB_DESC(1, MT7620_MIB_STATS_PPE_MTR_CNT63, "PPE_MTR_CNT63"),
151 + MIB_DESC(1, MT7620_MIB_STATS_GDM1_TX_GBCNT, "GDM1_TX_GBCNT"),
152 + MIB_DESC(1, MT7620_MIB_STATS_GDM1_TX_GPCNT, "GDM1_TX_GPCNT"),
153 + MIB_DESC(1, MT7620_MIB_STATS_GDM1_TX_SKIPCNT, "GDM1_TX_SKIPCNT"),
154 + MIB_DESC(1, MT7620_MIB_STATS_GDM1_TX_COLCNT, "GDM1_TX_COLCNT"),
155 + MIB_DESC(1, MT7620_MIB_STATS_GDM1_RX_GBCNT1, "GDM1_RX_GBCNT1"),
156 + MIB_DESC(1, MT7620_MIB_STATS_GDM1_RX_GPCNT1, "GDM1_RX_GPCNT1"),
157 + MIB_DESC(1, MT7620_MIB_STATS_GDM1_RX_OERCNT, "GDM1_RX_OERCNT"),
158 + MIB_DESC(1, MT7620_MIB_STATS_GDM1_RX_FERCNT, "GDM1_RX_FERCNT"),
159 + MIB_DESC(1, MT7620_MIB_STATS_GDM1_RX_SERCNT, "GDM1_RX_SERCNT"),
160 + MIB_DESC(1, MT7620_MIB_STATS_GDM1_RX_LERCNT, "GDM1_RX_LERCNT"),
161 + MIB_DESC(1, MT7620_MIB_STATS_GDM1_RX_CERCNT, "GDM1_RX_CERCNT"),
162 + MIB_DESC(1, MT7620_MIB_STATS_GDM1_RX_FCCNT, "GDM1_RX_FCCNT"),
163 + MIB_DESC(1, MT7620_MIB_STATS_GDM2_TX_GBCNT, "GDM2_TX_GBCNT"),
164 + MIB_DESC(1, MT7620_MIB_STATS_GDM2_TX_GPCNT, "GDM2_TX_GPCNT"),
165 + MIB_DESC(1, MT7620_MIB_STATS_GDM2_TX_SKIPCNT, "GDM2_TX_SKIPCNT"),
166 + MIB_DESC(1, MT7620_MIB_STATS_GDM2_TX_COLCNT, "GDM2_TX_COLCNT"),
167 + MIB_DESC(1, MT7620_MIB_STATS_GDM2_RX_GBCNT, "GDM2_RX_GBCNT"),
168 + MIB_DESC(1, MT7620_MIB_STATS_GDM2_RX_GPCNT, "GDM2_RX_GPCNT"),
169 + MIB_DESC(1, MT7620_MIB_STATS_GDM2_RX_OERCNT, "GDM2_RX_OERCNT"),
170 + MIB_DESC(1, MT7620_MIB_STATS_GDM2_RX_FERCNT, "GDM2_RX_FERCNT"),
171 + MIB_DESC(1, MT7620_MIB_STATS_GDM2_RX_SERCNT, "GDM2_RX_SERCNT"),
172 + MIB_DESC(1, MT7620_MIB_STATS_GDM2_RX_LERCNT, "GDM2_RX_LERCNT"),
173 + MIB_DESC(1, MT7620_MIB_STATS_GDM2_RX_CERCNT, "GDM2_RX_CERCNT"),
174 + MIB_DESC(1, MT7620_MIB_STATS_GDM2_RX_FCCNT, "GDM2_RX_FCCNT")
177 +static const struct mt7xxx_mib_desc mt7620_port_mibs[] = {
178 + MIB_DESC(1, MT7620_MIB_STATS_PORT_TGPCN, "TxGPC"),
179 + MIB_DESC(1, MT7620_MIB_STATS_PORT_TBOCN, "TxBOC"),
180 + MIB_DESC(1, MT7620_MIB_STATS_PORT_TGOCN, "TxGOC"),
181 + MIB_DESC(1, MT7620_MIB_STATS_PORT_TEPCN, "TxEPC"),
182 + MIB_DESC(1, MT7620_MIB_STATS_PORT_RGPCN, "RxGPC"),
183 + MIB_DESC(1, MT7620_MIB_STATS_PORT_RBOCN, "RxBOC"),
184 + MIB_DESC(1, MT7620_MIB_STATS_PORT_RGOCN, "RxGOC"),
185 + MIB_DESC(1, MT7620_MIB_STATS_PORT_REPC1N, "RxEPC1"),
186 + MIB_DESC(1, MT7620_MIB_STATS_PORT_REPC2N, "RxEPC2")
189 +static const struct mt7xxx_mib_desc mt7621_mibs[] = {
190 + MIB_DESC(1, MT7621_STATS_TDPC, "TxDrop"),
191 + MIB_DESC(1, MT7621_STATS_TCRC, "TxCRC"),
192 + MIB_DESC(1, MT7621_STATS_TUPC, "TxUni"),
193 + MIB_DESC(1, MT7621_STATS_TMPC, "TxMulti"),
194 + MIB_DESC(1, MT7621_STATS_TBPC, "TxBroad"),
195 + MIB_DESC(1, MT7621_STATS_TCEC, "TxCollision"),
196 + MIB_DESC(1, MT7621_STATS_TSCEC, "TxSingleCol"),
197 + MIB_DESC(1, MT7621_STATS_TMCEC, "TxMultiCol"),
198 + MIB_DESC(1, MT7621_STATS_TDEC, "TxDefer"),
199 + MIB_DESC(1, MT7621_STATS_TLCEC, "TxLateCol"),
200 + MIB_DESC(1, MT7621_STATS_TXCEC, "TxExcCol"),
201 + MIB_DESC(1, MT7621_STATS_TPPC, "TxPause"),
202 + MIB_DESC(1, MT7621_STATS_TL64PC, "Tx64Byte"),
203 + MIB_DESC(1, MT7621_STATS_TL65PC, "Tx65Byte"),
204 + MIB_DESC(1, MT7621_STATS_TL128PC, "Tx128Byte"),
205 + MIB_DESC(1, MT7621_STATS_TL256PC, "Tx256Byte"),
206 + MIB_DESC(1, MT7621_STATS_TL512PC, "Tx512Byte"),
207 + MIB_DESC(1, MT7621_STATS_TL1024PC, "Tx1024Byte"),
208 + MIB_DESC(2, MT7621_STATS_TOC, "TxByte"),
209 + MIB_DESC(1, MT7621_STATS_RDPC, "RxDrop"),
210 + MIB_DESC(1, MT7621_STATS_RFPC, "RxFiltered"),
211 + MIB_DESC(1, MT7621_STATS_RUPC, "RxUni"),
212 + MIB_DESC(1, MT7621_STATS_RMPC, "RxMulti"),
213 + MIB_DESC(1, MT7621_STATS_RBPC, "RxBroad"),
214 + MIB_DESC(1, MT7621_STATS_RAEPC, "RxAlignErr"),
215 + MIB_DESC(1, MT7621_STATS_RCEPC, "RxCRC"),
216 + MIB_DESC(1, MT7621_STATS_RUSPC, "RxUnderSize"),
217 + MIB_DESC(1, MT7621_STATS_RFEPC, "RxFragment"),
218 + MIB_DESC(1, MT7621_STATS_ROSPC, "RxOverSize"),
219 + MIB_DESC(1, MT7621_STATS_RJEPC, "RxJabber"),
220 + MIB_DESC(1, MT7621_STATS_RPPC, "RxPause"),
221 + MIB_DESC(1, MT7621_STATS_RL64PC, "Rx64Byte"),
222 + MIB_DESC(1, MT7621_STATS_RL65PC, "Rx65Byte"),
223 + MIB_DESC(1, MT7621_STATS_RL128PC, "Rx128Byte"),
224 + MIB_DESC(1, MT7621_STATS_RL256PC, "Rx256Byte"),
225 + MIB_DESC(1, MT7621_STATS_RL512PC, "Rx512Byte"),
226 + MIB_DESC(1, MT7621_STATS_RL1024PC, "Rx1024Byte"),
227 + MIB_DESC(2, MT7621_STATS_ROC, "RxByte"),
228 + MIB_DESC(1, MT7621_STATS_RDPC_CTRL, "RxCtrlDrop"),
229 + MIB_DESC(1, MT7621_STATS_RDPC_ING, "RxIngDrop"),
230 + MIB_DESC(1, MT7621_STATS_RDPC_ARL, "RxARLDrop")
234 + /* Global attributes. */
235 + MT7530_ATTR_ENABLE_VLAN,
238 +struct mt7530_port_entry {
242 +struct mt7530_vlan_entry {
248 +struct mt7530_priv {
249 + void __iomem *base;
250 + struct mii_bus *bus;
251 + struct switch_dev swdev;
253 + bool global_vlan_enable;
254 + struct mt7530_vlan_entry vlan_entries[MT7530_NUM_VLANS];
255 + struct mt7530_port_entry port_entries[MT7530_NUM_PORTS];
258 +struct mt7530_mapping {
260 + u16 pvids[MT7530_NUM_PORTS];
261 + u8 members[MT7530_NUM_VLANS];
262 + u8 etags[MT7530_NUM_VLANS];
263 + u16 vids[MT7530_NUM_VLANS];
264 +} mt7530_defaults[] = {
267 + .pvids = { 1, 1, 1, 1, 2, 1, 1 },
268 + .members = { 0, 0x6f, 0x50 },
269 + .etags = { 0, 0x40, 0x40 },
270 + .vids = { 0, 1, 2 },
273 + .pvids = { 2, 1, 1, 1, 1, 1, 1 },
274 + .members = { 0, 0x7e, 0x41 },
275 + .etags = { 0, 0x40, 0x40 },
276 + .vids = { 0, 1, 2 },
280 +struct mt7530_mapping*
281 +mt7530_find_mapping(struct device_node *np)
286 + if (of_property_read_string(np, "mediatek,portmap", &map))
289 + for (i = 0; i < ARRAY_SIZE(mt7530_defaults); i++)
290 + if (!strcmp(map, mt7530_defaults[i].name))
291 + return &mt7530_defaults[i];
297 +mt7530_apply_mapping(struct mt7530_priv *mt7530, struct mt7530_mapping *map)
301 + for (i = 0; i < MT7530_NUM_PORTS; i++)
302 + mt7530->port_entries[i].pvid = map->pvids[i];
304 + for (i = 0; i < MT7530_NUM_VLANS; i++) {
305 + mt7530->vlan_entries[i].member = map->members[i];
306 + mt7530->vlan_entries[i].etags = map->etags[i];
307 + mt7530->vlan_entries[i].vid = map->vids[i];
312 +mt7530_reset_switch(struct switch_dev *dev)
314 + struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
317 + memset(priv->port_entries, 0, sizeof(priv->port_entries));
318 + memset(priv->vlan_entries, 0, sizeof(priv->vlan_entries));
320 + /* set default vid of each vlan to the same number of vlan, so the vid
321 + * won't need be set explicitly.
323 + for (i = 0; i < MT7530_NUM_VLANS; i++) {
324 + priv->vlan_entries[i].vid = i;
331 +mt7530_get_vlan_enable(struct switch_dev *dev,
332 + const struct switch_attr *attr,
333 + struct switch_val *val)
335 + struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
337 + val->value.i = priv->global_vlan_enable;
343 +mt7530_set_vlan_enable(struct switch_dev *dev,
344 + const struct switch_attr *attr,
345 + struct switch_val *val)
347 + struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
349 + priv->global_vlan_enable = val->value.i != 0;
355 +mt7530_r32(struct mt7530_priv *priv, u32 reg)
361 + mdiobus_write(priv->bus, 0x1f, 0x1f, (reg >> 6) & 0x3ff);
362 + low = mdiobus_read(priv->bus, 0x1f, (reg >> 2) & 0xf);
363 + high = mdiobus_read(priv->bus, 0x1f, 0x10);
365 + return (high << 16) | (low & 0xffff);
368 + val = ioread32(priv->base + reg);
369 + pr_debug("MT7530 MDIO Read [%04x]=%08x\n", reg, val);
375 +mt7530_w32(struct mt7530_priv *priv, u32 reg, u32 val)
378 + mdiobus_write(priv->bus, 0x1f, 0x1f, (reg >> 6) & 0x3ff);
379 + mdiobus_write(priv->bus, 0x1f, (reg >> 2) & 0xf, val & 0xffff);
380 + mdiobus_write(priv->bus, 0x1f, 0x10, val >> 16);
384 + pr_debug("MT7530 MDIO Write[%04x]=%08x\n", reg, val);
385 + iowrite32(val, priv->base + reg);
389 +mt7530_vtcr(struct mt7530_priv *priv, u32 cmd, u32 val)
393 + mt7530_w32(priv, REG_ESW_VLAN_VTCR, BIT(31) | (cmd << 12) | val);
395 + for (i = 0; i < 20; i++) {
396 + u32 val = mt7530_r32(priv, REG_ESW_VLAN_VTCR);
398 + if ((val & BIT(31)) == 0)
404 + printk("mt7530: vtcr timeout\n");
408 +mt7530_get_port_pvid(struct switch_dev *dev, int port, int *val)
410 + struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
412 + if (port >= MT7530_NUM_PORTS)
415 + *val = mt7530_r32(priv, REG_ESW_PORT_PPBV1(port));
422 +mt7530_set_port_pvid(struct switch_dev *dev, int port, int pvid)
424 + struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
426 + if (port >= MT7530_NUM_PORTS)
429 + if (pvid < MT7530_MIN_VID || pvid > MT7530_MAX_VID)
432 + priv->port_entries[port].pvid = pvid;
438 +mt7530_get_vlan_ports(struct switch_dev *dev, struct switch_val *val)
440 + struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
447 + if (val->port_vlan < 0 || val->port_vlan >= MT7530_NUM_VLANS)
450 + mt7530_vtcr(priv, 0, val->port_vlan);
452 + member = mt7530_r32(priv, REG_ESW_VLAN_VAWD1);
456 + etags = mt7530_r32(priv, REG_ESW_VLAN_VAWD2);
458 + for (i = 0; i < MT7530_NUM_PORTS; i++) {
459 + struct switch_port *p;
462 + if (!(member & BIT(i)))
465 + p = &val->value.ports[val->len++];
468 + etag = (etags >> (i * 2)) & 0x3;
470 + if (etag == ETAG_CTRL_TAG)
471 + p->flags |= BIT(SWITCH_PORT_FLAG_TAGGED);
472 + else if (etag != ETAG_CTRL_UNTAG)
473 + printk("vlan egress tag control neither untag nor tag.\n");
480 +mt7530_set_vlan_ports(struct switch_dev *dev, struct switch_val *val)
482 + struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
487 + if (val->port_vlan < 0 || val->port_vlan >= MT7530_NUM_VLANS ||
488 + val->len > MT7530_NUM_PORTS)
491 + for (i = 0; i < val->len; i++) {
492 + struct switch_port *p = &val->value.ports[i];
494 + if (p->id >= MT7530_NUM_PORTS)
497 + member |= BIT(p->id);
499 + if (p->flags & BIT(SWITCH_PORT_FLAG_TAGGED))
500 + etags |= BIT(p->id);
502 + priv->vlan_entries[val->port_vlan].member = member;
503 + priv->vlan_entries[val->port_vlan].etags = etags;
509 +mt7530_set_vid(struct switch_dev *dev, const struct switch_attr *attr,
510 + struct switch_val *val)
512 + struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
516 + vlan = val->port_vlan;
517 + vid = (u16)val->value.i;
519 + if (vlan < 0 || vlan >= MT7530_NUM_VLANS)
522 + if (vid < MT7530_MIN_VID || vid > MT7530_MAX_VID)
525 + priv->vlan_entries[vlan].vid = vid;
530 +mt7530_get_vid(struct switch_dev *dev, const struct switch_attr *attr,
531 + struct switch_val *val)
533 + struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
537 + vlan = val->port_vlan;
539 + vid = mt7530_r32(priv, REG_ESW_VLAN_VTIM(vlan));
544 + val->value.i = vid;
549 +mt7530_apply_config(struct switch_dev *dev)
551 + struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
556 + if (!priv->global_vlan_enable) {
557 + for (i = 0; i < MT7530_NUM_PORTS; i++)
558 + mt7530_w32(priv, REG_ESW_PORT_PCR(i), 0x00400000);
560 + mt7530_w32(priv, REG_ESW_PORT_PCR(MT7530_CPU_PORT), 0x00ff0000);
562 + for (i = 0; i < MT7530_NUM_PORTS; i++)
563 + mt7530_w32(priv, REG_ESW_PORT_PVC(i), 0x810000c0);
568 + /* set all ports as security mode */
569 + for (i = 0; i < MT7530_NUM_PORTS; i++)
570 + mt7530_w32(priv, REG_ESW_PORT_PCR(i), 0x00ff0003);
572 + /* check if a port is used in tag/untag vlan egress mode */
576 + for (i = 0; i < MT7530_NUM_VLANS; i++) {
577 + u8 member = priv->vlan_entries[i].member;
578 + u8 etags = priv->vlan_entries[i].etags;
583 + for (j = 0; j < MT7530_NUM_PORTS; j++) {
584 + if (!(member & BIT(j)))
587 + if (etags & BIT(j))
588 + tag_ports |= 1u << j;
590 + untag_ports |= 1u << j;
594 + /* set all untag-only ports as transparent and the rest as user port */
595 + for (i = 0; i < MT7530_NUM_PORTS; i++) {
596 + u32 pvc_mode = 0x81000000;
598 + if (untag_ports & BIT(i) && !(tag_ports & BIT(i)))
599 + pvc_mode = 0x810000c0;
601 + mt7530_w32(priv, REG_ESW_PORT_PVC(i), pvc_mode);
604 + for (i = 0; i < MT7530_NUM_VLANS; i++) {
605 + u16 vid = priv->vlan_entries[i].vid;
606 + u8 member = priv->vlan_entries[i].member;
607 + u8 etags = priv->vlan_entries[i].etags;
611 + val = mt7530_r32(priv, REG_ESW_VLAN_VTIM(i));
617 + val |= (vid << 12);
619 + mt7530_w32(priv, REG_ESW_VLAN_VTIM(i), val);
621 + /* vlan port membership */
623 + mt7530_w32(priv, REG_ESW_VLAN_VAWD1, REG_ESW_VLAN_VAWD1_IVL_MAC |
624 + REG_ESW_VLAN_VAWD1_VTAG_EN | (member << 16) |
625 + REG_ESW_VLAN_VAWD1_VALID);
627 + mt7530_w32(priv, REG_ESW_VLAN_VAWD1, 0);
631 + for (j = 0; j < MT7530_NUM_PORTS; j++) {
632 + if (etags & BIT(j))
633 + val |= ETAG_CTRL_TAG << (j * 2);
635 + val |= ETAG_CTRL_UNTAG << (j * 2);
637 + mt7530_w32(priv, REG_ESW_VLAN_VAWD2, val);
639 + /* write to vlan table */
640 + mt7530_vtcr(priv, 1, i);
643 + /* Port Default PVID */
644 + for (i = 0; i < MT7530_NUM_PORTS; i++) {
646 + val = mt7530_r32(priv, REG_ESW_PORT_PPBV1(i));
648 + val |= priv->port_entries[i].pvid;
649 + mt7530_w32(priv, REG_ESW_PORT_PPBV1(i), val);
656 +mt7530_get_port_link(struct switch_dev *dev, int port,
657 + struct switch_port_link *link)
659 + struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
662 + if (port < 0 || port >= MT7530_NUM_PORTS)
665 + pmsr = mt7530_r32(priv, 0x3008 + (0x100 * port));
667 + link->link = pmsr & 1;
668 + link->duplex = (pmsr >> 1) & 1;
669 + speed = (pmsr >> 2) & 3;
673 + link->speed = SWITCH_PORT_SPEED_10;
676 + link->speed = SWITCH_PORT_SPEED_100;
679 + case 3: /* forced gige speed can be 2 or 3 */
680 + link->speed = SWITCH_PORT_SPEED_1000;
683 + link->speed = SWITCH_PORT_SPEED_UNKNOWN;
690 +static u64 get_mib_counter(struct mt7530_priv *priv, int i, int port)
692 + unsigned int port_base;
695 + port_base = MT7621_MIB_COUNTER_BASE +
696 + MT7621_MIB_COUNTER_PORT_OFFSET * port;
698 + lo = mt7530_r32(priv, port_base + mt7621_mibs[i].offset);
699 + if (mt7621_mibs[i].size == 2) {
702 + hi = mt7530_r32(priv, port_base + mt7621_mibs[i].offset + 4);
709 +static int mt7621_sw_get_port_mib(struct switch_dev *dev,
710 + const struct switch_attr *attr,
711 + struct switch_val *val)
713 + static char buf[4096];
714 + struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
717 + if (val->port_vlan >= MT7530_NUM_PORTS)
720 + len += snprintf(buf + len, sizeof(buf) - len,
721 + "Port %d MIB counters\n", val->port_vlan);
723 + for (i = 0; i < ARRAY_SIZE(mt7621_mibs); ++i) {
725 + len += snprintf(buf + len, sizeof(buf) - len,
726 + "%-11s: ", mt7621_mibs[i].name);
727 + counter = get_mib_counter(priv, i, val->port_vlan);
728 + len += snprintf(buf + len, sizeof(buf) - len, "%llu\n",
732 + val->value.s = buf;
737 +static u64 get_mib_counter_7620(struct mt7530_priv *priv, int i)
739 + return mt7530_r32(priv, MT7620_MIB_COUNTER_BASE + mt7620_mibs[i].offset);
742 +static u64 get_mib_counter_port_7620(struct mt7530_priv *priv, int i, int port)
744 + return mt7530_r32(priv,
745 + MT7620_MIB_COUNTER_BASE_PORT +
746 + (MT7620_MIB_COUNTER_PORT_OFFSET * port) +
747 + mt7620_port_mibs[i].offset);
750 +static int mt7530_sw_get_mib(struct switch_dev *dev,
751 + const struct switch_attr *attr,
752 + struct switch_val *val)
754 + static char buf[4096];
755 + struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
758 + len += snprintf(buf + len, sizeof(buf) - len, "Switch MIB counters\n");
760 + for (i = 0; i < ARRAY_SIZE(mt7620_mibs); ++i) {
762 + len += snprintf(buf + len, sizeof(buf) - len,
763 + "%-11s: ", mt7620_mibs[i].name);
764 + counter = get_mib_counter_7620(priv, i);
765 + len += snprintf(buf + len, sizeof(buf) - len, "%llu\n",
769 + val->value.s = buf;
774 +static int mt7530_sw_get_port_mib(struct switch_dev *dev,
775 + const struct switch_attr *attr,
776 + struct switch_val *val)
778 + static char buf[4096];
779 + struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
782 + if (val->port_vlan >= MT7530_NUM_PORTS)
785 + len += snprintf(buf + len, sizeof(buf) - len,
786 + "Port %d MIB counters\n", val->port_vlan);
788 + for (i = 0; i < ARRAY_SIZE(mt7620_port_mibs); ++i) {
790 + len += snprintf(buf + len, sizeof(buf) - len,
791 + "%-11s: ", mt7620_port_mibs[i].name);
792 + counter = get_mib_counter_port_7620(priv, i, val->port_vlan);
793 + len += snprintf(buf + len, sizeof(buf) - len, "%llu\n",
797 + val->value.s = buf;
802 +static const struct switch_attr mt7530_global[] = {
804 + .type = SWITCH_TYPE_INT,
805 + .name = "enable_vlan",
806 + .description = "VLAN mode (1:enabled)",
808 + .id = MT7530_ATTR_ENABLE_VLAN,
809 + .get = mt7530_get_vlan_enable,
810 + .set = mt7530_set_vlan_enable,
812 + .type = SWITCH_TYPE_STRING,
814 + .description = "Get MIB counters for switch",
815 + .get = mt7530_sw_get_mib,
820 +static const struct switch_attr mt7621_port[] = {
822 + .type = SWITCH_TYPE_STRING,
824 + .description = "Get MIB counters for port",
825 + .get = mt7621_sw_get_port_mib,
830 +static const struct switch_attr mt7530_port[] = {
832 + .type = SWITCH_TYPE_STRING,
834 + .description = "Get MIB counters for port",
835 + .get = mt7530_sw_get_port_mib,
840 +static const struct switch_attr mt7530_vlan[] = {
842 + .type = SWITCH_TYPE_INT,
844 + .description = "VLAN ID (0-4094)",
845 + .set = mt7530_set_vid,
846 + .get = mt7530_get_vid,
851 +static const struct switch_dev_ops mt7621_ops = {
853 + .attr = mt7530_global,
854 + .n_attr = ARRAY_SIZE(mt7530_global),
857 + .attr = mt7621_port,
858 + .n_attr = ARRAY_SIZE(mt7621_port),
861 + .attr = mt7530_vlan,
862 + .n_attr = ARRAY_SIZE(mt7530_vlan),
864 + .get_vlan_ports = mt7530_get_vlan_ports,
865 + .set_vlan_ports = mt7530_set_vlan_ports,
866 + .get_port_pvid = mt7530_get_port_pvid,
867 + .set_port_pvid = mt7530_set_port_pvid,
868 + .get_port_link = mt7530_get_port_link,
869 + .apply_config = mt7530_apply_config,
870 + .reset_switch = mt7530_reset_switch,
873 +static const struct switch_dev_ops mt7530_ops = {
875 + .attr = mt7530_global,
876 + .n_attr = ARRAY_SIZE(mt7530_global),
879 + .attr = mt7530_port,
880 + .n_attr = ARRAY_SIZE(mt7530_port),
883 + .attr = mt7530_vlan,
884 + .n_attr = ARRAY_SIZE(mt7530_vlan),
886 + .get_vlan_ports = mt7530_get_vlan_ports,
887 + .set_vlan_ports = mt7530_set_vlan_ports,
888 + .get_port_pvid = mt7530_get_port_pvid,
889 + .set_port_pvid = mt7530_set_port_pvid,
890 + .get_port_link = mt7530_get_port_link,
891 + .apply_config = mt7530_apply_config,
892 + .reset_switch = mt7530_reset_switch,
896 +mt7530_probe(struct device *dev, void __iomem *base, struct mii_bus *bus, int vlan)
898 + struct switch_dev *swdev;
899 + struct mt7530_priv *mt7530;
900 + struct mt7530_mapping *map;
903 + mt7530 = devm_kzalloc(dev, sizeof(struct mt7530_priv), GFP_KERNEL);
907 + mt7530->base = base;
909 + mt7530->global_vlan_enable = vlan;
911 + swdev = &mt7530->swdev;
913 + swdev->alias = "mt7530";
914 + swdev->name = "mt7530";
915 + } else if (IS_ENABLED(CONFIG_SOC_MT7621)) {
916 + swdev->alias = "mt7621";
917 + swdev->name = "mt7621";
919 + swdev->alias = "mt7620";
920 + swdev->name = "mt7620";
922 + swdev->cpu_port = MT7530_CPU_PORT;
923 + swdev->ports = MT7530_NUM_PORTS;
924 + swdev->vlans = MT7530_NUM_VLANS;
925 + if (IS_ENABLED(CONFIG_SOC_MT7621))
926 + swdev->ops = &mt7621_ops;
928 + swdev->ops = &mt7530_ops;
930 + ret = register_switch(swdev, NULL);
932 + dev_err(dev, "failed to register mt7530\n");
937 + map = mt7530_find_mapping(dev->of_node);
939 + mt7530_apply_mapping(mt7530, map);
940 + mt7530_apply_config(swdev);
943 + if (!IS_ENABLED(CONFIG_SOC_MT7621) && bus && mt7530_r32(mt7530, REG_HWTRAP) != 0x1117edf) {
944 + dev_info(dev, "fixing up MHWTRAP register - bootloader probably played with it\n");
945 + mt7530_w32(mt7530, REG_HWTRAP, 0x1117edf);
947 + dev_info(dev, "loaded %s driver\n", swdev->name);
952 +++ b/drivers/net/ethernet/mediatek/mt7530.h
955 + * This program is free software; you can redistribute it and/or
956 + * modify it under the terms of the GNU General Public License
957 + * as published by the Free Software Foundation; either version 2
958 + * of the License, or (at your option) any later version.
960 + * This program is distributed in the hope that it will be useful,
961 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
962 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
963 + * GNU General Public License for more details.
965 + * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
966 + * Copyright (C) 2016 Vitaly Chekryzhev <13hakta@gmail.com>
972 +#define MT7620_MIB_COUNTER_BASE_PORT 0x4000
973 +#define MT7620_MIB_COUNTER_PORT_OFFSET 0x100
974 +#define MT7620_MIB_COUNTER_BASE 0x1010
976 +/* PPE Accounting Group #0 Byte Counter */
977 +#define MT7620_MIB_STATS_PPE_AC_BCNT0 0x000
979 +/* PPE Accounting Group #0 Packet Counter */
980 +#define MT7620_MIB_STATS_PPE_AC_PCNT0 0x004
982 +/* PPE Accounting Group #63 Byte Counter */
983 +#define MT7620_MIB_STATS_PPE_AC_BCNT63 0x1F8
985 +/* PPE Accounting Group #63 Packet Counter */
986 +#define MT7620_MIB_STATS_PPE_AC_PCNT63 0x1FC
988 +/* PPE Meter Group #0 */
989 +#define MT7620_MIB_STATS_PPE_MTR_CNT0 0x200
991 +/* PPE Meter Group #63 */
992 +#define MT7620_MIB_STATS_PPE_MTR_CNT63 0x2FC
994 +/* Transmit good byte count for CPU GDM */
995 +#define MT7620_MIB_STATS_GDM1_TX_GBCNT 0x300
997 +/* Transmit good packet count for CPU GDM (exclude flow control frames) */
998 +#define MT7620_MIB_STATS_GDM1_TX_GPCNT 0x304
1000 +/* Transmit abort count for CPU GDM */
1001 +#define MT7620_MIB_STATS_GDM1_TX_SKIPCNT 0x308
1003 +/* Transmit collision count for CPU GDM */
1004 +#define MT7620_MIB_STATS_GDM1_TX_COLCNT 0x30C
1006 +/* Received good byte count for CPU GDM */
1007 +#define MT7620_MIB_STATS_GDM1_RX_GBCNT1 0x320
1009 +/* Received good packet count for CPU GDM (exclude flow control frame) */
1010 +#define MT7620_MIB_STATS_GDM1_RX_GPCNT1 0x324
1012 +/* Received overflow error packet count for CPU GDM */
1013 +#define MT7620_MIB_STATS_GDM1_RX_OERCNT 0x328
1015 +/* Received FCS error packet count for CPU GDM */
1016 +#define MT7620_MIB_STATS_GDM1_RX_FERCNT 0x32C
1018 +/* Received too short error packet count for CPU GDM */
1019 +#define MT7620_MIB_STATS_GDM1_RX_SERCNT 0x330
1021 +/* Received too long error packet count for CPU GDM */
1022 +#define MT7620_MIB_STATS_GDM1_RX_LERCNT 0x334
1024 +/* Received IP/TCP/UDP checksum error packet count for CPU GDM */
1025 +#define MT7620_MIB_STATS_GDM1_RX_CERCNT 0x338
1027 +/* Received flow control pkt count for CPU GDM */
1028 +#define MT7620_MIB_STATS_GDM1_RX_FCCNT 0x33C
1030 +/* Transmit good byte count for PPE GDM */
1031 +#define MT7620_MIB_STATS_GDM2_TX_GBCNT 0x340
1033 +/* Transmit good packet count for PPE GDM (exclude flow control frames) */
1034 +#define MT7620_MIB_STATS_GDM2_TX_GPCNT 0x344
1036 +/* Transmit abort count for PPE GDM */
1037 +#define MT7620_MIB_STATS_GDM2_TX_SKIPCNT 0x348
1039 +/* Transmit collision count for PPE GDM */
1040 +#define MT7620_MIB_STATS_GDM2_TX_COLCNT 0x34C
1042 +/* Received good byte count for PPE GDM */
1043 +#define MT7620_MIB_STATS_GDM2_RX_GBCNT 0x360
1045 +/* Received good packet count for PPE GDM (exclude flow control frame) */
1046 +#define MT7620_MIB_STATS_GDM2_RX_GPCNT 0x364
1048 +/* Received overflow error packet count for PPE GDM */
1049 +#define MT7620_MIB_STATS_GDM2_RX_OERCNT 0x368
1051 +/* Received FCS error packet count for PPE GDM */
1052 +#define MT7620_MIB_STATS_GDM2_RX_FERCNT 0x36C
1054 +/* Received too short error packet count for PPE GDM */
1055 +#define MT7620_MIB_STATS_GDM2_RX_SERCNT 0x370
1057 +/* Received too long error packet count for PPE GDM */
1058 +#define MT7620_MIB_STATS_GDM2_RX_LERCNT 0x374
1060 +/* Received IP/TCP/UDP checksum error packet count for PPE GDM */
1061 +#define MT7620_MIB_STATS_GDM2_RX_CERCNT 0x378
1063 +/* Received flow control pkt count for PPE GDM */
1064 +#define MT7620_MIB_STATS_GDM2_RX_FCCNT 0x37C
1066 +/* Tx Packet Counter of Port n */
1067 +#define MT7620_MIB_STATS_PORT_TGPCN 0x10
1069 +/* Tx Bad Octet Counter of Port n */
1070 +#define MT7620_MIB_STATS_PORT_TBOCN 0x14
1072 +/* Tx Good Octet Counter of Port n */
1073 +#define MT7620_MIB_STATS_PORT_TGOCN 0x18
1075 +/* Tx Event Packet Counter of Port n */
1076 +#define MT7620_MIB_STATS_PORT_TEPCN 0x1C
1078 +/* Rx Packet Counter of Port n */
1079 +#define MT7620_MIB_STATS_PORT_RGPCN 0x20
1081 +/* Rx Bad Octet Counter of Port n */
1082 +#define MT7620_MIB_STATS_PORT_RBOCN 0x24
1084 +/* Rx Good Octet Counter of Port n */
1085 +#define MT7620_MIB_STATS_PORT_RGOCN 0x28
1087 +/* Rx Event Packet Counter of Port n */
1088 +#define MT7620_MIB_STATS_PORT_REPC1N 0x2C
1090 +/* Rx Event Packet Counter of Port n */
1091 +#define MT7620_MIB_STATS_PORT_REPC2N 0x30
1093 +#define MT7621_MIB_COUNTER_BASE 0x4000
1094 +#define MT7621_MIB_COUNTER_PORT_OFFSET 0x100
1095 +#define MT7621_STATS_TDPC 0x00
1096 +#define MT7621_STATS_TCRC 0x04
1097 +#define MT7621_STATS_TUPC 0x08
1098 +#define MT7621_STATS_TMPC 0x0C
1099 +#define MT7621_STATS_TBPC 0x10
1100 +#define MT7621_STATS_TCEC 0x14
1101 +#define MT7621_STATS_TSCEC 0x18
1102 +#define MT7621_STATS_TMCEC 0x1C
1103 +#define MT7621_STATS_TDEC 0x20
1104 +#define MT7621_STATS_TLCEC 0x24
1105 +#define MT7621_STATS_TXCEC 0x28
1106 +#define MT7621_STATS_TPPC 0x2C
1107 +#define MT7621_STATS_TL64PC 0x30
1108 +#define MT7621_STATS_TL65PC 0x34
1109 +#define MT7621_STATS_TL128PC 0x38
1110 +#define MT7621_STATS_TL256PC 0x3C
1111 +#define MT7621_STATS_TL512PC 0x40
1112 +#define MT7621_STATS_TL1024PC 0x44
1113 +#define MT7621_STATS_TOC 0x48
1114 +#define MT7621_STATS_RDPC 0x60
1115 +#define MT7621_STATS_RFPC 0x64
1116 +#define MT7621_STATS_RUPC 0x68
1117 +#define MT7621_STATS_RMPC 0x6C
1118 +#define MT7621_STATS_RBPC 0x70
1119 +#define MT7621_STATS_RAEPC 0x74
1120 +#define MT7621_STATS_RCEPC 0x78
1121 +#define MT7621_STATS_RUSPC 0x7C
1122 +#define MT7621_STATS_RFEPC 0x80
1123 +#define MT7621_STATS_ROSPC 0x84
1124 +#define MT7621_STATS_RJEPC 0x88
1125 +#define MT7621_STATS_RPPC 0x8C
1126 +#define MT7621_STATS_RL64PC 0x90
1127 +#define MT7621_STATS_RL65PC 0x94
1128 +#define MT7621_STATS_RL128PC 0x98
1129 +#define MT7621_STATS_RL256PC 0x9C
1130 +#define MT7621_STATS_RL512PC 0xA0
1131 +#define MT7621_STATS_RL1024PC 0xA4
1132 +#define MT7621_STATS_ROC 0xA8
1133 +#define MT7621_STATS_RDPC_CTRL 0xB0
1134 +#define MT7621_STATS_RDPC_ING 0xB4
1135 +#define MT7621_STATS_RDPC_ARL 0xB8
1137 +int mt7530_probe(struct device *dev, void __iomem *base, struct mii_bus *bus, int vlan);
1140 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
1141 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
1142 @@ -1291,8 +1291,13 @@ static int __init fe_init(struct net_dev
1145 err = fe_hw_init(dev);
1149 + goto err_phy_disconnect;
1151 + if ((priv->flags & FE_FLAG_HAS_SWITCH) && priv->soc->switch_config)
1152 + priv->soc->switch_config(priv);
1158 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
1159 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
1160 @@ -383,6 +383,7 @@ struct fe_soc_data {
1161 int (*fwd_config)(struct fe_priv *priv);
1162 void (*tx_dma)(struct fe_tx_dma *txd);
1163 int (*switch_init)(struct fe_priv *priv);
1164 + int (*switch_config)(struct fe_priv *priv);
1165 void (*port_init)(struct fe_priv *priv, struct device_node *port);
1166 int (*has_carrier)(struct fe_priv *priv);
1167 int (*mdio_init)(struct fe_priv *priv);
1168 --- a/drivers/net/ethernet/mediatek/soc_mt7620.c
1169 +++ b/drivers/net/ethernet/mediatek/soc_mt7620.c
1170 @@ -313,6 +313,7 @@ static struct fe_soc_data mt7620_data =
1171 .fwd_config = mt7620_fwd_config,
1172 .tx_dma = mt7620_tx_dma,
1173 .switch_init = mtk_gsw_init,
1174 + .switch_config = mt7620_gsw_config,
1175 .port_init = mt7620_port_init,
1176 .reg_table = mt7620_reg_table,
1177 .pdma_glo_cfg = FE_PDMA_SIZE_16DWORDS,