1 From b327cd58c3fec1c6382128e929eab9bc0d68e912 Mon Sep 17 00:00:00 2001
2 From: Sergio Paracuellos <sergio.paracuellos@gmail.com>
3 Date: Sun, 8 Mar 2020 10:19:27 +0100
4 Subject: [PATCH] staging: mt7621-pci: simplify
5 'mt7621_pcie_init_virtual_bridges' function
7 Function 'mt7621_pcie_init_virtual_bridges' is a bit mess and can be
8 refactorized properly in a cleaner way. Introduce new 'pcie_rmw' inline
9 function helper to do clear and set the correct bits this function needs
12 Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
13 Link: https://lore.kernel.org/r/20200308091928.17177-1-sergio.paracuellos@gmail.com
14 Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
16 drivers/staging/mt7621-pci/pci-mt7621.c | 85 +++++++++++++--------------------
17 1 file changed, 33 insertions(+), 52 deletions(-)
19 --- a/drivers/staging/mt7621-pci/pci-mt7621.c
20 +++ b/drivers/staging/mt7621-pci/pci-mt7621.c
22 #define RALINK_PCI_IOBASE 0x002C
24 /* PCICFG virtual bridges */
25 -#define MT7621_BR0_MASK GENMASK(19, 16)
26 -#define MT7621_BR1_MASK GENMASK(23, 20)
27 -#define MT7621_BR2_MASK GENMASK(27, 24)
28 -#define MT7621_BR_ALL_MASK GENMASK(27, 16)
29 -#define MT7621_BR0_SHIFT 16
30 -#define MT7621_BR1_SHIFT 20
31 -#define MT7621_BR2_SHIFT 24
32 +#define PCIE_P2P_MAX 3
33 +#define PCIE_P2P_BR_DEVNUM_SHIFT(p) (16 + (p) * 4)
34 +#define PCIE_P2P_BR_DEVNUM0_SHIFT PCIE_P2P_BR_DEVNUM_SHIFT(0)
35 +#define PCIE_P2P_BR_DEVNUM1_SHIFT PCIE_P2P_BR_DEVNUM_SHIFT(1)
36 +#define PCIE_P2P_BR_DEVNUM2_SHIFT PCIE_P2P_BR_DEVNUM_SHIFT(2)
37 +#define PCIE_P2P_BR_DEVNUM_MASK 0xf
38 +#define PCIE_P2P_BR_DEVNUM_MASK_FULL (0xfff << PCIE_P2P_BR_DEVNUM0_SHIFT)
40 /* PCIe RC control registers */
41 #define MT7621_PCIE_OFFSET 0x2000
42 @@ -154,6 +154,15 @@ static inline void pcie_write(struct mt7
43 writel(val, pcie->base + reg);
46 +static inline void pcie_rmw(struct mt7621_pcie *pcie, u32 reg, u32 clr, u32 set)
48 + u32 val = readl(pcie->base + reg);
52 + writel(val, pcie->base + reg);
55 static inline u32 pcie_port_read(struct mt7621_pcie_port *port, u32 reg)
57 return readl(port->base + reg);
58 @@ -554,7 +563,9 @@ static void mt7621_pcie_enable_ports(str
59 static int mt7621_pcie_init_virtual_bridges(struct mt7621_pcie *pcie)
61 u32 pcie_link_status = 0;
65 + u32 p2p_br_devnum[PCIE_P2P_MAX];
66 struct mt7621_pcie_port *port;
68 list_for_each_entry(port, &pcie->ports, list) {
69 @@ -567,50 +578,20 @@ static int mt7621_pcie_init_virtual_brid
70 if (pcie_link_status == 0)
74 - * pcie(2/1/0) link status pcie2_num pcie1_num pcie0_num
84 - switch (pcie_link_status) {
86 - val = pcie_read(pcie, RALINK_PCI_PCICFG_ADDR);
87 - val &= ~(MT7621_BR0_MASK | MT7621_BR1_MASK);
88 - val |= 0x1 << MT7621_BR0_SHIFT;
89 - val |= 0x0 << MT7621_BR1_SHIFT;
90 - pcie_write(pcie, val, RALINK_PCI_PCICFG_ADDR);
93 - val = pcie_read(pcie, RALINK_PCI_PCICFG_ADDR);
94 - val &= ~MT7621_BR_ALL_MASK;
95 - val |= 0x1 << MT7621_BR0_SHIFT;
96 - val |= 0x2 << MT7621_BR1_SHIFT;
97 - val |= 0x0 << MT7621_BR2_SHIFT;
98 - pcie_write(pcie, val, RALINK_PCI_PCICFG_ADDR);
101 - val = pcie_read(pcie, RALINK_PCI_PCICFG_ADDR);
102 - val &= ~MT7621_BR_ALL_MASK;
103 - val |= 0x0 << MT7621_BR0_SHIFT;
104 - val |= 0x2 << MT7621_BR1_SHIFT;
105 - val |= 0x1 << MT7621_BR2_SHIFT;
106 - pcie_write(pcie, val, RALINK_PCI_PCICFG_ADDR);
109 - val = pcie_read(pcie, RALINK_PCI_PCICFG_ADDR);
110 - val &= ~MT7621_BR_ALL_MASK;
111 - val |= 0x2 << MT7621_BR0_SHIFT;
112 - val |= 0x0 << MT7621_BR1_SHIFT;
113 - val |= 0x1 << MT7621_BR2_SHIFT;
114 - pcie_write(pcie, val, RALINK_PCI_PCICFG_ADDR);
118 + for (i = 0; i < PCIE_P2P_MAX; i++)
119 + if (pcie_link_status & BIT(i))
120 + p2p_br_devnum[i] = n++;
122 + for (i = 0; i < PCIE_P2P_MAX; i++)
123 + if ((pcie_link_status & BIT(i)) == 0)
124 + p2p_br_devnum[i] = n++;
126 + pcie_rmw(pcie, RALINK_PCI_CONFIG_ADDR,
127 + PCIE_P2P_BR_DEVNUM_MASK_FULL,
128 + (p2p_br_devnum[0] << PCIE_P2P_BR_DEVNUM0_SHIFT) |
129 + (p2p_br_devnum[1] << PCIE_P2P_BR_DEVNUM1_SHIFT) |
130 + (p2p_br_devnum[2] << PCIE_P2P_BR_DEVNUM2_SHIFT));