1 From 3faf4e1c537de86058fc22a851cd979489b9185e Mon Sep 17 00:00:00 2001
2 From: Sergio Paracuellos <sergio.paracuellos@gmail.com>
3 Date: Wed, 18 Mar 2020 10:44:45 +0100
4 Subject: [PATCH] staging: mt7621-pci: fix io space and properly set resource
7 Function 'mt7621_pci_parse_request_of_pci_ranges' is using
8 'of_pci_range_to_resource' to get both mem and io resources.
9 Internally this function calls to 'pci_address_to_pio' which
10 returns -1 if io space address is an address > IO_SPACE_LIMIT
11 which is 0xFFFF for mips. This mt7621 soc has io space in physical
12 address 0x1e160000. In order to fix this, overwrite invalid io
13 0xffffffff with properly values from the device tree and set
14 mapped address of this resource as io port base memory address
15 calling 'set_io_port_base' function. There is also need to properly
16 setup resource limits and io and memory windows with properly
17 parsed values instead of set them as 'no limit' which it is wrong.
18 For any reason I don't really know legacy driver sets up mem window
19 as 0xFFFFFFFF and any other value seems to does not work as expected,
20 so set up also here with same values.
22 Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
23 Link: https://lore.kernel.org/r/20200318094445.19669-1-sergio.paracuellos@gmail.com
24 Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
26 drivers/staging/mt7621-pci/pci-mt7621.c | 43 +++++++++++++++++++--------------
27 1 file changed, 25 insertions(+), 18 deletions(-)
29 --- a/drivers/staging/mt7621-pci/pci-mt7621.c
30 +++ b/drivers/staging/mt7621-pci/pci-mt7621.c
31 @@ -118,6 +118,7 @@ struct mt7621_pcie_port {
33 * @offset: IO / Memory offset
34 * @dev: Pointer to PCIe device
35 + * @io_map_base: virtual memory base address for io
36 * @ports: pointer to PCIe port information
37 * @resets_inverted: depends on chip revision
38 * reset lines are inverted.
39 @@ -132,6 +133,7 @@ struct mt7621_pcie {
43 + unsigned long io_map_base;
44 struct list_head ports;
47 @@ -291,22 +293,21 @@ static int mt7621_pci_parse_request_of_p
50 for_each_of_pci_range(&parser, &range) {
51 - struct resource *res = NULL;
53 switch (range.flags & IORESOURCE_TYPE_BITS) {
55 - ioremap(range.cpu_addr, range.size);
58 + (unsigned long)ioremap(range.cpu_addr,
60 + of_pci_range_to_resource(&range, node, &pcie->io);
61 + pcie->io.start = range.cpu_addr;
62 + pcie->io.end = range.cpu_addr + range.size - 1;
63 pcie->offset.io = 0x00000000UL;
67 + of_pci_range_to_resource(&range, node, &pcie->mem);
68 pcie->offset.mem = 0x00000000UL;
73 - of_pci_range_to_resource(&range, node, res);
76 err = of_pci_parse_bus_range(node, &pcie->busn);
77 @@ -318,6 +319,8 @@ static int mt7621_pci_parse_request_of_p
78 pcie->busn.flags = IORESOURCE_BUS;
81 + set_io_port_base(pcie->io_map_base);
86 @@ -548,6 +551,10 @@ static void mt7621_pcie_enable_ports(str
90 + /* Setup MEMWIN and IOWIN */
91 + pcie_write(pcie, 0xffffffff, RALINK_PCI_MEMBASE);
92 + pcie_write(pcie, pcie->io.start, RALINK_PCI_IOBASE);
94 list_for_each_entry(port, &pcie->ports, list) {
96 mt7621_pcie_port_clk_enable(port);
97 @@ -668,11 +675,17 @@ static int mt7621_pci_probe(struct platf
101 + err = mt7621_pci_parse_request_of_pci_ranges(pcie);
103 + dev_err(dev, "Error requesting pci resources from ranges");
104 + goto out_release_gpios;
107 /* set resources limits */
108 - iomem_resource.start = 0;
109 - iomem_resource.end = ~0UL; /* no limit */
110 - ioport_resource.start = 0;
111 - ioport_resource.end = ~0UL; /* no limit */
112 + iomem_resource.start = pcie->mem.start;
113 + iomem_resource.end = pcie->mem.end;
114 + ioport_resource.start = pcie->io.start;
115 + ioport_resource.end = pcie->io.end;
117 mt7621_pcie_init_ports(pcie);
119 @@ -685,12 +698,6 @@ static int mt7621_pci_probe(struct platf
121 mt7621_pcie_enable_ports(pcie);
123 - err = mt7621_pci_parse_request_of_pci_ranges(pcie);
125 - dev_err(dev, "Error requesting pci resources from ranges");
126 - goto out_release_gpios;
129 setup_cm_memory_region(pcie);
131 err = mt7621_pcie_request_resources(pcie, &res);