1 From 7f29222b1731e8182ba94a331531dec18865a1e4 Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Sun, 27 Jul 2014 09:31:47 +0100
4 Subject: [PATCH 48/53] asoc: add mt7620 support
6 Signed-off-by: John Crispin <blogic@openwrt.org>
8 arch/mips/ralink/of.c | 2 +
9 sound/soc/Kconfig | 1 +
10 sound/soc/Makefile | 1 +
11 sound/soc/ralink/Kconfig | 15 ++
12 sound/soc/ralink/Makefile | 11 +
13 sound/soc/ralink/mt7620-i2s.c | 436 ++++++++++++++++++++++++++++++++++++++
14 sound/soc/ralink/mt7620-wm8960.c | 233 ++++++++++++++++++++
15 7 files changed, 699 insertions(+)
16 create mode 100644 sound/soc/ralink/Kconfig
17 create mode 100644 sound/soc/ralink/Makefile
18 create mode 100644 sound/soc/ralink/mt7620-i2s.c
19 create mode 100644 sound/soc/ralink/mt7620-wm8960.c
21 --- a/sound/soc/Kconfig
22 +++ b/sound/soc/Kconfig
23 @@ -78,6 +78,7 @@ source "sound/soc/mxs/Kconfig"
24 source "sound/soc/pxa/Kconfig"
25 source "sound/soc/qcom/Kconfig"
26 source "sound/soc/rockchip/Kconfig"
27 +source "sound/soc/ralink/Kconfig"
28 source "sound/soc/samsung/Kconfig"
29 source "sound/soc/sh/Kconfig"
30 source "sound/soc/sof/Kconfig"
31 --- a/sound/soc/Makefile
32 +++ b/sound/soc/Makefile
33 @@ -48,6 +48,7 @@ obj-$(CONFIG_SND_SOC) += kirkwood/
34 obj-$(CONFIG_SND_SOC) += pxa/
35 obj-$(CONFIG_SND_SOC) += qcom/
36 obj-$(CONFIG_SND_SOC) += rockchip/
37 +obj-$(CONFIG_SND_SOC) += ralink/
38 obj-$(CONFIG_SND_SOC) += samsung/
39 obj-$(CONFIG_SND_SOC) += sh/
40 obj-$(CONFIG_SND_SOC) += sof/
42 +++ b/sound/soc/ralink/Kconfig
44 +config SND_RALINK_SOC_I2S
45 + depends on RALINK && SND_SOC && !SOC_RT288X
46 + select SND_SOC_GENERIC_DMAENGINE_PCM
48 + tristate "SoC Audio (I2S protocol) for Ralink SoC"
50 + Say Y if you want to use I2S protocol and I2S codec on Ralink/MediaTek
53 +++ b/sound/soc/ralink/Makefile
56 +# Ralink/MediaTek Platform Support
58 +snd-soc-ralink-i2s-objs := ralink-i2s.o
60 +obj-$(CONFIG_SND_RALINK_SOC_I2S) += snd-soc-ralink-i2s.o
62 +++ b/sound/soc/ralink/ralink-i2s.c
65 + * Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
66 + * Copyright (C) 2016 Michael Lee <igvtee@gmail.com>
68 + * This program is free software; you can redistribute it and/or modify it
69 + * under the terms of the GNU General Public License as published by the
70 + * Free Software Foundation; either version 2 of the License, or (at your
71 + * option) any later version.
73 + * You should have received a copy of the GNU General Public License along
74 + * with this program; if not, write to the Free Software Foundation, Inc.,
75 + * 675 Mass Ave, Cambridge, MA 02139, USA.
79 +#include <linux/module.h>
80 +#include <linux/platform_device.h>
81 +#include <linux/clk.h>
82 +#include <linux/regmap.h>
83 +#include <linux/reset.h>
84 +#include <linux/debugfs.h>
85 +#include <linux/of_device.h>
86 +#include <sound/pcm_params.h>
87 +#include <sound/dmaengine_pcm.h>
89 +#include <asm/mach-ralink/ralink_regs.h>
91 +#define DRV_NAME "ralink-i2s"
93 +#define I2S_REG_CFG0 0x00
94 +#define I2S_REG_INT_STATUS 0x04
95 +#define I2S_REG_INT_EN 0x08
96 +#define I2S_REG_FF_STATUS 0x0c
97 +#define I2S_REG_WREG 0x10
98 +#define I2S_REG_RREG 0x14
99 +#define I2S_REG_CFG1 0x18
100 +#define I2S_REG_DIVCMP 0x20
101 +#define I2S_REG_DIVINT 0x24
104 +#define I2S_REG_CFG0_EN BIT(31)
105 +#define I2S_REG_CFG0_DMA_EN BIT(30)
106 +#define I2S_REG_CFG0_BYTE_SWAP BIT(28)
107 +#define I2S_REG_CFG0_TX_EN BIT(24)
108 +#define I2S_REG_CFG0_RX_EN BIT(20)
109 +#define I2S_REG_CFG0_SLAVE BIT(16)
110 +#define I2S_REG_CFG0_RX_THRES 12
111 +#define I2S_REG_CFG0_TX_THRES 4
112 +#define I2S_REG_CFG0_THRES_MASK (0xf << I2S_REG_CFG0_RX_THRES) | \
113 + (4 << I2S_REG_CFG0_TX_THRES)
114 +#define I2S_REG_CFG0_DFT_THRES (4 << I2S_REG_CFG0_RX_THRES) | \
115 + (4 << I2S_REG_CFG0_TX_THRES)
117 +#define I2S_REG_CFG0_CLK_DIS BIT(8)
118 +#define I2S_REG_CFG0_TXCH_SWAP BIT(3)
119 +#define I2S_REG_CFG0_TXCH1_OFF BIT(2)
120 +#define I2S_REG_CFG0_TXCH0_OFF BIT(1)
121 +#define I2S_REG_CFG0_SLAVE_EN BIT(0)
123 +#define I2S_REG_CFG0_RXCH_SWAP BIT(11)
124 +#define I2S_REG_CFG0_RXCH1_OFF BIT(10)
125 +#define I2S_REG_CFG0_RXCH0_OFF BIT(9)
126 +#define I2S_REG_CFG0_WS_INV BIT(0)
128 +#define I2S_REG_CFG0_FMT_LE BIT(29)
129 +#define I2S_REG_CFG0_SYS_BE BIT(28)
130 +#define I2S_REG_CFG0_NORM_24 BIT(18)
131 +#define I2S_REG_CFG0_DATA_24 BIT(17)
133 +/* I2S_REG_INT_STATUS */
134 +#define I2S_REG_INT_RX_FAULT BIT(7)
135 +#define I2S_REG_INT_RX_OVRUN BIT(6)
136 +#define I2S_REG_INT_RX_UNRUN BIT(5)
137 +#define I2S_REG_INT_RX_THRES BIT(4)
138 +#define I2S_REG_INT_TX_FAULT BIT(3)
139 +#define I2S_REG_INT_TX_OVRUN BIT(2)
140 +#define I2S_REG_INT_TX_UNRUN BIT(1)
141 +#define I2S_REG_INT_TX_THRES BIT(0)
142 +#define I2S_REG_INT_TX_MASK 0xf
143 +#define I2S_REG_INT_RX_MASK 0xf0
145 +/* I2S_REG_INT_STATUS */
146 +#define I2S_RX_AVCNT(x) ((x >> 4) & 0xf)
147 +#define I2S_TX_AVCNT(x) (x & 0xf)
149 +#define MT7628_I2S_RX_AVCNT(x) ((x >> 8) & 0x1f)
150 +#define MT7628_I2S_TX_AVCNT(x) (x & 0x1f)
153 +#define I2S_REG_CFG1_LBK BIT(31)
154 +#define I2S_REG_CFG1_EXTLBK BIT(30)
156 +#define I2S_REG_CFG1_LEFT_J BIT(0)
157 +#define I2S_REG_CFG1_RIGHT_J BIT(1)
158 +#define I2S_REG_CFG1_FMT_MASK 0x3
160 +/* I2S_REG_DIVCMP */
161 +#define I2S_REG_DIVCMP_CLKEN BIT(31)
162 +#define I2S_REG_DIVCMP_DIVCOMP_MASK 0x1ff
164 +/* I2S_REG_DIVINT */
165 +#define I2S_REG_DIVINT_MASK 0x3ff
168 +#define RALINK_I2S_DIVCMP 0
169 +#define RALINK_I2S_DIVINT 1
172 +#define RALINK_I2S_FIFO_SIZE 32
175 +#define RALINK_FLAGS_TXONLY BIT(0)
176 +#define RALINK_FLAGS_LEFT_J BIT(1)
177 +#define RALINK_FLAGS_RIGHT_J BIT(2)
178 +#define RALINK_FLAGS_ENDIAN BIT(3)
179 +#define RALINK_FLAGS_24BIT BIT(4)
181 +#define RALINK_I2S_INT_EN 0
183 +struct ralink_i2s_stats {
191 + struct device *dev;
192 + void __iomem *regs;
194 + struct regmap *regmap;
200 + struct snd_dmaengine_dai_dma_data playback_dma_data;
201 + struct snd_dmaengine_dai_dma_data capture_dma_data;
203 + struct dentry *dbg_dir;
204 + struct dentry *dbg_stats;
205 + struct ralink_i2s_stats txstats;
206 + struct ralink_i2s_stats rxstats;
209 +static void ralink_i2s_dump_regs(struct ralink_i2s *i2s)
214 + ret = regmap_bulk_read(i2s->regmap, I2S_REG_CFG0,
215 + buf, ARRAY_SIZE(buf));
217 + dev_dbg(i2s->dev, "CFG0: %08x, INTSTAT: %08x, INTEN: %08x, " \
218 + "FFSTAT: %08x, WREG: %08x, RREG: %08x, " \
219 + "CFG1: %08x, DIVCMP: %08x, DIVINT: %08x\n",
220 + buf[0], buf[1], buf[2], buf[3], buf[4],
221 + buf[5], buf[6], buf[8], buf[9]);
224 +static int ralink_i2s_set_sysclk(struct snd_soc_dai *dai,
225 + int clk_id, unsigned int freq, int dir)
230 +static int ralink_i2s_set_sys_bclk(struct snd_soc_dai *dai, int width, int rate)
232 + struct ralink_i2s *i2s = snd_soc_dai_get_drvdata(dai);
233 + unsigned long clk = clk_get_rate(i2s->clk);
237 + /* disable clock at slave mode */
238 + if ((i2s->fmt & SND_SOC_DAIFMT_MASTER_MASK) ==
239 + SND_SOC_DAIFMT_CBM_CFM) {
240 + regmap_update_bits(i2s->regmap, I2S_REG_CFG0,
241 + I2S_REG_CFG0_CLK_DIS,
242 + I2S_REG_CFG0_CLK_DIS);
246 + /* FREQOUT = FREQIN / (I2S_CLK_DIV + 1) */
247 + div = (clk / rate ) - 1;
249 + data = rt_sysc_r32(0x30);
250 + data &= (0xff << 8);
251 + data |= (0x1 << 15) | (div << 8);
252 + rt_sysc_w32(data, 0x30);
255 + regmap_update_bits(i2s->regmap, I2S_REG_CFG0, I2S_REG_CFG0_CLK_DIS, 0);
257 + dev_dbg(i2s->dev, "clk: %lu, rate: %u, div: %d\n",
263 +static int ralink_i2s_set_bclk(struct snd_soc_dai *dai, int width, int rate)
265 + struct ralink_i2s *i2s = snd_soc_dai_get_drvdata(dai);
266 + unsigned long clk = clk_get_rate(i2s->clk);
267 + int divint, divcomp;
269 + /* disable clock at slave mode */
270 + if ((i2s->fmt & SND_SOC_DAIFMT_MASTER_MASK) ==
271 + SND_SOC_DAIFMT_CBM_CFM) {
272 + regmap_update_bits(i2s->regmap, I2S_REG_DIVCMP,
273 + I2S_REG_DIVCMP_CLKEN, 0);
277 + /* FREQOUT = FREQIN * (1/2) * (1/(DIVINT + DIVCOMP/512)) */
278 + clk = clk / (2 * 2 * width);
279 + divint = clk / rate;
280 + divcomp = ((clk % rate) * 512) / rate;
282 + if ((divint > I2S_REG_DIVINT_MASK) ||
283 + (divcomp > I2S_REG_DIVCMP_DIVCOMP_MASK))
286 + regmap_update_bits(i2s->regmap, I2S_REG_DIVINT,
287 + I2S_REG_DIVINT_MASK, divint);
288 + regmap_update_bits(i2s->regmap, I2S_REG_DIVCMP,
289 + I2S_REG_DIVCMP_DIVCOMP_MASK, divcomp);
292 + regmap_update_bits(i2s->regmap, I2S_REG_DIVCMP, I2S_REG_DIVCMP_CLKEN,
293 + I2S_REG_DIVCMP_CLKEN);
295 + dev_dbg(i2s->dev, "clk: %lu, rate: %u, int: %d, comp: %d\n",
296 + clk_get_rate(i2s->clk), rate, divint, divcomp);
301 +static int ralink_i2s_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
303 + struct ralink_i2s *i2s = snd_soc_dai_get_drvdata(dai);
304 + unsigned int cfg0 = 0, cfg1 = 0;
306 + /* set master/slave audio interface */
307 + switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
308 + case SND_SOC_DAIFMT_CBM_CFM:
309 + if (i2s->flags & RALINK_FLAGS_TXONLY)
310 + cfg0 |= I2S_REG_CFG0_SLAVE_EN;
312 + cfg0 |= I2S_REG_CFG0_SLAVE;
314 + case SND_SOC_DAIFMT_CBS_CFS:
320 + /* interface format */
321 + switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
322 + case SND_SOC_DAIFMT_I2S:
324 + case SND_SOC_DAIFMT_RIGHT_J:
325 + if (i2s->flags & RALINK_FLAGS_RIGHT_J) {
326 + cfg1 |= I2S_REG_CFG1_RIGHT_J;
330 + case SND_SOC_DAIFMT_LEFT_J:
331 + if (i2s->flags & RALINK_FLAGS_LEFT_J) {
332 + cfg1 |= I2S_REG_CFG1_LEFT_J;
340 + /* clock inversion */
341 + switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
342 + case SND_SOC_DAIFMT_NB_NF:
348 + if (i2s->flags & RALINK_FLAGS_TXONLY) {
349 + regmap_update_bits(i2s->regmap, I2S_REG_CFG0,
350 + I2S_REG_CFG0_SLAVE_EN, cfg0);
352 + regmap_update_bits(i2s->regmap, I2S_REG_CFG0,
353 + I2S_REG_CFG0_SLAVE, cfg0);
355 + regmap_update_bits(i2s->regmap, I2S_REG_CFG1,
356 + I2S_REG_CFG1_FMT_MASK, cfg1);
362 +static int ralink_i2s_startup(struct snd_pcm_substream *substream,
363 + struct snd_soc_dai *dai)
365 + struct ralink_i2s *i2s = snd_soc_dai_get_drvdata(dai);
367 + if (snd_soc_dai_active(dai))
370 + /* setup status interrupt */
371 +#if (RALINK_I2S_INT_EN)
372 + regmap_write(i2s->regmap, I2S_REG_INT_EN, 0xff);
374 + regmap_write(i2s->regmap, I2S_REG_INT_EN, 0x0);
378 + regmap_update_bits(i2s->regmap, I2S_REG_CFG0,
379 + I2S_REG_CFG0_EN | I2S_REG_CFG0_DMA_EN |
380 + I2S_REG_CFG0_THRES_MASK,
381 + I2S_REG_CFG0_EN | I2S_REG_CFG0_DMA_EN |
382 + I2S_REG_CFG0_DFT_THRES);
387 +static void ralink_i2s_shutdown(struct snd_pcm_substream *substream,
388 + struct snd_soc_dai *dai)
390 + struct ralink_i2s *i2s = snd_soc_dai_get_drvdata(dai);
392 + /* If both streams are stopped, disable module and clock */
393 + if (snd_soc_dai_active(dai))
397 + * datasheet mention when disable all control regs are cleared
398 + * to initial values. need reinit at startup.
400 + regmap_update_bits(i2s->regmap, I2S_REG_CFG0, I2S_REG_CFG0_EN, 0);
403 +static int ralink_i2s_hw_params(struct snd_pcm_substream *substream,
404 + struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
406 + struct ralink_i2s *i2s = snd_soc_dai_get_drvdata(dai);
410 + width = params_width(params);
413 + if (i2s->flags & RALINK_FLAGS_24BIT)
414 + regmap_update_bits(i2s->regmap, I2S_REG_CFG0,
415 + I2S_REG_CFG0_DATA_24, 0);
418 + if (i2s->flags & RALINK_FLAGS_24BIT) {
419 + regmap_update_bits(i2s->regmap, I2S_REG_CFG0,
420 + I2S_REG_CFG0_DATA_24,
421 + I2S_REG_CFG0_DATA_24);
429 + switch (params_channels(params)) {
436 + if (i2s->flags & RALINK_FLAGS_ENDIAN) {
437 + /* system endian */
438 +#ifdef SNDRV_LITTLE_ENDIAN
439 + regmap_update_bits(i2s->regmap, I2S_REG_CFG0,
440 + I2S_REG_CFG0_SYS_BE, 0);
442 + regmap_update_bits(i2s->regmap, I2S_REG_CFG0,
443 + I2S_REG_CFG0_SYS_BE,
444 + I2S_REG_CFG0_SYS_BE);
448 + switch (params_format(params)) {
449 + case SNDRV_PCM_FORMAT_S16_LE:
450 + case SNDRV_PCM_FORMAT_S24_LE:
451 + regmap_update_bits(i2s->regmap, I2S_REG_CFG0,
452 + I2S_REG_CFG0_FMT_LE,
453 + I2S_REG_CFG0_FMT_LE);
455 + case SNDRV_PCM_FORMAT_S16_BE:
456 + case SNDRV_PCM_FORMAT_S24_BE:
457 + regmap_update_bits(i2s->regmap, I2S_REG_CFG0,
458 + I2S_REG_CFG0_FMT_LE, 0);
465 + /* setup bclk rate */
466 + if (i2s->flags & RALINK_FLAGS_TXONLY)
467 + ret = ralink_i2s_set_sys_bclk(dai, width, params_rate(params));
469 + ret = ralink_i2s_set_bclk(dai, width, params_rate(params));
474 +static int ralink_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
475 + struct snd_soc_dai *dai)
477 + struct ralink_i2s *i2s = snd_soc_dai_get_drvdata(dai);
478 + unsigned int mask, val;
480 + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
481 + mask = I2S_REG_CFG0_TX_EN;
483 + mask = I2S_REG_CFG0_RX_EN;
486 + case SNDRV_PCM_TRIGGER_START:
487 + case SNDRV_PCM_TRIGGER_RESUME:
488 + case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
491 + case SNDRV_PCM_TRIGGER_STOP:
492 + case SNDRV_PCM_TRIGGER_SUSPEND:
493 + case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
500 + regmap_update_bits(i2s->regmap, I2S_REG_CFG0, mask, val);
505 +static void ralink_i2s_init_dma_data(struct ralink_i2s *i2s,
506 + struct resource *res)
508 + struct snd_dmaengine_dai_dma_data *dma_data;
511 + dma_data = &i2s->playback_dma_data;
512 + dma_data->addr = res->start + I2S_REG_WREG;
513 + dma_data->addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
514 + dma_data->maxburst = 1;
516 + if (i2s->flags & RALINK_FLAGS_TXONLY)
520 + dma_data = &i2s->capture_dma_data;
521 + dma_data->addr = res->start + I2S_REG_RREG;
522 + dma_data->addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
523 + dma_data->maxburst = 1;
526 +static int ralink_i2s_dai_probe(struct snd_soc_dai *dai)
528 + struct ralink_i2s *i2s = snd_soc_dai_get_drvdata(dai);
530 + snd_soc_dai_init_dma_data(dai, &i2s->playback_dma_data,
531 + &i2s->capture_dma_data);
536 +static int ralink_i2s_dai_remove(struct snd_soc_dai *dai)
541 +static const struct snd_soc_dai_ops ralink_i2s_dai_ops = {
542 + .set_sysclk = ralink_i2s_set_sysclk,
543 + .set_fmt = ralink_i2s_set_fmt,
544 + .startup = ralink_i2s_startup,
545 + .shutdown = ralink_i2s_shutdown,
546 + .hw_params = ralink_i2s_hw_params,
547 + .trigger = ralink_i2s_trigger,
550 +static struct snd_soc_dai_driver ralink_i2s_dai = {
552 + .probe = ralink_i2s_dai_probe,
553 + .remove = ralink_i2s_dai_remove,
554 + .ops = &ralink_i2s_dai_ops,
556 + .stream_name = "I2S Capture",
560 + .rate_max = 192000,
561 + .rates = SNDRV_PCM_RATE_CONTINUOUS,
562 + .formats = SNDRV_PCM_FMTBIT_S16_LE,
565 + .stream_name = "I2S Playback",
569 + .rate_max = 192000,
570 + .rates = SNDRV_PCM_RATE_CONTINUOUS,
571 + .formats = SNDRV_PCM_FMTBIT_S16_LE,
573 + .symmetric_rate = 1,
576 +static struct snd_pcm_hardware ralink_pcm_hardware = {
577 + .info = SNDRV_PCM_INFO_MMAP |
578 + SNDRV_PCM_INFO_MMAP_VALID |
579 + SNDRV_PCM_INFO_INTERLEAVED |
580 + SNDRV_PCM_INFO_BLOCK_TRANSFER,
581 + .formats = SNDRV_PCM_FMTBIT_S16_LE,
584 + .period_bytes_min = PAGE_SIZE,
585 + .period_bytes_max = PAGE_SIZE * 2,
587 + .periods_max = 128,
588 + .buffer_bytes_max = 128 * 1024,
589 + .fifo_size = RALINK_I2S_FIFO_SIZE,
592 +static const struct snd_dmaengine_pcm_config ralink_dmaengine_pcm_config = {
593 + .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config,
594 + .pcm_hardware = &ralink_pcm_hardware,
595 + .prealloc_buffer_size = 256 * PAGE_SIZE,
598 +static const struct snd_soc_component_driver ralink_i2s_component = {
602 +static bool ralink_i2s_readable_reg(struct device *dev, unsigned int reg)
607 +static bool ralink_i2s_volatile_reg(struct device *dev, unsigned int reg)
610 + case I2S_REG_INT_STATUS:
611 + case I2S_REG_FF_STATUS:
617 +static bool ralink_i2s_writeable_reg(struct device *dev, unsigned int reg)
620 + case I2S_REG_FF_STATUS:
627 +static const struct regmap_config ralink_i2s_regmap_config = {
631 + .writeable_reg = ralink_i2s_writeable_reg,
632 + .readable_reg = ralink_i2s_readable_reg,
633 + .volatile_reg = ralink_i2s_volatile_reg,
634 + .max_register = I2S_REG_DIVINT,
637 +#if (RALINK_I2S_INT_EN)
638 +static irqreturn_t ralink_i2s_irq(int irq, void *devid)
640 + struct ralink_i2s *i2s = devid;
643 + regmap_read(i2s->regmap, I2S_REG_INT_STATUS, &status);
644 + if (unlikely(!status))
648 + if (status & I2S_REG_INT_TX_MASK) {
649 + if (status & I2S_REG_INT_TX_THRES)
650 + i2s->txstats.belowthres++;
651 + if (status & I2S_REG_INT_TX_UNRUN)
652 + i2s->txstats.underrun++;
653 + if (status & I2S_REG_INT_TX_OVRUN)
654 + i2s->txstats.overrun++;
655 + if (status & I2S_REG_INT_TX_FAULT)
656 + i2s->txstats.dmafault++;
660 + if (status & I2S_REG_INT_RX_MASK) {
661 + if (status & I2S_REG_INT_RX_THRES)
662 + i2s->rxstats.belowthres++;
663 + if (status & I2S_REG_INT_RX_UNRUN)
664 + i2s->rxstats.underrun++;
665 + if (status & I2S_REG_INT_RX_OVRUN)
666 + i2s->rxstats.overrun++;
667 + if (status & I2S_REG_INT_RX_FAULT)
668 + i2s->rxstats.dmafault++;
671 + /* clean status bits */
672 + regmap_write(i2s->regmap, I2S_REG_INT_STATUS, status);
674 + return IRQ_HANDLED;
678 +#if IS_ENABLED(CONFIG_DEBUG_FS)
679 +static int ralink_i2s_stats_show(struct seq_file *s, void *unused)
681 + struct ralink_i2s *i2s = s->private;
683 + seq_printf(s, "tx stats\n");
684 + seq_printf(s, "\tbelow threshold\t%u\n", i2s->txstats.belowthres);
685 + seq_printf(s, "\tunder run\t%u\n", i2s->txstats.underrun);
686 + seq_printf(s, "\tover run\t%u\n", i2s->txstats.overrun);
687 + seq_printf(s, "\tdma fault\t%u\n", i2s->txstats.dmafault);
689 + seq_printf(s, "rx stats\n");
690 + seq_printf(s, "\tbelow threshold\t%u\n", i2s->rxstats.belowthres);
691 + seq_printf(s, "\tunder run\t%u\n", i2s->rxstats.underrun);
692 + seq_printf(s, "\tover run\t%u\n", i2s->rxstats.overrun);
693 + seq_printf(s, "\tdma fault\t%u\n", i2s->rxstats.dmafault);
695 + ralink_i2s_dump_regs(i2s);
700 +static int ralink_i2s_stats_open(struct inode *inode, struct file *file)
702 + return single_open(file, ralink_i2s_stats_show, inode->i_private);
705 +static const struct file_operations ralink_i2s_stats_ops = {
706 + .open = ralink_i2s_stats_open,
708 + .llseek = seq_lseek,
709 + .release = single_release,
712 +static inline int ralink_i2s_debugfs_create(struct ralink_i2s *i2s)
714 + i2s->dbg_dir = debugfs_create_dir(dev_name(i2s->dev), NULL);
718 + i2s->dbg_stats = debugfs_create_file("stats", S_IRUGO,
719 + i2s->dbg_dir, i2s, &ralink_i2s_stats_ops);
720 + if (!i2s->dbg_stats) {
721 + debugfs_remove(i2s->dbg_dir);
728 +static inline void ralink_i2s_debugfs_remove(struct ralink_i2s *i2s)
730 + debugfs_remove(i2s->dbg_stats);
731 + debugfs_remove(i2s->dbg_dir);
734 +static inline int ralink_i2s_debugfs_create(struct ralink_i2s *i2s)
739 +static inline void ralink_i2s_debugfs_remove(struct ralink_i2s *i2s)
745 + * TODO: these refclk setup functions should use
746 + * clock framework instead. hardcode it now.
748 +static void rt3350_refclk_setup(void)
752 + /* set refclk output 12Mhz clock */
753 + data = rt_sysc_r32(0x2c);
754 + data |= (0x1 << 8);
755 + rt_sysc_w32(data, 0x2c);
758 +static void rt3883_refclk_setup(void)
762 + /* set refclk output 12Mhz clock */
763 + data = rt_sysc_r32(0x2c);
764 + data &= ~(0x3 << 13);
765 + data |= (0x1 << 13);
766 + rt_sysc_w32(data, 0x2c);
769 +static void rt3552_refclk_setup(void)
773 + /* set refclk output 12Mhz clock */
774 + data = rt_sysc_r32(0x2c);
775 + data &= ~(0xf << 8);
776 + data |= (0x3 << 8);
777 + rt_sysc_w32(data, 0x2c);
780 +static void mt7620_refclk_setup(void)
784 + /* set refclk output 12Mhz clock */
785 + data = rt_sysc_r32(0x2c);
786 + data &= ~(0x7 << 9);
788 + rt_sysc_w32(data, 0x2c);
791 +static void mt7621_refclk_setup(void)
795 + /* set refclk output 12Mhz clock */
796 + data = rt_sysc_r32(0x2c);
797 + data &= ~(0x1f << 18);
798 + data |= (0x19 << 18);
799 + data &= ~(0x1f << 12);
800 + data |= (0x1 << 12);
801 + data &= ~(0x7 << 9);
802 + data |= (0x5 << 9);
803 + rt_sysc_w32(data, 0x2c);
806 +static void mt7628_refclk_setup(void)
810 + /* set i2s and refclk digital pad */
811 + data = rt_sysc_r32(0x3c);
813 + rt_sysc_w32(data, 0x3c);
815 + /* Adjust REFCLK0's driving strength */
816 + data = rt_sysc_r32(0x1354);
817 + data &= ~(0x1 << 5);
818 + rt_sysc_w32(data, 0x1354);
819 + data = rt_sysc_r32(0x1364);
820 + data |= ~(0x1 << 5);
821 + rt_sysc_w32(data, 0x1364);
823 + /* set refclk output 12Mhz clock */
824 + data = rt_sysc_r32(0x2c);
825 + data &= ~(0x7 << 9);
827 + rt_sysc_w32(data, 0x2c);
830 +struct rt_i2s_data {
832 + void (*refclk_setup)(void);
835 +struct rt_i2s_data rt3050_i2s_data = { .flags = RALINK_FLAGS_TXONLY };
836 +struct rt_i2s_data rt3350_i2s_data = { .flags = RALINK_FLAGS_TXONLY,
837 + .refclk_setup = rt3350_refclk_setup };
838 +struct rt_i2s_data rt3883_i2s_data = {
839 + .flags = (RALINK_FLAGS_LEFT_J | RALINK_FLAGS_RIGHT_J),
840 + .refclk_setup = rt3883_refclk_setup };
841 +struct rt_i2s_data rt3352_i2s_data = { .refclk_setup = rt3552_refclk_setup};
842 +struct rt_i2s_data mt7620_i2s_data = { .refclk_setup = mt7620_refclk_setup};
843 +struct rt_i2s_data mt7621_i2s_data = { .refclk_setup = mt7621_refclk_setup};
844 +struct rt_i2s_data mt7628_i2s_data = {
845 + .flags = (RALINK_FLAGS_ENDIAN | RALINK_FLAGS_24BIT |
846 + RALINK_FLAGS_LEFT_J),
847 + .refclk_setup = mt7628_refclk_setup};
849 +static const struct of_device_id ralink_i2s_match_table[] = {
850 + { .compatible = "ralink,rt3050-i2s",
851 + .data = (void *)&rt3050_i2s_data },
852 + { .compatible = "ralink,rt3350-i2s",
853 + .data = (void *)&rt3350_i2s_data },
854 + { .compatible = "ralink,rt3883-i2s",
855 + .data = (void *)&rt3883_i2s_data },
856 + { .compatible = "ralink,rt3352-i2s",
857 + .data = (void *)&rt3352_i2s_data },
858 + { .compatible = "mediatek,mt7620-i2s",
859 + .data = (void *)&mt7620_i2s_data },
860 + { .compatible = "mediatek,mt7621-i2s",
861 + .data = (void *)&mt7621_i2s_data },
862 + { .compatible = "mediatek,mt7628-i2s",
863 + .data = (void *)&mt7628_i2s_data },
866 +MODULE_DEVICE_TABLE(of, ralink_i2s_match_table);
868 +static int ralink_i2s_probe(struct platform_device *pdev)
870 + const struct of_device_id *match;
871 + struct device_node *np = pdev->dev.of_node;
872 + struct ralink_i2s *i2s;
873 + struct resource *res;
876 + struct rt_i2s_data *data;
878 + i2s = devm_kzalloc(&pdev->dev, sizeof(*i2s), GFP_KERNEL);
882 + platform_set_drvdata(pdev, i2s);
883 + i2s->dev = &pdev->dev;
885 + match = of_match_device(ralink_i2s_match_table, &pdev->dev);
888 + data = (struct rt_i2s_data *)match->data;
889 + i2s->flags = data->flags;
890 + /* setup out 12Mhz refclk to codec as mclk */
891 + if (data->refclk_setup)
892 + data->refclk_setup();
894 + if (of_property_read_u32(np, "txdma-req", &dma_req)) {
895 + dev_err(&pdev->dev, "no txdma-req define\n");
898 + i2s->txdma_req = (u16)dma_req;
899 + if (!(i2s->flags & RALINK_FLAGS_TXONLY)) {
900 + if (of_property_read_u32(np, "rxdma-req", &dma_req)) {
901 + dev_err(&pdev->dev, "no rxdma-req define\n");
904 + i2s->rxdma_req = (u16)dma_req;
907 + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
908 + i2s->regs = devm_ioremap_resource(&pdev->dev, res);
909 + if (IS_ERR(i2s->regs))
910 + return PTR_ERR(i2s->regs);
912 + i2s->regmap = devm_regmap_init_mmio(&pdev->dev, i2s->regs,
913 + &ralink_i2s_regmap_config);
914 + if (IS_ERR(i2s->regmap)) {
915 + dev_err(&pdev->dev, "regmap init failed\n");
916 + return PTR_ERR(i2s->regmap);
919 + irq = platform_get_irq(pdev, 0);
921 + dev_err(&pdev->dev, "failed to get irq\n");
925 +#if (RALINK_I2S_INT_EN)
926 + ret = devm_request_irq(&pdev->dev, irq, ralink_i2s_irq,
927 + 0, dev_name(&pdev->dev), i2s);
929 + dev_err(&pdev->dev, "failed to request irq\n");
934 + i2s->clk = devm_clk_get(&pdev->dev, NULL);
935 + if (IS_ERR(i2s->clk)) {
936 + dev_err(&pdev->dev, "no clock defined\n");
937 + return PTR_ERR(i2s->clk);
940 + ret = clk_prepare_enable(i2s->clk);
944 + ralink_i2s_init_dma_data(i2s, res);
946 + ret = device_reset(&pdev->dev);
948 + dev_err(&pdev->dev, "failed to reset device\n");
949 + goto err_clk_disable;
952 + ret = ralink_i2s_debugfs_create(i2s);
954 + dev_err(&pdev->dev, "create debugfs failed\n");
955 + goto err_clk_disable;
958 + /* enable 24bits support */
959 + if (i2s->flags & RALINK_FLAGS_24BIT) {
960 + ralink_i2s_dai.capture.formats |= SNDRV_PCM_FMTBIT_S24_LE;
961 + ralink_i2s_dai.playback.formats |= SNDRV_PCM_FMTBIT_S24_LE;
964 + /* enable big endian support */
965 + if (i2s->flags & RALINK_FLAGS_ENDIAN) {
966 + ralink_i2s_dai.capture.formats |= SNDRV_PCM_FMTBIT_S16_BE;
967 + ralink_i2s_dai.playback.formats |= SNDRV_PCM_FMTBIT_S16_BE;
968 + ralink_pcm_hardware.formats |= SNDRV_PCM_FMTBIT_S16_BE;
969 + if (i2s->flags & RALINK_FLAGS_24BIT) {
970 + ralink_i2s_dai.capture.formats |=
971 + SNDRV_PCM_FMTBIT_S24_BE;
972 + ralink_i2s_dai.playback.formats |=
973 + SNDRV_PCM_FMTBIT_S24_BE;
974 + ralink_pcm_hardware.formats |=
975 + SNDRV_PCM_FMTBIT_S24_BE;
979 + /* disable capture support */
980 + if (i2s->flags & RALINK_FLAGS_TXONLY)
981 + memset(&ralink_i2s_dai.capture, sizeof(ralink_i2s_dai.capture),
984 + ret = devm_snd_soc_register_component(&pdev->dev, &ralink_i2s_component,
985 + &ralink_i2s_dai, 1);
989 + ret = devm_snd_dmaengine_pcm_register(&pdev->dev,
990 + &ralink_dmaengine_pcm_config,
991 + SND_DMAENGINE_PCM_FLAG_COMPAT);
995 + dev_info(i2s->dev, "mclk %luMHz\n", clk_get_rate(i2s->clk) / 1000000);
1000 + ralink_i2s_debugfs_remove(i2s);
1003 + clk_disable_unprepare(i2s->clk);
1008 +static int ralink_i2s_remove(struct platform_device *pdev)
1010 + struct ralink_i2s *i2s = platform_get_drvdata(pdev);
1012 + ralink_i2s_debugfs_remove(i2s);
1013 + clk_disable_unprepare(i2s->clk);
1018 +static struct platform_driver ralink_i2s_driver = {
1019 + .probe = ralink_i2s_probe,
1020 + .remove = ralink_i2s_remove,
1023 + .of_match_table = ralink_i2s_match_table,
1026 +module_platform_driver(ralink_i2s_driver);
1028 +MODULE_AUTHOR("Lars-Peter Clausen, <lars@metafoo.de>");
1029 +MODULE_DESCRIPTION("Ralink/MediaTek I2S driver");
1030 +MODULE_LICENSE("GPL");
1031 +MODULE_ALIAS("platform:" DRV_NAME);