1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
3 #include <dt-bindings/clock/rtl83xx-clk.h>
7 #define STRINGIZE(s) #s
8 #define LAN_LABEL(p, s) STRINGIZE(p ## s)
9 #define SWITCH_PORT_LABEL(n) LAN_LABEL(lan, n)
11 #define INTERNAL_PHY(n) \
12 phy##n: ethernet-phy@##n { \
14 compatible = "ethernet-phy-ieee802.3-c22"; \
18 #define EXTERNAL_PHY(n) \
19 phy##n: ethernet-phy@##n { \
21 compatible = "ethernet-phy-ieee802.3-c22"; \
24 #define EXTERNAL_SFP_PHY(n) \
25 phy##n: ethernet-phy@##n { \
26 compatible = "ethernet-phy-ieee802.3-c22"; \
32 #define EXTERNAL_SFP_PHY_FULL(n, s) \
33 phy##n: ethernet-phy@##n { \
34 compatible = "ethernet-phy-ieee802.3-c22"; \
39 #define SWITCH_PORT(n, s, m) \
42 label = SWITCH_PORT_LABEL(s) ; \
43 phy-handle = <&phy##n>; \
47 #define SWITCH_SFP_PORT(n, s, m) \
50 label = SWITCH_PORT_LABEL(s) ; \
51 phy-handle = <&phy##n>; \
63 compatible = "realtek,rtl839x-soc";
66 compatible = "fixed-clock";
68 clock-frequency = <25000000>;
71 ccu: clock-controller {
72 compatible = "realtek,rtl8390-clock";
75 clock-names = "ref_clk";
83 compatible = "mips,mips34Kc";
85 clocks = <&ccu CLK_CPU>;
86 operating-points-v2 = <&cpu_opp_table>;
90 compatible = "mips,mips34Kc";
92 clocks = <&ccu CLK_CPU>;
93 operating-points-v2 = <&cpu_opp_table>;
97 cpu_opp_table: opp-table-0 {
98 compatible = "operating-points-v2";
102 opp-hz = /bits/ 64 <425000000>;
105 opp-hz = /bits/ 64 <450000000>;
108 opp-hz = /bits/ 64 <475000000>;
111 opp-hz = /bits/ 64 <500000000>;
114 opp-hz = /bits/ 64 <525000000>;
117 opp-hz = /bits/ 64 <550000000>;
120 opp-hz = /bits/ 64 <575000000>;
123 opp-hz = /bits/ 64 <600000000>;
126 opp-hz = /bits/ 64 <625000000>;
129 opp-hz = /bits/ 64 <650000000>;
132 opp-hz = /bits/ 64 <675000000>;
135 opp-hz = /bits/ 64 <700000000>;
138 opp-hz = /bits/ 64 <725000000>;
141 opp-hz = /bits/ 64 <750000000>;
146 bootargs = "console=ttyS0,115200";
150 compatible = "mti,cpu-interrupt-controller";
151 #address-cells = <0>;
152 #interrupt-cells = <1>;
153 interrupt-controller;
157 compatible = "simple-bus";
158 #address-cells = <1>;
160 ranges = <0x0 0x18000000 0x10000>;
162 intc: interrupt-controller@3000 {
163 compatible = "realtek,rtl8390-intc", "realtek,rtl-intc";
164 reg = <0x3000 0x18>, <0x3018 0x18>;
165 interrupt-controller;
166 #interrupt-cells = <2>;
168 interrupt-parent = <&cpuintc>;
169 interrupts = <2>, <3>, <4>, <5>, <6>;
173 compatible = "realtek,rtl8380-spi";
174 reg = <0x1200 0x100>;
176 #address-cells = <1>;
181 compatible = "realtek,rtl8390-timer", "realtek,otto-timer";
182 reg = <0x3100 0x10>, <0x3110 0x10>, <0x3120 0x10>,
183 <0x3130 0x10>, <0x3140 0x10>;
185 interrupt-parent = <&intc>;
186 interrupts = <29 4>, <28 4>, <17 4>, <16 4>, <15 4>;
187 clocks = <&ccu CLK_LXB>;
191 compatible = "ns16550a";
192 reg = <0x2000 0x100>;
194 clocks = <&ccu CLK_LXB>;
196 interrupt-parent = <&intc>;
206 pinctrl-names = "default";
207 pinctrl-0 = <&enable_uart1>;
209 compatible = "ns16550a";
210 reg = <0x2100 0x100>;
212 clocks = <&ccu CLK_LXB>;
214 interrupt-parent = <&intc>;
225 gpio0: gpio-controller@3500 {
226 compatible = "realtek,rtl8390-gpio", "realtek,otto-gpio";
233 interrupt-controller;
234 #interrupt-cells = <2>;
235 interrupt-parent = <&intc>;
239 watchdog0: watchdog@3150 {
240 compatible = "realtek,rtl8390-wdt";
243 realtek,reset-mode = "soc";
245 clocks = <&ccu CLK_LXB>;
248 interrupt-parent = <&intc>;
249 interrupt-names = "phase1", "phase2";
250 interrupts = <19 4>, <18 4>;
256 compatible = "pinctrl-single";
257 reg = <0x1b000004 0x4>;
259 pinctrl-single,bit-per-mux;
260 pinctrl-single,register-width = <32>;
261 pinctrl-single,function-mask = <0x1>;
262 #pinctrl-cells = <2>;
264 enable_uart1: pinmux_enable_uart1 {
265 pinctrl-single,bits = <0x0 0x1 0x3>;
268 disable_jtag: pinmux_disable_jtag {
269 pinctrl-single,bits = <0x0 0x2 0x3>;
275 compatible = "pinctrl-single";
276 reg = <0x1b0000e4 0x4>;
278 pinctrl-single,bit-per-mux;
279 pinctrl-single,register-width = <32>;
280 pinctrl-single,function-mask = <0x1>;
281 #pinctrl-cells = <2>;
284 pinmux_disable_sys_led: disable_sys_led {
285 pinctrl-single,bits = <0x0 0x0 0x4000>;
289 ethernet0: ethernet@1b00a300 {
290 compatible = "realtek,rtl838x-eth";
291 reg = <0x1b00a300 0x100>;
293 interrupt-parent = <&intc>;
296 phy-mode = "internal";
304 sram0: sram@9f000000 {
305 compatible = "mmio-sram";
306 reg = <0x9f000000 0x18000>;
307 #address-cells = <1>;
309 ranges = <0 0x9f000000 0x18000>;
312 switch0: switch@1b000000 {
314 compatible = "realtek,rtl83xx-switch";
316 interrupt-parent = <&intc>;