target/linux/realtek/dts-5.15/rtl8382_apresia_aplgs120gtss.dts

   1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
   2
   3 #include "rtl838x.dtsi"
   4
   5 #include <dt-bindings/input/input.h>
   6 #include <dt-bindings/gpio/gpio.h>
   7 #include <dt-bindings/leds/common.h>
   8
   9 / {
  10         compatible = "apresia,aplgs120gtss", "realtek,rtl8382-soc";
  11         model = "APRESIA ApresiaLightGS120GT-SS";
  12
  13         aliases {
  14                 led-boot = &led_power;
  15                 led-failsafe = &led_power;
  16                 led-running = &led_power;
  17                 led-upgrade = &led_power;
  18         };
  19
  20         memory@0 {
  21                 device_type = "memory";
  22                 reg = <0x0 0x10000000>;
  23         };
  24
  25         leds {
  26                 compatible = "gpio-leds";
  27
  28                 led_power: led-0 {
  29                         gpios = <&gpio0 0 GPIO_ACTIVE_LOW>;
  30                         color = <LED_COLOR_ID_GREEN>;
  31                         function = LED_FUNCTION_POWER;
  32                 };
  33
  34                 led-1 {
  35                         gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
  36                         color = <LED_COLOR_ID_RED>;
  37                         function = LED_FUNCTION_FAULT;
  38                 };
  39
  40                 /* LED chip is soldered, but no hole on the case */
  41                 led-2 {
  42                         gpios = <&gpio1 36 GPIO_ACTIVE_LOW>;
  43                         color = <LED_COLOR_ID_GREEN>;
  44                 };
  45         };
  46
  47         keys {
  48                 compatible = "gpio-keys-polled";
  49                 poll-interval = <20>;
  50
  51                 reset {
  52                         label = "reset";
  53                         gpios = <&gpio1 33 GPIO_ACTIVE_LOW>;
  54                         linux,code = <KEY_RESTART>;
  55                 };
  56         };
  57
  58         gpio-restart {
  59                 compatible = "gpio-restart";
  60                 gpios = <&gpio1 34 GPIO_ACTIVE_LOW>;
  61                 open-source;
  62         };
  63
  64         gpio1: rtl8231-gpio {
  65                 compatible = "realtek,rtl8231-gpio";
  66                 #gpio-cells = <2>;
  67                 gpio-controller;
  68                 indirect-access-bus-id = <0>;
  69         };
  70
  71         i2c0: i2c-gpio-0 {
  72                 compatible = "i2c-gpio";
  73                 sda-gpios = <&gpio1 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
  74                 scl-gpios = <&gpio1 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
  75                 i2c-gpio,delay-us = <2>;
  76                 #address-cells = <1>;
  77                 #size-cells = <0>;
  78         };
  79
  80         i2c1: i2c-gpio-1 {
  81                 compatible = "i2c-gpio";
  82                 sda-gpios = <&gpio1 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
  83                 scl-gpios = <&gpio1 7 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
  84                 i2c-gpio,delay-us = <2>;
  85                 #address-cells = <1>;
  86                 #size-cells = <0>;
  87         };
  88
  89         i2c2: i2c-gpio-2 {
  90                 compatible = "i2c-gpio";
  91                 sda-gpios = <&gpio1 11 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
  92                 scl-gpios = <&gpio1 12 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
  93                 i2c-gpio,delay-us = <2>;
  94                 #address-cells = <1>;
  95                 #size-cells = <0>;
  96         };
  97
  98         i2c3: i2c-gpio-3 {
  99                 compatible = "i2c-gpio";
 100                 sda-gpios = <&gpio1 22 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 101                 scl-gpios = <&gpio1 23 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 102                 i2c-gpio,delay-us = <2>;
 103                 #address-cells = <1>;
 104                 #size-cells = <0>;
 105         };
 106
 107         /* 4x TX-Disable lines are provided by RTL8214FC */
 108         sfp0: sfp-p17 {
 109                 compatible = "sff,sfp";
 110                 i2c-bus = <&i2c1>;
 111                 los-gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
 112                 mod-def0-gpio = <&gpio1 8 GPIO_ACTIVE_LOW>;
 113         };
 114
 115         sfp1: sfp-p18 {
 116                 compatible = "sff,sfp";
 117                 i2c-bus = <&i2c0>;
 118                 los-gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>;
 119                 mod-def0-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>;
 120         };
 121
 122         sfp2: sfp-p19 {
 123                 compatible = "sff,sfp";
 124                 i2c-bus = <&i2c3>;
 125                 los-gpio = <&gpio1 25 GPIO_ACTIVE_HIGH>;
 126                 mod-def0-gpio = <&gpio1 24 GPIO_ACTIVE_LOW>;
 127         };
 128
 129         sfp3: sfp-p20 {
 130                 compatible = "sff,sfp";
 131                 i2c-bus = <&i2c2>;
 132                 los-gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>;
 133                 mod-def0-gpio = <&gpio1 13 GPIO_ACTIVE_LOW>;
 134         };
 135 };
 136
 137 &gpio0 {
 138         rtl8231_reset {
 139                 gpio-hog;
 140                 gpios = <1 GPIO_ACTIVE_HIGH>;
 141                 output-high;
 142                 line-name = "rtl8231-reset";
 143         };
 144 };
 145
 146 &spi0 {
 147         status = "okay";
 148
 149         flash@0 {
 150                 compatible = "jedec,spi-nor";
 151                 reg = <0>;
 152                 spi-max-frequency = <10000000>;
 153
 154                 partitions {
 155                         compatible = "fixed-partitions";
 156                         #address-cells = <1>;
 157                         #size-cells = <1>;
 158
 159                         partition@0 {
 160                                 label = "u-boot";
 161                                 reg = <0x0 0x80000>;
 162                                 read-only;
 163                         };
 164
 165                         partition@80000 {
 166                                 label = "u-boot-env";
 167                                 reg = <0x80000 0x40000>;
 168                         };
 169
 170                         partition@c0000 {
 171                                 label = "u-boot-env2";
 172                                 reg = <0xc0000 0x40000>;
 173                         };
 174
 175                         partition@100000 {
 176                                 compatible = "openwrt,uimage", "denx,uimage";
 177                                 label = "firmware";
 178                                 reg = <0x100000 0xe80000>;
 179                                 openwrt,ih-magic = <0x12345000>;
 180                         };
 181
 182                         partition@f80000 {
 183                                 label = "firmware2";
 184                                 reg = <0xf80000 0xe80000>;
 185                         };
 186
 187                         partition@1e00000 {
 188                                 label = "jffs2";
 189                                 reg = <0x1e00000 0x200000>;
 190                                 read-only;
 191                         };
 192                 };
 193         };
 194 };
 195
 196 &ethernet0 {
 197         mdio-bus {
 198                 compatible = "realtek,rtl838x-mdio";
 199                 regmap = <&ethernet0>;
 200                 #address-cells = <1>;
 201                 #size-cells = <0>;
 202
 203                 EXTERNAL_PHY(0)
 204                 EXTERNAL_PHY(1)
 205                 EXTERNAL_PHY(2)
 206                 EXTERNAL_PHY(3)
 207                 EXTERNAL_PHY(4)
 208                 EXTERNAL_PHY(5)
 209                 EXTERNAL_PHY(6)
 210                 EXTERNAL_PHY(7)
 211
 212                 INTERNAL_PHY(8)
 213                 INTERNAL_PHY(9)
 214                 INTERNAL_PHY(10)
 215                 INTERNAL_PHY(11)
 216                 INTERNAL_PHY(12)
 217                 INTERNAL_PHY(13)
 218                 INTERNAL_PHY(14)
 219                 INTERNAL_PHY(15)
 220
 221                 EXTERNAL_SFP_PHY_FULL(24, 0)
 222                 EXTERNAL_SFP_PHY_FULL(25, 1)
 223                 EXTERNAL_SFP_PHY_FULL(26, 2)
 224                 EXTERNAL_SFP_PHY_FULL(27, 3)
 225         };
 226 };
 227
 228 &switch0 {
 229         ports {
 230                 #address-cells = <1>;
 231                 #size-cells = <0>;
 232
 233                 SWITCH_PORT(0, 1, qsgmii)
 234                 SWITCH_PORT(1, 2, qsgmii)
 235                 SWITCH_PORT(2, 3, qsgmii)
 236                 SWITCH_PORT(3, 4, qsgmii)
 237                 SWITCH_PORT(4, 5, qsgmii)
 238                 SWITCH_PORT(5, 6, qsgmii)
 239                 SWITCH_PORT(6, 7, qsgmii)
 240                 SWITCH_PORT(7, 8, qsgmii)
 241
 242                 SWITCH_PORT(8, 9, internal)
 243                 SWITCH_PORT(9, 10, internal)
 244                 SWITCH_PORT(10, 11, internal)
 245                 SWITCH_PORT(11, 12, internal)
 246                 SWITCH_PORT(12, 13, internal)
 247                 SWITCH_PORT(13, 14, internal)
 248                 SWITCH_PORT(14, 15, internal)
 249                 SWITCH_PORT(15, 16, internal)
 250
 251                 SWITCH_PORT(24, 17, qsgmii)
 252                 SWITCH_PORT(25, 18, qsgmii)
 253                 SWITCH_PORT(26, 19, qsgmii)
 254                 SWITCH_PORT(27, 20, qsgmii)
 255
 256                 port@28 {
 257                         ethernet = <&ethernet0>;
 258                         reg = <28>;
 259                         phy-mode = "internal";
 260
 261                         fixed-link {
 262                                 speed = <1000>;
 263                                 full-duplex;
 264                         };
 265                 };
 266         };
 267 };