1 # SPDX-License-Identifier: GPL-2.0
4 $id: http://devicetree.org/schemas/timer/realtek,rtl8300-timer.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Realtek Timer Device Tree Bindings
10 - Markus Stockhausen <markus.stockhausen@gmx.de>
13 The Realtek SOCs of the RTL83XX and RTL93XX series have at least 5 known
14 timers with corresponding interrupt lines . Their speed is derived from the
15 Lexra Bus (LXB) by dividers. Each timer has a block of 4 control registers in
16 the address range 0xb800xxxx with following start offsets.
18 RTL83XX: 0x3100, 0x3110, 0x3120, 0x3130, 0x3140
19 RTL93XX: 0x3200, 0x3210, 0x3220, 0x3230, 0x3240
25 - realtek,rtl8380-timer
26 - realtek,rtl8390-timer
27 - realtek,rtl9300-timer
28 - const: realtek,otto-timer
34 List of timer register addresses.
40 List of timer interrupts.
51 additionalProperties: false
56 compatible = "realtek,rtl8380-timer", "realtek,otto-timer";
57 reg = <0x3100 0x10>, <0x3110 0x10>, <0x3120 0x10>,
58 <0x3130 0x10>, <0x3140 0x10>;
60 interrupt-parent = <&intc>;
61 interrupts = <29 4>, <28 4>, <17 4>, <16 4>, <15 4>;
62 clocks = <&ccu CLK_LXB>;
66 compatible = "realtek,rtl8390-timer", "realtek,otto-timer";
67 reg = <0x3100 0x10>, <0x3110 0x10>, <0x3120 0x10>,
68 <0x3130 0x10>, <0x3140 0x10>;
70 interrupt-parent = <&intc>;
71 interrupts = <29 4>, <28 4>, <17 4>, <16 4>, <15 4>;
72 clocks = <&ccu CLK_LXB>;
76 compatible = "realtek,rtl9300-timer", "realtek,otto-timer";
77 reg = <0x3200 0x10>, <0x3210 0x10>, <0x3220 0x10>,
78 <0x3230 0x10>, <0x3240 0x10>;
80 interrupt-parent = <&intc>;
81 interrupts = <7 4>, <8 4>, <9 4>, <10 4>, <11 4>;
82 clocks = <&ccu CLK_LXB>;