target/linux/realtek/files-5.10/arch/mips/rtl838x/prom.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * prom.c
   4  * Early intialization code for the Realtek RTL838X SoC
   5  *
   6  * based on the original BSP by
   7  * Copyright (C) 2006-2012 Tony Wu (tonywu@realtek.com)
   8  * Copyright (C) 2020 B. Koblitz
   9  *
  10  */
  11
  12 #include <linux/init.h>
  13 #include <linux/kernel.h>
  14 #include <linux/string.h>
  15 #include <linux/of_fdt.h>
  16 #include <linux/libfdt.h>
  17 #include <asm/bootinfo.h>
  18 #include <asm/addrspace.h>
  19 #include <asm/page.h>
  20 #include <asm/cpu.h>
  21 #include <asm/fw/fw.h>
  22 #include <asm/smp-ops.h>
  23 #include <asm/mips-cps.h>
  24
  25 #include <mach-rtl83xx.h>
  26
  27 extern char arcs_cmdline[];
  28 extern const char __appended_dtb;
  29
  30 struct rtl83xx_soc_info soc_info;
  31 const void *fdt;
  32
  33 #ifdef CONFIG_MIPS_MT_SMP
  34 extern const struct plat_smp_ops vsmp_smp_ops;
  35 static struct plat_smp_ops rtl_smp_ops;
  36
  37 static void rtl_init_secondary(void)
  38 {
  39 #ifndef CONFIG_CEVT_R4K
  40 /*
  41  * These devices are low on resources. There might be the chance that CEVT_R4K
  42  * is not enabled in kernel build. Nevertheless the timer and interrupt 7 might
  43  * be active by default after startup of secondary VPE. With no registered
  44  * handler that leads to continuous unhandeled interrupts. In this case disable
  45  * counting (DC) in the core and confirm a pending interrupt.
  46  */
  47         write_c0_cause(read_c0_cause() | CAUSEF_DC);
  48         write_c0_compare(0);
  49 #endif /* CONFIG_CEVT_R4K */
  50 /*
  51  * Enable all CPU interrupts, as everything is managed by the external
  52  * controller. TODO: Standard vsmp_init_secondary() has special treatment for
  53  * Malta if external GIC is available. Maybe we need this too.
  54  */
  55         if (mips_gic_present())
  56                 pr_warn("%s: GIC present. Maybe interrupt enabling required.\n", __func__);
  57         else
  58                 set_c0_status(ST0_IM);
  59 }
  60 #endif /* CONFIG_MIPS_MT_SMP */
  61
  62 const char *get_system_type(void)
  63 {
  64         return soc_info.name;
  65 }
  66
  67 void __init prom_free_prom_memory(void)
  68 {
  69
  70 }
  71
  72 void __init device_tree_init(void)
  73 {
  74         if (!fdt_check_header(&__appended_dtb)) {
  75                 fdt = &__appended_dtb;
  76                 pr_info("Using appended Device Tree.\n");
  77         }
  78         initial_boot_params = (void *)fdt;
  79         unflatten_and_copy_device_tree();
  80 }
  81
  82 void __init identify_rtl9302(void)
  83 {
  84         switch (sw_r32(RTL93XX_MODEL_NAME_INFO) & 0xfffffff0) {
  85         case 0x93020810:
  86                 soc_info.name = "RTL9302A 12x2.5G";
  87                 break;
  88         case 0x93021010:
  89                 soc_info.name = "RTL9302B 8x2.5G";
  90                 break;
  91         case 0x93021810:
  92                 soc_info.name = "RTL9302C 16x2.5G";
  93                 break;
  94         case 0x93022010:
  95                 soc_info.name = "RTL9302D 24x2.5G";
  96                 break;
  97         case 0x93020800:
  98                 soc_info.name = "RTL9302A";
  99                 break;
 100         case 0x93021000:
 101                 soc_info.name = "RTL9302B";
 102                 break;
 103         case 0x93021800:
 104                 soc_info.name = "RTL9302C";
 105                 break;
 106         case 0x93022000:
 107                 soc_info.name = "RTL9302D";
 108                 break;
 109         case 0x93023001:
 110                 soc_info.name = "RTL9302F";
 111                 break;
 112         default:
 113                 soc_info.name = "RTL9302";
 114         }
 115 }
 116
 117 void __init prom_init(void)
 118 {
 119         uint32_t model;
 120
 121         /* uart0 */
 122         setup_8250_early_printk_port(0xb8002000, 2, 0);
 123
 124         model = sw_r32(RTL838X_MODEL_NAME_INFO);
 125         pr_info("RTL838X model is %x\n", model);
 126         model = model >> 16 & 0xFFFF;
 127
 128         if ((model != 0x8328) && (model != 0x8330) && (model != 0x8332)
 129             && (model != 0x8380) && (model != 0x8382)) {
 130                 model = sw_r32(RTL839X_MODEL_NAME_INFO);
 131                 pr_info("RTL839X model is %x\n", model);
 132                 model = model >> 16 & 0xFFFF;
 133         }
 134
 135         if ((model & 0x8390) != 0x8380 && (model & 0x8390) != 0x8390) {
 136                 model = sw_r32(RTL93XX_MODEL_NAME_INFO);
 137                 pr_info("RTL93XX model is %x\n", model);
 138                 model = model >> 16 & 0xFFFF;
 139         }
 140
 141         soc_info.id = model;
 142
 143         switch (model) {
 144         case 0x8328:
 145                 soc_info.name = "RTL8328";
 146                 soc_info.family = RTL8328_FAMILY_ID;
 147                 break;
 148         case 0x8332:
 149                 soc_info.name = "RTL8332";
 150                 soc_info.family = RTL8380_FAMILY_ID;
 151                 break;
 152         case 0x8380:
 153                 soc_info.name = "RTL8380";
 154                 soc_info.family = RTL8380_FAMILY_ID;
 155                 break;
 156         case 0x8382:
 157                 soc_info.name = "RTL8382";
 158                 soc_info.family = RTL8380_FAMILY_ID;
 159                 break;
 160         case 0x8390:
 161                 soc_info.name = "RTL8390";
 162                 soc_info.family = RTL8390_FAMILY_ID;
 163                 break;
 164         case 0x8391:
 165                 soc_info.name = "RTL8391";
 166                 soc_info.family = RTL8390_FAMILY_ID;
 167                 break;
 168         case 0x8392:
 169                 soc_info.name = "RTL8392";
 170                 soc_info.family = RTL8390_FAMILY_ID;
 171                 break;
 172         case 0x8393:
 173                 soc_info.name = "RTL8393";
 174                 soc_info.family = RTL8390_FAMILY_ID;
 175                 break;
 176         case 0x9301:
 177                 soc_info.name = "RTL9301";
 178                 soc_info.family = RTL9300_FAMILY_ID;
 179                 break;
 180         case 0x9302:
 181                 identify_rtl9302();
 182                 soc_info.family = RTL9300_FAMILY_ID;
 183                 break;
 184         case 0x9303:
 185                 soc_info.name = "RTL9303";
 186                 soc_info.family = RTL9300_FAMILY_ID;
 187                 break;
 188         case 0x9313:
 189                 soc_info.name = "RTL9313";
 190                 soc_info.family = RTL9310_FAMILY_ID;
 191                 break;
 192         default:
 193                 soc_info.name = "DEFAULT";
 194                 soc_info.family = 0;
 195         }
 196
 197         pr_info("SoC Type: %s\n", get_system_type());
 198
 199         fw_init_cmdline();
 200
 201         mips_cpc_probe();
 202
 203         if (!register_cps_smp_ops())
 204                 return;
 205
 206 #ifdef CONFIG_MIPS_MT_SMP
 207         if (cpu_has_mipsmt) {
 208                 rtl_smp_ops = vsmp_smp_ops;
 209                 rtl_smp_ops.init_secondary = rtl_init_secondary;
 210                 register_smp_ops(&rtl_smp_ops);
 211                 return;
 212         }
 213 #endif
 214
 215         register_up_smp_ops();
 216 }